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path: root/llvm/lib/CodeGen/BranchFolding.cpp
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* Where the BranchFolding pass removes a branch then adds another better branch,Bill Wendling2012-03-071-4/+27
| | | | | | | | the DebugLoc information can be maintained throughout by grabbing the DebugLoc before the RemoveBranch and then passing the result to the InsertBranch. Patch by Andrew Stanford-Jason! llvm-svn: 152212
* Convert more GenRegisterInfo tables from unsigned to uint16_t to reduce ↵Craig Topper2012-03-051-2/+2
| | | | | | static data size. llvm-svn: 152016
* Use uint16_t to store register overlaps to reduce static data.Craig Topper2012-03-041-5/+5
| | | | llvm-svn: 152001
* Remove extra semi-colons.Chad Rosier2012-02-221-2/+2
| | | | llvm-svn: 151169
* Handle register masks in branch folding.Jakob Stoklund Olesen2012-02-151-0/+8
| | | | | | | Don't attempt to move instructions with regmask operands. They are most likely calls anyway. llvm-svn: 150634
* Move pass configuration out of pass constructors: BranchFolderPassAndrew Trick2012-02-081-12/+16
| | | | llvm-svn: 150095
* whitespaceAndrew Trick2012-02-081-2/+2
| | | | llvm-svn: 150094
* More dead code removal (using -Wunreachable-code)David Blaikie2012-01-201-1/+2
| | | | llvm-svn: 148578
* When hoisting common code, watch out for uses which are marked "kill". If theEvan Cheng2012-01-121-0/+5
| | | | | | | | | | | killed registers are needed below the insertion point, then unset the kill marker. Sorry I'm not able to find a reduced test case. rdar://10660944 llvm-svn: 148043
* Revert part of r147716. Looks like x87 instructions kill markers are all messedEvan Cheng2012-01-071-9/+11
| | | | | | | | | | up so branch folding pass can't use the scavenger. :-( This doesn't breaks anything currently. It just means targets which do not carefully update kill markers cannot run post-ra scheduler (not new, it has always been the case). We should fix this at some point since it's really hacky. llvm-svn: 147719
* Added a late machine instruction copy propagation pass. This catchesEvan Cheng2012-01-071-11/+9
| | | | | | | | | | | | | | | | | | | | | | | | opportunities that only present themselves after late optimizations such as tail duplication .e.g. ## BB#1: movl %eax, %ecx movl %ecx, %eax ret The register allocator also leaves some of them around (due to false dep between copies from phi-elimination, etc.) This required some changes in codegen passes. Post-ra scheduler and the pseudo-instruction expansion passes have been moved after branch folding and tail merging. They were before branch folding before because it did not always update block livein's. That's fixed now. The pass change makes independently since we want to properly schedule instructions after branch folding / tail duplication. rdar://10428165 rdar://10640363 llvm-svn: 147716
* - Add MachineInstrBundle.h and MachineInstrBundle.cpp. This includes a functionEvan Cheng2011-12-141-2/+3
| | | | | | | | | | to finalize MI bundles (i.e. add BUNDLE instruction and computing register def and use lists of the BUNDLE instruction) and a pass to unpack bundles. - Teach more of MachineBasic and MachineInstr methods to be bundle aware. - Switch Thumb2 IT block to MI bundles and delete the hazard recognizer hack to prevent IT blocks from being broken apart. llvm-svn: 146542
* Add bundle aware API for querying instruction properties and switch the codeEvan Cheng2011-12-071-8/+7
| | | | | | | | | | | | | | generator to it. For non-bundle instructions, these behave exactly the same as the MC layer API. For properties like mayLoad / mayStore, look into the bundle and if any of the bundled instructions has the property it would return true. For properties like isPredicable, only return true if *all* of the bundled instructions have the property. For properties like canFoldAsLoad, isCompare, conservatively return false for bundles. llvm-svn: 146026
* Reapply r142920 with fix:Bill Wendling2011-10-261-0/+3
| | | | | | | | | | | | An MBB which branches to an EH landing pad shouldn't be considered for tail merging. In SjLj EH, the jump to the landing pad is not done explicitly through a branch statement. The EH landing pad is added as a successor to the throwing BB. Because of that however, the branch folding pass could mistakenly think that it could merge the throwing BB with another BB. This isn't safe to do. <rdar://problem/10334833> llvm-svn: 143001
* Revert commit 142891. Takumi bisected the tablegen miscompilesDuncan Sands2011-10-251-2/+1
| | | | | | | | | | | | | | down to this commit. Original commit message: An MBB which branches to an EH landing pad shouldn't be considered for tail merging. In SjLj EH, the jump to the landing pad is not done explicitly through a branch statement. The EH landing pad is added as a successor to the throwing BB. Because of that however, the branch folding pass could mistakenly think that it could merge the throwing BB with another BB. This isn't safe to do. <rdar://problem/10334833> llvm-svn: 142920
* An MBB which branches to an EH landing pad shouldn't be considered for tail ↵Bill Wendling2011-10-251-1/+2
| | | | | | | | | | | | merging. In SjLj EH, the jump to the landing pad is not done explicitly through a branch statement. The EH landing pad is added as a successor to the throwing BB. Because of that however, the branch folding pass could mistakenly think that it could merge the throwing BB with another BB. This isn't safe to do. <rdar://problem/10334833> llvm-svn: 142891
* Fix liveness computations in BranchFolding.Jakob Stoklund Olesen2011-08-051-13/+16
| | | | | | | | | | | | | | | | | | | | | | | The old code would look at kills and defs in one pass over the instruction operands, causing problems with this code: %R0<def>, %CPSR<def,dead> = tLSLri %R5<kill>, 2, pred:14, pred:%noreg %R0<def>, %CPSR<def,dead> = tADDrr %R4<kill>, %R0<kill>, pred:14, %pred:%noreg The last instruction kills and redefines %R0, so it is still live after the instruction. This caused a register scavenger crash when compiling 483.xalancbmk for armv6. I am not including a test case because it requires too much bad luck to expose this old bug. First you need to convince the register allocator to use %R0 twice on the tADDrr instruction, then you have to convince BranchFolding to do something that causes it to run the register scavenger on he bad block. <rdar://problem/9898200> llvm-svn: 136973
* When tail-merging multiple blocks, make sure to correctly update the live-in ↵Eli Friedman2011-07-061-10/+21
| | | | | | | | | | list on the merged block to correctly account for the live-outs of all the predecessors. They might not be the same in all cases (the testcase I have involves a PHI node where one of the operands is an IMPLICIT_DEF). Unfortunately, the testcase I have is large and confidential, so I don't have a test to commit at the moment; I'll see if I can come up with something smaller where this issue reproduces. <rdar://problem/9716278> llvm-svn: 134565
* - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo andEvan Cheng2011-06-281-3/+3
| | | | | | | | sink them into MC layer. - Added MCInstrInfo, which captures the tablegen generated static data. Chang TargetInstrInfo so it's based off MCInstrInfo. llvm-svn: 134021
* Add 132986 back, but avoid non-determinism if a bb address gets reused.Rafael Espindola2011-06-141-5/+24
| | | | llvm-svn: 132995
* revert 132986 to see if the bots go green.Rafael Espindola2011-06-141-21/+5
| | | | llvm-svn: 132988
* Make the threshold used by branch folding softer. Before we would get aRafael Espindola2011-06-141-5/+21
| | | | | | | sharp all or nothing transition when one extra predecessor was added. Now we still test first ones for merging. llvm-svn: 132974
* Add comment.Devang Patel2011-05-261-0/+3
| | | | llvm-svn: 132149
* During branch folding avoid inserting redundant DBG_VALUE machine instructions.Devang Patel2011-05-261-0/+13
| | | | llvm-svn: 132148
* Update comment.Evan Cheng2011-05-121-2/+0
| | | | llvm-svn: 131258
* Re-enable branchfolding common code hoisting optimization. Fixed a liveness ↵Evan Cheng2011-05-121-13/+38
| | | | | | test bug and also taught it to update liveins. llvm-svn: 131241
* Temporarily disable the transformation. It's breaking 186.crafty in some ↵Evan Cheng2011-05-121-0/+4
| | | | | | configuration. llvm-svn: 131235
* Re-commit 131172 with fix. MachineInstr identity checks should check deadEvan Cheng2011-05-121-6/+263
| | | | | | | | | markers. In some cases a register def is dead on one path, but not on another. This is passing Clang self-hosting. llvm-svn: 131214
* Revert 131172 as it is causing clang to miscompile itself. I will tryRafael Espindola2011-05-111-261/+6
| | | | | | to provide a reduced testcase. llvm-svn: 131176
* Add a late optimization to BranchFolding that hoist common instruction sequencesEvan Cheng2011-05-111-6/+261
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | at the start of basic blocks to their common predecessor. It's actually quite common (e.g. about 50 times in JM/lencod) and has shown to be a nice code size benefit. e.g. pushq %rax testl %edi, %edi jne LBB0_2 ## BB#1: xorb %al, %al popq %rdx ret LBB0_2: xorb %al, %al callq _foo popq %rdx ret => pushq %rax xorb %al, %al testl %edi, %edi je LBB0_2 ## BB#1: callq _foo LBB0_2: popq %rdx ret rdar://9145558 llvm-svn: 131172
* Branch folding is folding a landing pad into a regular BB.Bill Wendling2011-04-221-1/+1
| | | | | | | | | | | | | | | An exception is thrown via a call to _cxa_throw, which we don't expect to return. Therefore, the "true" part of the invoke goes to a BB that has 'unreachable' as its only instruction. This is lowered into an empty MachineBB. The landing pad for this invoke, however, is directly after the "true" MBB. When the empty MBB is removed, the landing pad is directly below the BB with the invoke call. The unconditional branch is removed and then the two blocks are merged together. The testcase is too big for a regression test. <rdar://problem/9305728> llvm-svn: 129965
* Add more debugging output.Evan Cheng2011-02-211-2/+4
| | | | llvm-svn: 126158
* Reapply r110396, with fixes to appease the Linux buildbot gods.Owen Anderson2010-08-061-1/+1
| | | | llvm-svn: 110460
* Revert r110396 to fix buildbots.Owen Anderson2010-08-061-1/+1
| | | | llvm-svn: 110410
* Don't use PassInfo* as a type identifier for passes. Instead, use the ↵Owen Anderson2010-08-051-1/+1
| | | | | | | | address of the static ID member as the sole unique type identifier. Clean up APIs related to this change. llvm-svn: 110396
* Tail merging pass shall not break up IT blocks. rdar://8115404Evan Cheng2010-06-221-5/+18
| | | | llvm-svn: 106517
* Allow ARM if-converter to be run after post allocation scheduling.Evan Cheng2010-06-181-16/+2
| | | | | | | | | | | | | | | | - This fixed a number of bugs in if-converter, tail merging, and post-allocation scheduler. If-converter now runs branch folding / tail merging first to maximize if-conversion opportunities. - Also changed the t2IT instruction slightly. It now defines the ITSTATE register which is read by instructions in the IT block. - Added Thumb2 specific hazard recognizer to ensure the scheduler doesn't change the instruction ordering in the IT block (since IT mask has been finalized). It also ensures no other instructions can be scheduled between instructions in the IT block. This is not yet enabled. llvm-svn: 106344
* Add a DebugLoc parameter to TargetInstrInfo::InsertBranch(). ThisStuart Hastings2010-06-171-13/+18
| | | | | | | | | | | | addresses a longstanding deficiency noted in many FIXMEs scattered across all the targets. This effectively moves the problem up one level, replacing eleven FIXMEs in the targets with eight FIXMEs in CodeGen, plus one path through FastISel where we actually supply a DebugLoc, fixing Radar 7421831. llvm-svn: 106243
* Fix a bug which prevented tail merging of return instructions inDan Gohman2010-05-031-24/+5
| | | | | | | | | | | | | | | | | | | | beneficial cases. See the changes in test/CodeGen/X86/tail-opts.ll and test/CodeGen/ARM/ifcvt2.ll for details. The fix is to change HashEndOfMBB to hash at most one instruction, instead of trying to apply heuristics about when it will be profitable to consider more than one instruction. The regular tail-merging heuristics are already prepared to handle the same cases, and they're more precise. Also, make test/CodeGen/ARM/ifcvt5.ll and test/CodeGen/Thumb2/thumb2-branch.ll slightly more complex so that they continue to test what they're intended to test. And, this eliminates the problem in test/CodeGen/Thumb2/2009-10-15-ITBlockBranch.ll, the testcase from PR5204. Update it accordingly. llvm-svn: 102907
* Teach AnalyzeBranch, RemoveBranch and the branchDale Johannesen2010-04-021-3/+9
| | | | | | | folder to be tolerant of debug info following the branch(es) at the end of a block. llvm-svn: 100168
* Stop trying to merge identical jump tables. This had been inadvertentlyBob Wilson2010-03-191-28/+6
| | | | | | | | | | | disabled for several months (since svn r88806) and no one noticed. My fix for pr6543 yesterday reenabled it, but broke the ARM port's code for using TBB/TBH. Rather than adding a target hook to disable merging for Thumb2 only, I'm just taking this out. It is not common to have identical jump tables, the code we used to merge them was O(N^2), and it only helps code size, not performance. llvm-svn: 98977
* Remove a check that can no longer be true, after r84803.Bob Wilson2010-03-161-16/+0
| | | | llvm-svn: 98694
* eliminate InvalidateLabel and LabelIDList from MMI and replaceChris Lattner2010-03-141-11/+0
| | | | | | them with a counter. llvm-svn: 98462
* Fix another place where DEBUG_VALUE affected codegen.Dale Johannesen2010-03-101-1/+12
| | | | llvm-svn: 98181
* This survived a bootstrap, so let's try 98104 again.Dale Johannesen2010-03-101-4/+69
| | | | llvm-svn: 98137
* Speculatively revert 98104; could be what's causing crashesDale Johannesen2010-03-101-56/+3
| | | | llvm-svn: 98108
* Ever more complicated DEBUG_VALUE fixes for branch folding.Dale Johannesen2010-03-091-3/+56
| | | | llvm-svn: 98104
* Fix dbg value handling in tail merging.Dale Johannesen2010-03-081-3/+25
| | | | llvm-svn: 97938
* Fix some more places where dbg_value affected codegen.Dale Johannesen2010-03-051-1/+5
| | | | llvm-svn: 97765
* move target-independent opcodes out of TargetInstrInfoChris Lattner2010-02-091-2/+2
| | | | | | | | | into TargetOpcodes.h. #include the new TargetOpcodes.h into MachineInstr. Add new inline accessors (like isPHI()) to MachineInstr, and start using them throughout the codebase. llvm-svn: 95687
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