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* Remove special-casing of return blocks for liveness.Jakob Stoklund Olesen2013-02-051-17/+1
| | | | | | | Now that return value registers are return instruction uses, there is no need for special treatment of return blocks. llvm-svn: 174416
* Remove duplicate includes.Roman Divacky2012-12-211-1/+0
| | | | llvm-svn: 170902
* Use the new script to sort the includes of every file under lib.Chandler Carruth2012-12-031-4/+4
| | | | | | | | | | | | | | | | | Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] llvm-svn: 169131
* Use MCPhysReg for RegisterClassInfo allocation orders.Jakob Stoklund Olesen2012-11-291-1/+1
| | | | | | This saves a bit of memory. llvm-svn: 168852
* Remove RegisterClassInfo::isReserved() and isAllocatable().Jakob Stoklund Olesen2012-10-151-2/+2
| | | | | | Clients can use the equivalent functions in MRI. llvm-svn: 165990
* Move RegisterClassInfo.h.Andrew Trick2012-06-061-1/+1
| | | | | | Allow targets to access this API. It's required for RegisterPressure. llvm-svn: 158102
* Switch all register list clients to the new MC*Iterator interface.Jakob Stoklund Olesen2012-06-011-21/+16
| | | | | | | | | | | | | No functional change intended. Sorry for the churn. The iterator classes are supposed to help avoid giant commits like this one in the future. The TableGen-produced register lists are getting quite large, and it may be necessary to change the table representation. This makes it possible to do so without changing all clients (again). llvm-svn: 157854
* Add an MF argument to TRI::getPointerRegClass() and TII::getRegClass().Jakob Stoklund Olesen2012-05-071-2/+2
| | | | | | | | | | | | | The getPointerRegClass() hook can return register classes that depend on the calling convention of the current function (ptr_rc_tailcall). So far, we have been able to infer the calling convention from the subtarget alone, but as we add support for multiple calling conventions per target, that no longer works. Patch by Yiannis Tsiouris! llvm-svn: 156328
* Convert more GenRegisterInfo tables from unsigned to uint16_t to reduce ↵Craig Topper2012-03-051-2/+2
| | | | | | static data size. llvm-svn: 152016
* Use uint16_t to store register overlaps to reduce static data.Craig Topper2012-03-041-6/+6
| | | | llvm-svn: 152001
* Use uint16_t to store registers in callee saved register tables to reduce ↵Craig Topper2012-03-041-1/+1
| | | | | | size of static data. llvm-svn: 151996
* AggressiveAntiDepBreaker needs to skip debug values because a debug value ↵Hal Finkel2012-01-161-0/+3
| | | | | | does not have a corresponding SUnit llvm-svn: 148260
* Added a late machine instruction copy propagation pass. This catchesEvan Cheng2012-01-071-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | opportunities that only present themselves after late optimizations such as tail duplication .e.g. ## BB#1: movl %eax, %ecx movl %ecx, %eax ret The register allocator also leaves some of them around (due to false dep between copies from phi-elimination, etc.) This required some changes in codegen passes. Post-ra scheduler and the pseudo-instruction expansion passes have been moved after branch folding and tail merging. They were before branch folding before because it did not always update block livein's. That's fixed now. The pass change makes independently since we want to properly schedule instructions after branch folding / tail duplication. rdar://10428165 rdar://10640363 llvm-svn: 147716
* Add bundle aware API for querying instruction properties and switch the codeEvan Cheng2011-12-071-4/+4
| | | | | | | | | | | | | | generator to it. For non-bundle instructions, these behave exactly the same as the MC layer API. For properties like mayLoad / mayStore, look into the bundle and if any of the bundled instructions has the property it would return true. For properties like isPredicable, only return true if *all* of the bundled instructions have the property. For properties like canFoldAsLoad, isCompare, conservatively return false for bundles. llvm-svn: 146026
* Rename TargetSubtarget to TargetSubtargetInfo for consistency.Evan Cheng2011-07-011-1/+1
| | | | llvm-svn: 134259
* More refactoring. Move getRegClass from TargetOperandInfo to TargetInstrInfo.Evan Cheng2011-06-271-2/+2
| | | | llvm-svn: 133944
* Teach antidependency breakers to use RegisterClassInfo.Jakob Stoklund Olesen2011-06-161-12/+13
| | | | | | No functional change was intended. llvm-svn: 133202
* Update DBG_VALUEs while breaking anti dependencies.Devang Patel2011-06-021-9/+7
| | | | llvm-svn: 132487
* Fix a ton of comment typos found by codespell. Patch byChris Lattner2011-04-151-1/+1
| | | | | | Luis Felipe Strano Moraes! llvm-svn: 129558
* Simplify AggressiveAntiDepBreaker's use of register aliases.Jakob Stoklund Olesen2010-12-141-31/+14
| | | | llvm-svn: 121805
* Anti-dependency breaking needs to be careful not to use reserved regsJim Grosbach2010-09-021-0/+2
| | | | llvm-svn: 112832
* Use std::vector instead of TargetRegisterInfo::FirstVirtualRegister. This timeBill Wendling2010-07-151-5/+5
| | | | | | make sure to allocate enough space in the std::vector. llvm-svn: 108449
* Reserve a goodly amount of room for the vectors.Bill Wendling2010-07-151-2/+4
| | | | llvm-svn: 108448
* Use std::vector instead of TargetRegisterInfo::FirstVirtualRegister.Bill Wendling2010-07-151-10/+10
| | | | llvm-svn: 108440
* revert bill's patches in an attempt to fix the buildbot.Chris Lattner2010-07-151-12/+10
| | | | llvm-svn: 108419
* Fix headers.Bill Wendling2010-07-151-0/+1
| | | | llvm-svn: 108413
* Use std::vector instead of a hard-coded array. The length of that array couldBill Wendling2010-07-151-11/+12
| | | | | | get *very* large, but we only need it to be the size of the number of pregs. llvm-svn: 108412
* Convert the last use of getPhysicalRegisterRegClass and remove it.Rafael Espindola2010-07-121-1/+5
| | | | | | | | | | | | AggressiveAntiDepBreaker should not be using getPhysicalRegisterRegClass. An instruction might be using a register that can only be replaced with one from a subclass of getPhysicalRegisterRegClass. With this patch we use getMinimalPhysRegClass. This is correct, but conservative. We should check the uses of the register and select the largest register class that can be used in all of them. llvm-svn: 108122
* Make post-ra scheduling, anti-dep breaking, and register scavenger ↵Evan Cheng2010-06-161-21/+43
| | | | | | (conservatively) aware of predicated instructions. This enables ARM to move if-conversion before post-ra scheduler. llvm-svn: 106091
* Not all entries in the range will have an SUnit. Check for that when lookingJim Grosbach2010-06-021-0/+1
| | | | | | for debug information. llvm-svn: 105324
* Update debug information when breaking anti-dependencies. rdar://7759363Jim Grosbach2010-06-011-0/+12
| | | | llvm-svn: 105300
* Make BreakAntiDependencies' SUnits argument const, and make the BeginDan Gohman2010-04-191-19/+20
| | | | | | and End arguments by-value rather than by-reference. llvm-svn: 101830
* Tidy whitespace.Bob Wilson2010-04-091-9/+8
| | | | llvm-svn: 100904
* move target-independent opcodes out of TargetInstrInfoChris Lattner2010-02-091-4/+3
| | | | | | | | | into TargetOpcodes.h. #include the new TargetOpcodes.h into MachineInstr. Add new inline accessors (like isPHI()) to MachineInstr, and start using them throughout the codebase. llvm-svn: 95687
* 80 column and whitespace cleanupJim Grosbach2010-01-061-75/+84
| | | | llvm-svn: 92837
* Change errs() to dbgs().David Greene2009-12-241-59/+59
| | | | llvm-svn: 92093
* <rdar://problem/7453528>. Track only physical registers that are valid for ↵David Goodwin2009-12-091-12/+15
| | | | | | the target. llvm-svn: 90970
* <rdar://problem/6721894>. Allow multiple registers to be renamed together ↵David Goodwin2009-11-241-6/+0
| | | | | | (super and sub) if necessary to break an anti-dependence. llvm-svn: 89722
* Restructure code to allow renaming of multiple-register groups for anti-dep ↵David Goodwin2009-11-201-44/+73
| | | | | | breaking. llvm-svn: 89511
* Remove some old experimental code that is no longer needed. Remove ↵David Goodwin2009-11-201-62/+36
| | | | | | additional, speculative scheduling pass as its cost did not translate into significant performance improvement. Minor tweaks. llvm-svn: 89471
* Fix a couple of problems with maintaining liveness information for antidep ↵David Goodwin2009-11-191-17/+47
| | | | | | breaking. llvm-svn: 89404
* Allow target to specify regclass for which antideps will only be broken ↵David Goodwin2009-11-131-25/+95
| | | | | | along the critical path. llvm-svn: 88682
* Rename registers to break output dependencies in addition to anti-dependencies.David Goodwin2009-11-121-2/+3
| | | | llvm-svn: 87015
* Allow targets to specify register classes whose member registers should not ↵David Goodwin2009-11-101-1/+13
| | | | | | be renamed to break anti-dependencies. llvm-svn: 86628
* Fix bug in aggressive antidep breaking; liveness was not updated correctly ↵David Goodwin2009-11-051-10/+7
| | | | | | for regions that do not have antidep candidates. llvm-svn: 86172
* Replace std::map.at() with std::map[].David Goodwin2009-11-051-1/+1
| | | | llvm-svn: 86102
* Break anti-dependencies using free registers in a round-robin manner to ↵David Goodwin2009-11-051-16/+41
| | | | | | avoid introducing new anti-dependencies. llvm-svn: 86098
* Do a scheduling pass ignoring anti-dependencies to identify candidate ↵David Goodwin2009-11-031-10/+26
| | | | | | registers that should be renamed. llvm-svn: 85939
* Between scheduling regions, correctly maintain anti-dep breaking state so ↵David Goodwin2009-10-291-5/+7
| | | | | | that we don't incorrectly rename registers that span these regions. llvm-svn: 85537
* Fix a couple of bugs in aggressive anti-dep breaking.David Goodwin2009-10-291-36/+61
| | | | llvm-svn: 85522
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