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* Remove unnecessary TargetMachine.h includes.Eric Christopher2014-10-141-1/+0
| | | | llvm-svn: 219672
* Reduce double set lookups. NFC.Benjamin Kramer2014-10-101-6/+2
| | | | llvm-svn: 219505
* Have MachineFunction cache a pointer to the subtarget to make lookupsEric Christopher2014-08-051-3/+3
| | | | | | | | | | | shorter/easier and have the DAG use that to do the same lookup. This can be used in the future for TargetMachine based caching lookups from the MachineFunction easily. Update the MIPS subtarget switching machinery to update this pointer at the same time it runs. llvm-svn: 214838
* Remove the TargetMachine forwards for TargetSubtargetInfo basedEric Christopher2014-08-041-12/+7
| | | | | | information and update all callers. No functional change. llvm-svn: 214781
* Disable IsSub subregister assert. pr18663.Will Schmidt2014-07-311-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | This is a follow-up to the activity in the bug at http://llvm.org/bugs/show_bug.cgi?id=18663 . The underlying issue has to do with how the KILL pseudo-instruction is handled. I defer to Hal/Jakob/Uli for additional details and background. This will disable the (bad?) assert, add an associated fixme comment, and add a pair of tests. The code change and the pr18663-2.ll test are copied from the referenced bug. That test does not immediately fail in my environment, but I have added the pr18663.ll test which does. (Comment from Hal) to provide everyone else with some context, this assert was not bad when it was written. At that time, we only generated KILL pseudo instructions around subregister copies. This logic, unfortunately, had its own problems. In r199797, the relevant logic in MachineCopyPropagation was replaced to generate KILLs for other kinds of copies too. This change in semantics broke this now-problematic assumption in AggressiveAntiDepBreaker. The AggressiveAntiDepBreaker really needs a proper cleanup to deal with the change, but removing the assert (which just allows the function to return false) is a safe conservative behavior, and should do for the time being. llvm-svn: 214429
* [Modules] Remove potential ODR violations by sinking the DEBUG_TYPEChandler Carruth2014-04-221-1/+2
| | | | | | | | | | | | define below all header includes in the lib/CodeGen/... tree. While the current modules implementation doesn't check for this kind of ODR violation yet, it is likely to grow support for it in the future. It also removes one layer of macro pollution across all the included headers. Other sub-trees will follow. llvm-svn: 206837
* [C++11] More 'nullptr' conversion. In some cases just using a boolean check ↵Craig Topper2014-04-141-24/+23
| | | | | | instead of comparing to nullptr. llvm-svn: 206142
* Make consistent use of MCPhysReg instead of uint16_t throughout the tree.Craig Topper2014-04-041-1/+1
| | | | llvm-svn: 205610
* Fix the aggressive anti-dep breaker's subregister definition handlingHal Finkel2014-02-261-1/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The aggressive anti-dependency breaker scans instructions, bottom-up, within the scheduling region in order to find opportunities where register renaming can be used to break anti-dependencies. Unfortunately, the aggressive anti-dep breaker was treating a register definition as defining all of that register's aliases (including super registers). This behavior is incorrect when the super register is live and there are other definitions of subregisters of the super register. For example, given the following sequence: %CR2EQ<def> = CROR %CR3UN, %CR3UN<kill> %CR2GT<def> = IMPLICIT_DEF %X4<def> = MFOCRF8 %CR2 the analysis of the first subregister definition would work as expected: Anti: %CR2GT<def> = IMPLICIT_DEF Def Groups: CR2GT=g194->g0(via CR2) Antidep reg: CR2GT (zero group) Use Groups: but the analysis of the second one would not: Anti: %CR2EQ<def> = CROR %CR3UN, %CR3UN<kill> Def Groups: CR2EQ=g195 Antidep reg: CR2EQ Rename Candidates for Group g195: ... because, when processing the %CR2GT<def>, we'd mark all super registers of %CR2GT (%CR2 in this case) as defined. As a result, when processing %CR2EQ<def>, %CR2 no longer appears to be live, and %CR2EQ<def>'s group is not %unioned with the %CR2 group. I don't have an in-tree test case for this yet (and even if I did, I don't have a small one). llvm-svn: 202294
* Fix crash in AggressiveAntiDepBreaker with empty CriticalPathSetHal Finkel2013-09-121-1/+1
| | | | | | | | | | | | If no register classes are added to CriticalPathRCs, then the CriticalPathSet bitmask will be empty. In that case, ExcludeRegs must remain NULL or else this line will cause a segfault: } else if ((ExcludeRegs != NULL) && ExcludeRegs->test(AntiDepReg)) { I have no in-tree test case. llvm-svn: 190584
* Simplify logic now that r182490 is in place. No functional change intended.Chad Rosier2013-05-221-2/+2
| | | | llvm-svn: 182531
* Remove special-casing of return blocks for liveness.Jakob Stoklund Olesen2013-02-051-17/+1
| | | | | | | Now that return value registers are return instruction uses, there is no need for special treatment of return blocks. llvm-svn: 174416
* Remove duplicate includes.Roman Divacky2012-12-211-1/+0
| | | | llvm-svn: 170902
* Use the new script to sort the includes of every file under lib.Chandler Carruth2012-12-031-4/+4
| | | | | | | | | | | | | | | | | Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] llvm-svn: 169131
* Use MCPhysReg for RegisterClassInfo allocation orders.Jakob Stoklund Olesen2012-11-291-1/+1
| | | | | | This saves a bit of memory. llvm-svn: 168852
* Remove RegisterClassInfo::isReserved() and isAllocatable().Jakob Stoklund Olesen2012-10-151-2/+2
| | | | | | Clients can use the equivalent functions in MRI. llvm-svn: 165990
* Move RegisterClassInfo.h.Andrew Trick2012-06-061-1/+1
| | | | | | Allow targets to access this API. It's required for RegisterPressure. llvm-svn: 158102
* Switch all register list clients to the new MC*Iterator interface.Jakob Stoklund Olesen2012-06-011-21/+16
| | | | | | | | | | | | | No functional change intended. Sorry for the churn. The iterator classes are supposed to help avoid giant commits like this one in the future. The TableGen-produced register lists are getting quite large, and it may be necessary to change the table representation. This makes it possible to do so without changing all clients (again). llvm-svn: 157854
* Add an MF argument to TRI::getPointerRegClass() and TII::getRegClass().Jakob Stoklund Olesen2012-05-071-2/+2
| | | | | | | | | | | | | The getPointerRegClass() hook can return register classes that depend on the calling convention of the current function (ptr_rc_tailcall). So far, we have been able to infer the calling convention from the subtarget alone, but as we add support for multiple calling conventions per target, that no longer works. Patch by Yiannis Tsiouris! llvm-svn: 156328
* Convert more GenRegisterInfo tables from unsigned to uint16_t to reduce ↵Craig Topper2012-03-051-2/+2
| | | | | | static data size. llvm-svn: 152016
* Use uint16_t to store register overlaps to reduce static data.Craig Topper2012-03-041-6/+6
| | | | llvm-svn: 152001
* Use uint16_t to store registers in callee saved register tables to reduce ↵Craig Topper2012-03-041-1/+1
| | | | | | size of static data. llvm-svn: 151996
* AggressiveAntiDepBreaker needs to skip debug values because a debug value ↵Hal Finkel2012-01-161-0/+3
| | | | | | does not have a corresponding SUnit llvm-svn: 148260
* Added a late machine instruction copy propagation pass. This catchesEvan Cheng2012-01-071-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | opportunities that only present themselves after late optimizations such as tail duplication .e.g. ## BB#1: movl %eax, %ecx movl %ecx, %eax ret The register allocator also leaves some of them around (due to false dep between copies from phi-elimination, etc.) This required some changes in codegen passes. Post-ra scheduler and the pseudo-instruction expansion passes have been moved after branch folding and tail merging. They were before branch folding before because it did not always update block livein's. That's fixed now. The pass change makes independently since we want to properly schedule instructions after branch folding / tail duplication. rdar://10428165 rdar://10640363 llvm-svn: 147716
* Add bundle aware API for querying instruction properties and switch the codeEvan Cheng2011-12-071-4/+4
| | | | | | | | | | | | | | generator to it. For non-bundle instructions, these behave exactly the same as the MC layer API. For properties like mayLoad / mayStore, look into the bundle and if any of the bundled instructions has the property it would return true. For properties like isPredicable, only return true if *all* of the bundled instructions have the property. For properties like canFoldAsLoad, isCompare, conservatively return false for bundles. llvm-svn: 146026
* Rename TargetSubtarget to TargetSubtargetInfo for consistency.Evan Cheng2011-07-011-1/+1
| | | | llvm-svn: 134259
* More refactoring. Move getRegClass from TargetOperandInfo to TargetInstrInfo.Evan Cheng2011-06-271-2/+2
| | | | llvm-svn: 133944
* Teach antidependency breakers to use RegisterClassInfo.Jakob Stoklund Olesen2011-06-161-12/+13
| | | | | | No functional change was intended. llvm-svn: 133202
* Update DBG_VALUEs while breaking anti dependencies.Devang Patel2011-06-021-9/+7
| | | | llvm-svn: 132487
* Fix a ton of comment typos found by codespell. Patch byChris Lattner2011-04-151-1/+1
| | | | | | Luis Felipe Strano Moraes! llvm-svn: 129558
* Simplify AggressiveAntiDepBreaker's use of register aliases.Jakob Stoklund Olesen2010-12-141-31/+14
| | | | llvm-svn: 121805
* Anti-dependency breaking needs to be careful not to use reserved regsJim Grosbach2010-09-021-0/+2
| | | | llvm-svn: 112832
* Use std::vector instead of TargetRegisterInfo::FirstVirtualRegister. This timeBill Wendling2010-07-151-5/+5
| | | | | | make sure to allocate enough space in the std::vector. llvm-svn: 108449
* Reserve a goodly amount of room for the vectors.Bill Wendling2010-07-151-2/+4
| | | | llvm-svn: 108448
* Use std::vector instead of TargetRegisterInfo::FirstVirtualRegister.Bill Wendling2010-07-151-10/+10
| | | | llvm-svn: 108440
* revert bill's patches in an attempt to fix the buildbot.Chris Lattner2010-07-151-12/+10
| | | | llvm-svn: 108419
* Fix headers.Bill Wendling2010-07-151-0/+1
| | | | llvm-svn: 108413
* Use std::vector instead of a hard-coded array. The length of that array couldBill Wendling2010-07-151-11/+12
| | | | | | get *very* large, but we only need it to be the size of the number of pregs. llvm-svn: 108412
* Convert the last use of getPhysicalRegisterRegClass and remove it.Rafael Espindola2010-07-121-1/+5
| | | | | | | | | | | | AggressiveAntiDepBreaker should not be using getPhysicalRegisterRegClass. An instruction might be using a register that can only be replaced with one from a subclass of getPhysicalRegisterRegClass. With this patch we use getMinimalPhysRegClass. This is correct, but conservative. We should check the uses of the register and select the largest register class that can be used in all of them. llvm-svn: 108122
* Make post-ra scheduling, anti-dep breaking, and register scavenger ↵Evan Cheng2010-06-161-21/+43
| | | | | | (conservatively) aware of predicated instructions. This enables ARM to move if-conversion before post-ra scheduler. llvm-svn: 106091
* Not all entries in the range will have an SUnit. Check for that when lookingJim Grosbach2010-06-021-0/+1
| | | | | | for debug information. llvm-svn: 105324
* Update debug information when breaking anti-dependencies. rdar://7759363Jim Grosbach2010-06-011-0/+12
| | | | llvm-svn: 105300
* Make BreakAntiDependencies' SUnits argument const, and make the BeginDan Gohman2010-04-191-19/+20
| | | | | | and End arguments by-value rather than by-reference. llvm-svn: 101830
* Tidy whitespace.Bob Wilson2010-04-091-9/+8
| | | | llvm-svn: 100904
* move target-independent opcodes out of TargetInstrInfoChris Lattner2010-02-091-4/+3
| | | | | | | | | into TargetOpcodes.h. #include the new TargetOpcodes.h into MachineInstr. Add new inline accessors (like isPHI()) to MachineInstr, and start using them throughout the codebase. llvm-svn: 95687
* 80 column and whitespace cleanupJim Grosbach2010-01-061-75/+84
| | | | llvm-svn: 92837
* Change errs() to dbgs().David Greene2009-12-241-59/+59
| | | | llvm-svn: 92093
* <rdar://problem/7453528>. Track only physical registers that are valid for ↵David Goodwin2009-12-091-12/+15
| | | | | | the target. llvm-svn: 90970
* <rdar://problem/6721894>. Allow multiple registers to be renamed together ↵David Goodwin2009-11-241-6/+0
| | | | | | (super and sub) if necessary to break an anti-dependence. llvm-svn: 89722
* Restructure code to allow renaming of multiple-register groups for anti-dep ↵David Goodwin2009-11-201-44/+73
| | | | | | breaking. llvm-svn: 89511
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