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* canFoldMergeOpcode returns a bool result not an unsigned. NFCI.Simon Pilgrim2019-11-071-2/+2
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* [XCOFF] Add back extern template declarationsReid Kleckner2019-11-071-0/+6
| | | | | The extern template declarations were fine. The duplicate explicit instantiations were both in the .cpp file.
* Revert "[XCOFF] Fix link errors from explicit template instantiation"Reid Kleckner2019-11-071-6/+0
| | | | | | | | This reverts commit c989993ba1a666f04f7aee7df51d9f4de0588b71. maskray already fixed the explicit instantiation definition in the .cpp file, and these extern template declarations seem to be causing warnings that I don't understand.
* [XCOFF] Fix link errors from explicit template instantiationReid Kleckner2019-11-071-0/+6
| | | | | | | | | | | | | | | | I happen to be using clang-cl+lld-link locally, and I get these link errors: lld-link: error: undefined symbol: public: unsigned short __cdecl llvm::object::XCOFFSectionHeader<struct llvm::object::XCOFFSectionHeader64>::getSectionType(void) const >>> referenced by C:\src\llvm-project\llvm\tools\llvm-readobj\XCOFFDumper.cpp:106 >>> tools\llvm-readobj\CMakeFiles\llvm-readobj.dir\XCOFFDumper.cpp.obj:(public: virtual void __cdecl `anonymous namespace'::XCOFFDumper::printSectionHeaders(void)) I suspect this is because the explicit template instaniation appears before the inline method definitions in the .cpp file, so they aren't available at the point of instantiation. Move the explicit instantiation later. Also, forward declare the explicit instantiation for good measure.
* MachineMemOperand::getBaseAlignment() - fix "shift of i32 then extended to ↵Simon Pilgrim2019-11-071-1/+1
| | | | i64" static analyzer warning. NFCI.
* TypeRecord - fix uninitialized variable warnings. NFCI.Simon Pilgrim2019-11-071-26/+26
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* Using crtp to refactor the xcoff section headerdiggerlin2019-11-071-6/+15
| | | | | | | | | | | | | SUMMARY: According to https://reviews.llvm.org/D68575#inline-617586, Create a NFC patch for it. Using crtp to refactor the xcoff section header Move the define of SectionFlagsReservedMask and SectionFlagsTypeMask from XCOFFDumper.cpp to XCOFFObjectFile.h Reviewers: hubert.reinterpretcast,jasonliu Subscribers: rupprecht, seiyai,hiraditya Differential Revision: https://reviews.llvm.org/D69131
* Add support for options -frounding-math, ftrapping-math, -ffp-model=, and ↵Melanie Blower2019-11-071-1/+1
| | | | | | | | | | | | -ffp-exception-behavior= Add options to control floating point behavior: trapping and exception behavior, rounding, and control of optimizations that affect floating point calculations. More details in UsersManual.rst. Reviewers: rjmccall Differential Revision: https://reviews.llvm.org/D62731
* SampleProfWriter - fix uninitialized variable warnings. NFCI.Simon Pilgrim2019-11-071-2/+2
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* [ThinLTO] Import readonly vars with refsevgeny2019-11-071-9/+20
| | | | | | Patch allows importing declarations of functions and variables, referenced by the initializer of some other readonly variable. Differential revision: https://reviews.llvm.org/D69561
* [SLP] allow forming 2-way reduction patternsSanjay Patel2019-11-071-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | We have a vector compare reduction problem seen in PR39665 comment 2: https://bugs.llvm.org/show_bug.cgi?id=39665#c2 Or slightly reduced here: define i1 @cmp2(<2 x double> %a0) { %a = fcmp ogt <2 x double> %a0, <double 1.0, double 1.0> %b = extractelement <2 x i1> %a, i32 0 %c = extractelement <2 x i1> %a, i32 1 %d = and i1 %b, %c ret i1 %d } SLP would not attempt to turn this into a vector reduction because there is an artificial lower limit on that transform. We can not completely remove that limit without inducing regressions though, so this patch just hacks an extra attempt at creating a 2-way reduction to the end of the analysis. As shown in the test file, we are still not getting some of the motivating cases, so follow-on patches will be needed to solve those cases. Differential Revision: https://reviews.llvm.org/D59710
* Temporarily Revert "[LV] Apply sink-after & interleave-groups as VPlan ↵Eric Christopher2019-11-061-3/+6
| | | | | | | | transformations (NFC)" as it's causing assert failures. This reverts commit 100e797adb433724a17c9b42b6533cd634cb796b.
* [AArch64][SVE] Add remaining patterns and intrinsics for add/sub/mad patternsDanilo Carvalho Grael2019-11-061-1/+31
| | | | | | | | | | | Add pattern matching and intrinsics for the following instructions: predicated orr, eor, and, bic predicated mul, smulh, umulh, sdiv, udiv, sdivr, udivr predicated smax, umax, smin, umin, sabd, uabd mad, msb, mla, mls https://reviews.llvm.org/D69588
* Temporarily Revert:Eric Christopher2019-11-061-1/+1
| | | | | | | | | | | | | | | | | "[SLP] Generalization of stores vectorization." "[SLP] Fix -Wunused-variable. NFC" "[SLP] Vectorize jumbled stores." As they're causing significant (10-30x) compile time regressions on vectorizable code. The primary cause of the compile-time regression is f228b5371647f471853c5fb3e6719823a42fe451. This reverts commits: f228b5371647f471853c5fb3e6719823a42fe451 5503455ccb3f5fcedced158332c016c8d3a7fa81 21d498c9c0f32dcab5bc89ac593aa813b533b43a
* [ConstantRange] Add `subWithNoWrap()` methodRoman Lebedev2019-11-071-0/+8
| | | | | | | | | | | | | | | | | | | | | Summary: Much like D67339, adds ConstantRange handling for when we know no-wrap behavior of the `sub`. Unlike addWithNoWrap(), we only get lucky re returning empty set for signed wrap. For unsigned, we must perform overflow check manually. A patch that makes use of this in LVI (CVP) to be posted later. Reviewers: nikic, shchenz, efriedma Reviewed By: nikic Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D69918
* [JITLink] Refactor EH-frame handling to support eh-frames with existing relocs.Lang Hames2019-11-061-28/+163
| | | | | | | | | | | | | | | | | | Some targets (E.g. MachO/arm64) use relocations to fix some CFI record fields in the eh-frame section. When relocations are used the initial (pre-relocation) content of the eh-frame section can no longer be interpreted by following the eh-frame specification. This causes errors in the existing eh-frame parser. This patch moves eh-frame handling into two LinkGraph passes that are run after relocations have been parsed (but before they are applied). The first] pass breaks up blocks in the eh-frame section into per-CFI-record blocks, and the second parses blocks of (potentially multiple) CFI records and adds the appropriate edges to any CFI fields that do not have existing relocations. These passes can be run independently of one another. By handling eh-frame splitting/fixing with LinkGraph passes we can both re-use existing relocations for CFI record fields and avoid applying eh-frame fixups before parsing the section (which would complicate the linker and require extra temporary allocations of working memory).
* [JumpThreading] Factor out code to clone instructions (NFC)Kazu Hirata2019-11-061-0/+4
| | | | | | | | | | | | | | Summary: This patch factors out code to clone instructions -- partly for readability and partly to facilitate an upcoming patch of my own. Reviewers: wmi Subscribers: hiraditya, jfb, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D69861
* [GISel][ArtifactCombiner] Relax the constraint to combine unmerge with ↵Quentin Colombet2019-11-061-25/+51
| | | | | | | | | | | | | | | concat_vectors The combine G_UNMERGE_VALUES with G_CONCAT_VECTORS used to only be performed when the result type of the G_UNMERGE_VALUES was a vector type. In other words, we were expecting that the G_UNMERGE_VALUES was effectively the exact opposite of the G_CONCAT_VECTORS. Lift that constraint by allowing any G_UNMERGE_VALUES to be combined with any G_CONCAT_VECTORS (as long as the size of the different pieces that we merge/unmerge match). Differential Revision: https://reviews.llvm.org/D69288
* LoopAccessAnalysis - fix uninitialized variable warnings. NFCI.Simon Pilgrim2019-11-061-7/+7
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* BranchProbabilityInfo - fix uninitialized variable warning. NFCI.Simon Pilgrim2019-11-061-1/+1
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* DWARFDebugLoclists: Move to a incremental parsing modelPavel Labath2019-11-062-33/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This patch stems from the discussion D68270 (including some offline talks). The idea is to provide an "incremental" api for parsing location lists, which will avoid caching or materializing parsed data. An additional goal is to provide a high level location list api, which abstracts the differences between different encoding schemes, and can be used by users which don't care about those (such as LLDB). This patch implements the first part. It implements a call-back based "visitLocationList" api. This function parses a single location list, calling a user-specified callback for each entry. This is going to be the base api, which other location list functions (right now, just the dumping code) are going to be based on. Future patches will do something similar for the v4 location lists, and add a mechanism to translate raw entries into concrete address ranges. Reviewers: dblaikie, probinson, JDevlieghere, aprantl, SouraVX Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D69672
* [NFC][APInt] Fix typos in comments.Miloš Stojanović2019-11-061-4/+4
| | | | Testing git commit access.
* [APInt] Fix implicit truncation warning in bitsToFloat(). NFCI.Simon Pilgrim2019-11-061-2/+2
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* [TTI][LV] preferPredicateOverEpilogueSjoerd Meijer2019-11-063-0/+34
| | | | | | | | | | | | | | | | | We have two ways to steer creating a predicated vector body over creating a scalar epilogue. To force this, we have 1) a command line option and 2) a pragma available. This adds a third: a target hook to TargetTransformInfo that can be queried whether predication is preferred or not, which allows the vectoriser to make the decision without forcing it. While this change behaves as a non-functional change for now, it shows the required TTI plumbing, usage of this new hook in the vectoriser, and the beginning of an ARM MVE implementation. I will follow up on this with: - a complete MVE implementation, see D69845. - a patch to disable this, i.e. we should respect "vector_predicate(disable)" and its corresponding loophint. Differential Revision: https://reviews.llvm.org/D69040
* [ARM,MVE] Add intrinsics for gather/scatter load/stores.Simon Tatham2019-11-061-9/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds two new families of intrinsics, both of which are memory accesses taking a vector of locations to load from / store to. The vldrq_gather_base / vstrq_scatter_base intrinsics take a vector of base addresses, and an immediate offset to be added consistently to each one. vldrq_gather_offset / vstrq_scatter_offset take a scalar base address, and a vector of offsets to add to it. The 'shifted_offset' variants also multiply each offset by the element size type, so that the vector is effectively of array indices. At the IR level, these operations are represented by a single set of four IR intrinsics: {gather,scatter} × {base,offset}. The other details (signed/unsigned, shift, and memory element size as opposed to vector element size) are all specified by IR intrinsic polymorphism and immediate operands, because that made the selection job easier than making a huge family of similarly named intrinsics. I considered using the standard IR representations such as llvm.masked.gather, but they're not a good fit. In order to use llvm.masked.gather to represent a gather_offset load with element size smaller than a pointer, you'd have to expand the <8 x i16> vector of offsets into an <8 x i16*> vector of pointers, which would be split up during legalization, so you'd spend most of your time undoing the mess it had made. Also, ISel support for llvm.masked.gather would be easy enough in a trivial way (you can expand it into a gather-base load with a zero immediate offset), but instruction-selecting lots of fiddly idioms back into all the _other_ MVE load instructions would be much more work. So I think dedicated IR intrinsics are the more sensible approach, at least for the moment. On the clang tablegen side, I've added two new features to the Tablegen source accepted by MveEmitter: a 'CopyKind' type node for defining a type that varies with the parameter type (it lets you ask for an unsigned integer type of the same width as the parameter), and an 'unsignedflag' value node for passing an immediate IR operand which is 0 for a signed integer type or 1 for an unsigned one. That lets me write each kind of intrinsic just once and get all its subtypes and immediate arguments generated automatically. Also I've tweaked the handling of pointer-typed values in the code generation part of MveEmitter: they're generated as Address rather than Value (i.e. including an alignment) so that they can be given to the ordinary IR load and store operations, but I'd omitted the code to convert them back to Value when they're going to be used as an argument to an IR intrinsic. On the MC side, I've enhanced MVEVectorVTInfo so that it can tell you not only the full assembly-language suffix for a given vector type (like 's32' or 'u16') but also the numeric-only one used by store instructions (just '32' or '16'). Reviewers: dmgreen Subscribers: kristof.beyls, hiraditya, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D69791
* [ADT] Add equality operator for SmallPtrSetYevgeny Rouban2019-11-061-0/+26
| | | | | Reviewed By: tellenbach Differential Revision: https://reviews.llvm.org/D69429
* [globalisel][docs] Rework GMIR documentation and add an early GenericOpcode ↵Daniel Sanders2019-11-052-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | reference Summary: Rework the GMIR documentation to focus more on the end user than the implementation and tie it in to the MIR document. There was also some out-of-date information which has been removed. The quality of the GenericOpcode reference is highly variable and drops sharply as I worked through them all but we've got to start somewhere :-). It would be great if others could expand on this too as there is an awful lot to get through. Also fix a typo in the definition of G_FLOG. Previously, the comments said we had two base-2's (G_FLOG and G_FLOG2). Reviewers: aemerson, volkan, rovka, arsenm Reviewed By: rovka Subscribers: wdng, arphaman, jfb, Petar.Avramovic, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D69545
* [Automaton] Make Automaton thread-safeJames Molloy2019-11-051-1/+11
| | | | | | | | | | In an optimization to improve performance (rL375240) we added a std::shared_ptr around the main table map. This is safe, but we also ended up making the transcriber object a std::shared_ptr too. This has mutable state, so must be copied when we copy the Automaton object. This is very cheap; the main optimization was about the map `M` only. Reported by Dan Palermo. No test as triggering this is rather hard from a unit test.
* [llvm-objdump] Fix spurious "The end of the file was unexpectedly ↵Sid Manning2019-11-051-0/+2
| | | | | | | | | | | | | | | | | | | | | encountered" if a SHT_NOBITS sh_offset is larger than the file size llvm-objdump -D this file: int a[100000]; int main() { return 0; } Will produce an error: "The end of the file was unexpectedly encountered". This happens because of a check in Binary.h checkOffset. (Addr + Size > M.getBufferEnd()). The sh_offset and sh_size fields can be ignored for SHT_NOBITS sections. Fix the error by changing ELFObjectFile<ELFT>::getSectionContents to use the file base for SHT_NOBITS sections. Reviewed By: grimar, MaskRay Differential Revision: https://reviews.llvm.org/D69192
* [globalisel] Rename G_GEP to G_PTR_ADDDaniel Sanders2019-11-056-17/+17
| | | | | | | | | | | | | | | | Summary: G_GEP is rather poorly named. It's a simple pointer+scalar addition and doesn't support any of the complexities of getelementptr. I therefore propose that we rename it. There's a G_PTR_MASK so let's follow that convention and go with G_PTR_ADD Reviewers: volkan, aditya_nandakumar, bogner, rovka, arsenm Subscribers: sdardis, jvesely, wdng, nhaehnle, hiraditya, jrtc27, atanasyan, arphaman, Petar.Avramovic, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D69734
* [JumpThreading] Factor out code to merge basic blocks (NFC)Kazu Hirata2019-11-051-0/+1
| | | | | | | | | | | | | | | Summary: This patch factors out code to merge a basic block with its sole successor -- partly for readability and partly to facilitate an upcoming patch of my own. Reviewers: wmi Subscribers: hiraditya, jfb, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D69852
* [DFAPacketizer] Allow up to 64 functional unitsjmolloy2019-11-051-38/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: To drive the automaton we used a uint64_t as an action type. This contained the transition's resource requirements as a conjunction: (a OR b) AND (b OR c) We encoded this conjunction as a sequence of four 16-bit bitmasks. This limited the number of addressable functional units to 16, which is quite low and has bitten many people in the past. Instead, the DFAEmitter now generates a lookup table from InstrItinerary class (index of the ItinData inside the ProcItineraries) to an internal action index which is essentially a dense embedding of the conjunctive form. Because we never materialize the conjunctive form, we no longer have the 16 FU restriction. In this patch we limit to 64 functional units due to using a uint64_t bitmask in the DFAEmitter. Now that we've decoupled these representations we can increase this in future. Reviewers: ThomasRaoux, kparzysz, majnemer Reviewed By: ThomasRaoux Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D69110
* [LV] Apply sink-after & interleave-groups as VPlan transformations (NFC)Gil Rapaport2019-11-051-6/+3
| | | | | | | This recommits 2be17087f8c38934b7fc9208ae6cf4e9b4d44f4b (reverted in d3ec06d219788801380af1948c7f7ef9d3c6100b for heap-use-after-free) with a fix in IAI's reset() which was not clearing the set of interleave groups after deleting them.
* Fix uninitialized variable warning. NFCI.Simon Pilgrim2019-11-051-1/+1
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* [MCObjectFileInfo] Fix uninitialized variable warnings. NFCI.Simon Pilgrim2019-11-051-88/+89
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* [MachineOutliner] Fix uninitialized variable warnings. NFCI.Simon Pilgrim2019-11-051-6/+6
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* [JumpThreading] Factor out common code to update the SSA form (NFC)Kazu Hirata2019-11-051-0/+2
| | | | | | | | | | | | | | | Summary: This patch factors out common code to update the SSA form in JumpThreading.cpp -- partly for readability and partly to facilitate an coming patch of my own. Reviewers: wmi Subscribers: hiraditya, jfb, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D69811
* [GVN] Fix uninitialized variable warnings. NFCI.Simon Pilgrim2019-11-051-11/+11
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* Add missing GVN =operator. NFCI.Simon Pilgrim2019-11-051-0/+1
| | | | Fixes PVS Studio warning that the 'ValueTable' class implements a copy constructor, but lacks the '=' operator.
* [Scheduling][ARM] Consistently enable PostRA Machine schedulingDavid Green2019-11-051-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | In the ARM backend, for historical reasons we have only some targets using Machine Scheduling. The rest use the old list scheduler as they are using itinaries and the list scheduler seems to produce better code (and not crash running out of register on v6m codes). So whether to use the MIScheduler or not is checked at runtime from the subtarget features. This is fine, except for post-ra scheduling. Whether to use the old post-ra list scheduler or the post-ra machine schedule is decided as the pass manager is set up, in arms case from a newly constructed subtarget. Under some situations, like LTO, this won't include the correct cpu so can pick the wrong option. This can have a surprising effect on performance. To fix that, this patch overrides targetSchedulesPostRAScheduling and addPreSched2 in the ARM backend, adding _both_ post-ra schedulers and picking at runtime which to execute. To pick between the two I've had to add a enablePostRAMachineScheduler() method that normally returns enableMachineScheduler() && enablePostRAScheduler(), which can be overridden to enable just one of PostRAMachineScheduler vs PostRAScheduler. Thanks to David Penry for the identifying this problem. Differential Revision: https://reviews.llvm.org/D69775
* DWARFDebugLoclists: Make it possible to read relocated addressesPavel Labath2019-11-051-4/+5
| | | | | | | | | | | | | | | | | Summary: Handling relocations was not needed when the loclists section was a DWO-only thing. But since DWARF5, it is possible to use it in regular objects too, and the standard permits embedding addresses into the section directly. These addresses need to be relocated in unlinked files. Reviewers: JDevlieghere, dblaikie, probinson Subscribers: aprantl, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D68271
* [IR] Add Freeze instructionaqjune2019-11-057-67/+103
| | | | | | | | | | | | | | | | | | Summary: - Define Instruction::Freeze, let it be UnaryOperator - Add support for freeze to LLLexer/LLParser/BitcodeReader/BitcodeWriter The format is `%x = freeze <ty> %v` - Add support for freeze instruction to llvm-c interface. - Add m_Freeze in PatternMatch. - Erase freeze when lowering IR to SelDag. Reviewers: deadalnix, hfinkel, efriedma, lebedev.ri, nlopes, jdoerfert, regehr, filcab, delcypher, whitequark Reviewed By: lebedev.ri, jdoerfert Subscribers: jfb, kristof.beyls, hiraditya, lebedev.ri, steven_wu, dexonsmith, xbolva00, delcypher, spatel, regehr, trentxintong, vsk, filcab, nlopes, mehdi_amini, deadalnix, llvm-commits Differential Revision: https://reviews.llvm.org/D29011
* [demangle] NFC: get rid of NodeOrStringErik Pilkington2019-11-041-55/+19
| | | | | | This class was a bit overengineered, and was triggering some PVS warnings. Instead, put strings into a NameType and let clients unconditionally treat it as a Node.
* createMCObjectStreamer - fix uninitialized variable warning. NFCI.Simon Pilgrim2019-11-041-1/+1
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* MCDwarfFile::DirIndex - fix uninitialized variable warning. NFCI.Simon Pilgrim2019-11-041-1/+1
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* Lower generic MASSV entries to PowerPC subtarget-specific entriesJinsong Ji2019-11-041-2/+9
| | | | | | | | | | | | | | | | | | | | | This patch (second of two patches) lowers the generic PowerPC vector entries to PowerPC subtarget-specific entries. For instance, the PowerPC generic entry 'cbrtd2_massv' is lowered to 'cbrtd2_P9' or Power9 subtarget. The first patch enables the vectorizer to recognize the IBM MASS vector library routines. This patch specifically adds support for recognizing the '-vector-library=MASSV' option, and defines mappings from IEEE standard scalar math functions to generic PowerPC MASS vector counterparts. For instance, the generic PowerPC MASS vector entry for double-precision 'cbrt' function is '__cbrtd2_massv' The overall support for MASS vector library is presented as such in two patches for ease of review. Patch by pjeeva01 (Jeeva P.) Differential Revision: https://reviews.llvm.org/D59883
* Recommit "[CodeView] Add option to disable inline line tables."Amy Huang2019-11-041-0/+1
| | | | | | | | | | | | This reverts commit 004ed2b0d1b86d424643ffc88fce20ad8bab6804. Original commit hash 6d03890384517919a3ba7fe4c35535425f278f89 Summary: This adds a clang option to disable inline line tables. When it is used, the inliner uses the call site as the location of the inlined function instead of marking it as an inline location with the function location. https://reviews.llvm.org/D67723
* AliasSetTracker - fix uninitialized variable warnings. NFCI.Simon Pilgrim2019-11-041-2/+2
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* [MachineVerifier] Improve verification of live-in lists.Jonas Paulsson2019-11-041-0/+3
| | | | | | | | | | | | | | | | | MachineVerifier::visitMachineFunctionAfter() is extended to check the live-through case for live-in lists. This is only done for registers without aliases and that are neither allocatable or reserved, such as the SystemZ::CC register. The MachineVerifier earlier only catched the case of a live-in use without an entry in the live-in list (as "using an undefined physical register"). A comment in LivePhysRegs.h has been added stating a guarantee that addLiveOuts() can be trusted for a full register both before and after register allocation. Review: Quentin Colombet https://reviews.llvm.org/D68267
* [opaque pointer types] Add element type argument to IRBuilder ↵Craig Topper2019-11-032-11/+8
| | | | | | | | | | | | | | | | | | | | CreatePreserveStructAccessIndex and CreatePreserveArrayAccessIndex Summary: These were the only remaining users of the GetElementPtrInst::getGEPReturnType method that gets the element type from the pointer type. Remove that method since its now dead. Reviewers: jyknight, t.p.northover, arsenm Reviewed By: arsenm Subscribers: wdng, arsenm, arphaman, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D69756
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