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* Add logic to greedy reg alloc to avoid bad eviction chainsMarina Yatsina2017-10-223-0/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes bugzilla 26810 https://bugs.llvm.org/show_bug.cgi?id=26810 This is intended to prevent sequences like: movl %ebp, 8(%esp) # 4-byte Spill movl %ecx, %ebp movl %ebx, %ecx movl %edi, %ebx movl %edx, %edi cltd idivl %esi movl %edi, %edx movl %ebx, %edi movl %ecx, %ebx movl %ebp, %ecx movl 16(%esp), %ebp # 4 - byte Reload Such sequences are created in 2 scenarios: Scenario #1: vreg0 is evicted from physreg0 by vreg1 Evictee vreg0 is intended for region splitting with split candidate physreg0 (the reg vreg0 was evicted from) Region splitting creates a local interval because of interference with the evictor vreg1 (normally region spliiting creates 2 interval, the "by reg" and "by stack" intervals. Local interval created when interference occurs.) one of the split intervals ends up evicting vreg2 from physreg1 Evictee vreg2 is intended for region splitting with split candidate physreg1 one of the split intervals ends up evicting vreg3 from physreg2 etc.. until someone spills Scenario #2 vreg0 is evicted from physreg0 by vreg1 vreg2 is evicted from physreg2 by vreg3 etc Evictee vreg0 is intended for region splitting with split candidate physreg1 Region splitting creates a local interval because of interference with the evictor vreg1 one of the split intervals ends up evicting back original evictor vreg1 from physreg0 (the reg vreg0 was evicted from) Another evictee vreg2 is intended for region splitting with split candidate physreg1 one of the split intervals ends up evicting vreg3 from physreg2 etc.. until someone spills As compile time was a concern, I've added a flag to control weather we do cost calculations for local intervals we expect to be created (it's on by default for X86 target, off for the rest). Differential Revision: https://reviews.llvm.org/D35816 Change-Id: Id9411ff7bbb845463d289ba2ae97737a1ee7cc39 llvm-svn: 316295
* [Transforms] Fix some Clang-tidy modernize and Include What You Use ↵Eugene Zelenko2017-10-211-6/+18
| | | | | | warnings; other minor fixes (NFC). llvm-svn: 316253
* [Packetizer] Add function to check for aliasing between instructionsKrzysztof Parzyszek2017-10-201-0/+7
| | | | llvm-svn: 316243
* [Transforms] Fix some Clang-tidy modernize and Include What You Use ↵Eugene Zelenko2017-10-202-7/+14
| | | | | | warnings; other minor fixes (NFC). llvm-svn: 316241
* [WebAssembly] MC: Fix crash when -g specified.Sam Clegg2017-10-202-18/+17
| | | | | | | | | At this point we don't output any debug sections or thier relocations. Differential Revision: https://reviews.llvm.org/D39076 llvm-svn: 316240
* [globalisel][tablegen] Fix small spelling nits. NFCDaniel Sanders2017-10-202-3/+3
| | | | | | | ComplexRendererFn -> ComplexRendererFns Corrected a couple lingering references to tied operands that were missed. llvm-svn: 316237
* COFF: Add type server pdb files to linkrepro tar file.Peter Collingbourne2017-10-201-1/+1
| | | | | | Differential Revision: https://reviews.llvm.org/D38977 llvm-svn: 316233
* [ExecutionEngine] After a heroic dev-meeting hack session, the JIT supports TLS.Lang Hames2017-10-201-0/+5
| | | | | | Turns on EmulatedTLS support by default in EngineBuilder. ;) llvm-svn: 316200
* [Transforms] Fix some Clang-tidy modernize and Include What You Use ↵Eugene Zelenko2017-10-194-13/+21
| | | | | | warnings; other minor fixes (NFC). llvm-svn: 316187
* Const fix for YAMLParser.Sam McCall2017-10-191-2/+4
| | | | llvm-svn: 316151
* [MergeFunctions] Don't blindly RAUW a GlobalValue with a ConstantExpr.whitequark2017-10-191-0/+4
| | | | | | | | | | | | | | | | MergeFunctions uses (through FunctionComparator) a map of GlobalValues to identifiers because it needs to compare functions and globals do not have an inherent total order. Thus, FunctionComparator (through GlobalNumberState) has a ValueMap<GlobalValue *>. r315852 added a RAUW on globals that may have been previously encountered by the FunctionComparator, which would replace a GlobalValue * key with a ConstantExpr *, which is illegal. This commit adjusts that code path to remove the function being replaced from the ValueMap as well. llvm-svn: 316145
* [llvm-cov] Move LineCoverageIterator to libCoverage. NFC.Vedant Kumar2017-10-181-0/+83
| | | | | | | | | | | | | LineCoverageIterator makes it easy for clients of coverage data to determine line execution counts for a file or function. The coverage iteration logic is tricky enough that it really pays not to have multiple copies of it. Hopefully having just one implementation in LLVM will make the iteration logic easier to test, reuse, and update. This commit is NFC but I've added a unit test to go along with it just because it's easy to do now. llvm-svn: 316141
* Revert "[ScalarEvolution] Handling for ICmp occuring in the evolution chain."Sanjoy Das2017-10-181-3/+0
| | | | | | | This reverts commit r316054. There was some confusion over the review process: http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-20171016/495884.html llvm-svn: 316129
* [Transforms] Fix some Clang-tidy modernize and Include What You Use ↵Eugene Zelenko2017-10-184-16/+45
| | | | | | warnings; other minor fixes (NFC). llvm-svn: 316128
* AMDGPU: Rename MaxFlatWorkgroupSize to MaxFlatWorkGroupSize for consistencyKonstantin Zhuravlyov2017-10-182-4/+4
| | | | | | Differential Revision: https://reviews.llvm.org/D38957 llvm-svn: 316097
* [ScalarEvolution] Handling for ICmp occuring in the evolution chain.Jatin Bhateja2017-10-181-0/+3
| | | | | | | | | | | | | | | | | | | | | | Summary: If a compare instruction is same or inverse of the compare in the branch of the loop latch, then return a constant evolution node. Currently scope of evaluation is limited to SCEV computation for PHI nodes. This shall facilitate computations of loop exit counts in cases where compare appears in the evolution chain of induction variables. Will fix PR 34538 Reviewers: sanjoy, hfinkel, junryoungju Reviewed By: junryoungju Subscribers: javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D38494 llvm-svn: 316054
* [GlobalDCE] Use DenseMap instead of unordered_multimap for GVDependencies.Michael Zolotukhin2017-10-171-1/+1
| | | | | | | | | | | | | | | Summary: std::unordered_multimap happens to be very slow when the number of elements grows large. On one of our internal applications we observed a 17x compile time improvement from changing it to DenseMap. Reviewers: mehdi_amini, serge-sans-paille, davide Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D38916 llvm-svn: 316045
* [Transforms] Fix some Clang-tidy modernize and Include What You Use ↵Eugene Zelenko2017-10-174-36/+60
| | | | | | warnings; other minor fixes (NFC). llvm-svn: 316034
* Fix pthread_[gs]etname_np detectionSam McCall2017-10-171-0/+6
| | | | llvm-svn: 316005
* Fix `FaultMaps` crash when the out streamer is reusedYichao Yu2017-10-171-0/+3
| | | | | | | | | | | | | | | | | | | Summary: Make sure the map is cleared before processing a new module. Similar to what is done on `StackMaps`. This issue is similar to D38588, though this time for FaultMaps (on x86) rather than ARM/AArch64. Other than possible mixing of information between modules, the crash is caused by the pointers values in the map that was allocated by the bump pointer allocator that is unwinded when emitting the next file. This issue has been around since 3.8. This issue is likely much harder to write a test for since AFAICT it requires emitting something much more compilcated (and possibly real code) instead of just some random bytes. Reviewers: skatkov, sanjoy Reviewed By: skatkov, sanjoy Subscribers: sanjoy, aemerson, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D38924 llvm-svn: 315990
* Revert 315440 on behalf of mkazantsevPhilip Reames2017-10-171-7/+0
| | | | | | | | | | | This patch reverts rL315440 because of the bug described at https://bugs.llvm.org/show_bug.cgi?id=34937 The fix for the bug is on review as D38944, but not yet ready. Given this is a regression reverting until a fix is ready is called for. Max would have done the revert himself, but is having trouble doing a build of fresh LLVM for some reason. I did the build and test to ensure the revert worked as expected on his behalf. llvm-svn: 315974
* Revert "[SCEV] Maintain and use a loop->loop invalidation dependency"Sanjoy Das2017-10-171-14/+3
| | | | | | | | | This reverts commit r315713. It causes PR34968. I think I know what the problem is, but I don't think I'll have time to fix it this week. llvm-svn: 315962
* Add !callees metadataMatthew Simpson2017-10-162-0/+9
| | | | | | | | | This patch adds a new kind of metadata that indicates the possible callees of indirect calls. Differential Revision: https://reviews.llvm.org/D37354 llvm-svn: 315944
* [Transforms] Fix some Clang-tidy modernize and Include What You Use ↵Eugene Zelenko2017-10-165-12/+28
| | | | | | warnings; other minor fixes (NFC). llvm-svn: 315940
* Replace make_range in MachineRegisterInfo with ArrayRef, NFCKrzysztof Parzyszek2017-10-161-2/+3
| | | | llvm-svn: 315938
* Add base relative relocation record that can be used for the following case ↵Tony Tye2017-10-161-0/+1
| | | | | | | | | | | | | | (OpenCL example): static __global int Var = 0; __global int* Ptr[] = {&Var}; ... In this case Var is a non premptable symbol and so its address can be used as the value of Ptr, with a base relative relocation that will add the delta between the ELF address and the actual load address. Such relocations do not require a symbol. Differential Revision: https://reviews.llvm.org/D38909 llvm-svn: 315935
* Add iterator range MachineRegisterInfo::liveins(), adopt users, NFCKrzysztof Parzyszek2017-10-161-0/+3
| | | | llvm-svn: 315927
* [SCEV] Rename getMaxBECount and update comments. NFCAnna Thomas2017-10-161-3/+4
| | | | | | Post commit review comments at D38825. llvm-svn: 315920
* [SparsePropagation] Enable interprocedural analysisMatthew Simpson2017-10-161-131/+157
| | | | | | | | | | | | | | | | | | This patch adds the ability to perform IPSCCP-like interprocedural analysis to the generic sparse propagation solver. The patch gives clients the ability to define their own custom LatticeKey types that the generic solver maps to custom LatticeVal types. The custom lattice keys can be used, for example, to distinguish among mappings for regular values, values returned from functions, and values stored in global variables. Clients are responsible for defining how to convert between LatticeKeys and LLVM Values by providing a specialization of the LatticeKeyInfo template. The added unit tests demonstrate how the generic solver can be used to perform a simplified version of interprocedural constant propagation. Differential Revision: https://reviews.llvm.org/D37353 llvm-svn: 315919
* This patch is a result of D37262: The issues with X86 prefixes. It closes ↵Andrew V. Tischenko2017-10-161-0/+7
| | | | | | PR7709, PR17697, PR19251, PR32809 and PR21640. There could be other bugs closed by this patch. llvm-svn: 315899
* Re-commit r315885: [globalisel][tblgen] Add support for iPTR and implement ↵Daniel Sanders2017-10-162-1/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | am_unscaled* and am_indexed* Summary: iPTR is a pointer of subtarget-specific size to any address space. Therefore type checks on this size derive the SizeInBits from a subtarget hook. At this point, we can import the simplests G_LOAD rules and select load instructions using them. Further patches will support for the predicates to enable additional loads as well as the stores. The previous commit failed on MSVC due to a failure to convert an initializer_list to a std::vector. Hopefully, MSVC will accept this version. Depends on D37457 Reviewers: ab, qcolombet, t.p.northover, rovka, aditya_nandakumar Reviewed By: qcolombet Subscribers: kristof.beyls, javed.absar, llvm-commits, igorb Differential Revision: https://reviews.llvm.org/D37458 llvm-svn: 315887
* Revert r315885: [globalisel][tblgen] Add support for iPTR and implement ↵Daniel Sanders2017-10-162-16/+0
| | | | | | | | am_unscaled* and am_indexed* MSVC doesn't like one of the constructors. llvm-svn: 315886
* [globalisel][tblgen] Add support for iPTR and implement am_unscaled* and ↵Daniel Sanders2017-10-162-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | am_indexed* Summary: iPTR is a pointer of subtarget-specific size to any address space. Therefore type checks on this size derive the SizeInBits from a subtarget hook. At this point, we can import the simplests G_LOAD rules and select load instructions using them. Further patches will support for the predicates to enable additional loads as well as the stores. Depends on D37457 Reviewers: ab, qcolombet, t.p.northover, rovka, aditya_nandakumar Reviewed By: qcolombet Subscribers: kristof.beyls, javed.absar, llvm-commits, igorb Differential Revision: https://reviews.llvm.org/D37458 llvm-svn: 315885
* [globalisel][tablegen] Implement unindexed load, non-extending load, and ↵Daniel Sanders2017-10-162-1/+20
| | | | | | | | | | | | | | | | | | | | | | | | MemVT checks Summary: This includes some context-sensitivity in the MVT to LLT conversion so that pointer types are tested correctly. FIXME: I'm not happy with the way this is done since everything is a special-case. I've yet to find a reasonable way to implement it. select-load.mir fails because <1 x s64> loads in tablegen get priority over s64 loads. This is fixed in the next patch and as such they should be committed together, I've posted them separately to help with the review. Depends on D37456 Reviewers: ab, qcolombet, t.p.northover, rovka, aditya_nandakumar Subscribers: kristof.beyls, javed.absar, llvm-commits, igorb Differential Revision: https://reviews.llvm.org/D37457 llvm-svn: 315884
* Re-commit r315863: [globalisel][tablegen] Import ComplexPattern when used as ↵Daniel Sanders2017-10-152-7/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | an operator Summary: It's possible for a ComplexPattern to be used as an operator in a match pattern. This is used by the load/store patterns in AArch64 to name the suboperands returned by ComplexPattern predicate so that they can be broken apart and referenced independently in the result pattern. This patch adds support for this in order to enable the import of load/store patterns. Depends on D37445 Hopefully fixed the ambiguous constructor that a large number of bots reported. Reviewers: ab, qcolombet, t.p.northover, rovka, aditya_nandakumar Reviewed By: qcolombet Subscribers: aemerson, javed.absar, igorb, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D37456 llvm-svn: 315869
* Revert r315863: [globalisel][tablegen] Import ComplexPattern when used as an ↵Daniel Sanders2017-10-152-28/+7
| | | | | | | | operator A large number of bots are failing on an ambiguous constructor call. llvm-svn: 315866
* [globalisel][tablegen] Import ComplexPattern when used as an operatorDaniel Sanders2017-10-152-7/+28
| | | | | | | | | | | | | | | | | | | | | | | Summary: It's possible for a ComplexPattern to be used as an operator in a match pattern. This is used by the load/store patterns in AArch64 to name the suboperands returned by ComplexPattern predicate so that they can be broken apart and referenced independently in the result pattern. This patch adds support for this in order to enable the import of load/store patterns. Depends on D37445 Reviewers: ab, qcolombet, t.p.northover, rovka, aditya_nandakumar Reviewed By: qcolombet Subscribers: aemerson, javed.absar, igorb, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D37456 llvm-svn: 315863
* Reverting r315590; it did not include changes for llvm-tblgen, which is ↵Aaron Ballman2017-10-1511-18/+17
| | | | | | | | causing link errors for several people. Error LNK2019 unresolved external symbol "public: void __cdecl `anonymous namespace'::MatchableInfo::dump(void)const " (?dump@MatchableInfo@?A0xf4f1c304@@QEBAXXZ) referenced in function "public: void __cdecl `anonymous namespace'::AsmMatcherEmitter::run(class llvm::raw_ostream &)" (?run@AsmMatcherEmitter@?A0xf4f1c304@@QEAAXAEAVraw_ostream@llvm@@@Z) llvm-tblgen D:\llvm\2017\utils\TableGen\AsmMatcherEmitter.obj 1 llvm-svn: 315854
* [LoopInfo][Refactor] Make SetLoopAlreadyUnrolled a member function of the ↵Hongbin Zheng2017-10-151-0/+8
| | | | | | | | | | Loop Pass, NFC. This avoid code duplication and allow us to add the disable unroll metadata elsewhere. Differential Revision: https://reviews.llvm.org/D38928 llvm-svn: 315850
* [globalisel][tablegen] Map ld and st to G_LOAD and G_STORE. NFCDaniel Sanders2017-10-153-0/+44
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: There is an important mismatch between ISD::LOAD and G_LOAD (and likewise for ISD::STORE and G_STORE). In SelectionDAG, ISD::LOAD is a non-atomic load and atomic loads are handled by a separate node. However, this is not true of GlobalISel's G_LOAD. For G_LOAD, the MachineMemOperand indicates the atomicity of the operation. As a result, this mapping must also add a predicate that checks for non-atomic MachineMemOperands. This is NFC since these nodes always have predicates in practice and are therefore always rejected at the moment. Depends on D37443 Reviewers: ab, qcolombet, t.p.northover, rovka, aditya_nandakumar Reviewed By: qcolombet Subscribers: kristof.beyls, llvm-commits, igorb Differential Revision: https://reviews.llvm.org/D37445 llvm-svn: 315843
* [tablegen] Handle common load/store predicates inside tablegen. NFC.Daniel Sanders2017-10-151-168/+257
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: GlobalISel and SelectionDAG require different code for the common load/store predicates due to differences in the representation. For example: SelectionDAG: (load<signext,i8>:i32 GPR32:$addr) // The <> denote properties of the SDNode that are not printed in the DAG GlobalISel: (G_SEXT:s32 (G_LOAD:s8 GPR32:$addr)) Even without that, differences in the IR (SDNode vs MachineInstr) require differences in the C++ predicate. This patch moves the implementation of the common load/store predicates into tablegen so that it can handle these differences. It's NFC for SelectionDAG since it emits equivalent code and it's NFC for GlobalISel since the rules involving the relevant predicates are still rejected by the importer. Depends on D36618 Reviewers: ab, qcolombet, t.p.northover, rovka, aditya_nandakumar Subscribers: llvm-commits, igorb Differential Revision: https://reviews.llvm.org/D37443 Includes a partial revert of r315826 since this patch makes it necessary for getPredCode() to return a std::string and getImmCode() should have the same interface as getPredCode(). llvm-svn: 315841
* AMDGPU: Add AMDGPU HSA Kernel DescriptorKonstantin Zhuravlyov2017-10-141-0/+139
| | | | | | | | | | - Update docs to match llvm coding style - Add missing FP16_OVFL bit for gfx9 - Fix the size of the kernel descriptor in the docs Differential Revision: https://reviews.llvm.org/D38902 llvm-svn: 315822
* AMDGPU: Bring HSA metadata on par with the specificationKonstantin Zhuravlyov2017-10-141-55/+64
| | | | | | Differential Revision: https://reviews.llvm.org/D38753 llvm-svn: 315821
* [Dominators] Remove the NCA checkJakub Kuderski2017-10-141-37/+2
| | | | | | | | | | | | | | | | | | Summary: This patch removes the `verifyNCD` check. The reason for this is that the other checks are sufficient to prove or disprove correctness of any DominatorTree, and that `verifyNCD` doesn't provide (in my option) better error messages then the other ones. Additionally, this should give a (small) improvement to the total verification time, as the check is O(n), and checking the sibling property takes O(n^3). Reviewers: dberlin, grosser, davide, brzycki Reviewed By: brzycki Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D38802 llvm-svn: 315790
* [globalisel][tablegen] Fix an unused variable warning caused by a typo ↵Daniel Sanders2017-10-141-1/+1
| | | | | | | | (corrected OtherInsnID->OtherOpIdx). The tests were passing by luck since the instruction ID and operand index happened to be the same. llvm-svn: 315788
* [globalisel][tablegen] Fix undefined references to dump()Daniel Sanders2017-10-141-2/+0
| | | | | | Two debugging statements snuck into the commit. llvm-svn: 315783
* [globalisel][tablegen] Simplify named operand/operator lookups and fix a ↵Daniel Sanders2017-10-142-1/+26
| | | | | | | | | | | | | | | | | | | | | | wrong-code bug this revealed. Summary: Operand variable lookups are now performed by the RuleMatcher rather than searching the whole matcher hierarchy for a match. This revealed a wrong-code bug that currently affects ARM and X86 where patterns that use a variable more than once in the match pattern will be imported but won't check that the operands are identical. This can cause the tablegen-erated matcher to accept matches that should be rejected. Depends on D36569 Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar Subscribers: aemerson, igorb, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D36618 llvm-svn: 315780
* [globalisel][tablegen] Add support for fpimm and import of APInt/APFloat ↵Daniel Sanders2017-10-133-10/+61
| | | | | | | | | | | | | | | | | | | | | | based ImmLeaf. Summary: There's only a tablegen testcase for IntImmLeaf and not a CodeGen one because the relevant rules are rejected for other reasons at the moment. On AArch64, it's because there's an SDNodeXForm attached to the operand. On X86, it's because the rule either emits multiple instructions or has another predicate using PatFrag which cannot easily be supported at the same time. Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar Reviewed By: qcolombet Subscribers: aemerson, javed.absar, igorb, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D36569 llvm-svn: 315761
* [Transforms] Fix some Clang-tidy modernize and Include What You Use ↵Eugene Zelenko2017-10-134-16/+24
| | | | | | warnings; other minor fixes (NFC). llvm-svn: 315760
* [RegisterBankInfo] Cache the getMinimalPhysRegClass informationQuentin Colombet2017-10-131-2/+11
| | | | | | | | | | | | | | | TargetRegisterInfo::getMinimalPhysRegClass is actually pretty expensive because it has to iterate over all the register classes. Cache this information as we need and get it so that we limit its usage. Right now, we heavily rely on it, because this is how we get the mapping for vregs defined by copies from physreg (i.e., the one that are ABI related). Improve compile time by up to 10% for that pass. NFC llvm-svn: 315759
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