| Commit message (Collapse) | Author | Age | Files | Lines |
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return it as a clobber. This allows GVN to do smart things.
Enhance GVN to be smart about the case when a small load is clobbered
by a larger overlapping load. In this case, forward the value. This
allows us to compile stuff like this:
int test(void *P) {
int tmp = *(unsigned int*)P;
return tmp+*((unsigned char*)P+1);
}
into:
_test: ## @test
movl (%rdi), %ecx
movzbl %ch, %eax
addl %ecx, %eax
ret
which has one load. We already handled the case where the smaller
load was from a must-aliased base pointer.
llvm-svn: 130180
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space, if requested, will be used for complex addresses of the Blocks' variables.
llvm-svn: 130178
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llvm-svn: 130153
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patch by Johannes Schaub!
llvm-svn: 130151
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llvm-svn: 130094
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llvm-svn: 130086
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llvm-svn: 130068
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llvm-svn: 130033
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llvm-svn: 130028
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llvm-svn: 130027
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fix bugs exposed by the gcc dejagnu testsuite:
1. The load may actually be used by a dead instruction, which
would cause an assert.
2. The load may not be used by the current chain of instructions,
and we could move it past a side-effecting instruction. Change
how we process uses to define the problem away.
llvm-svn: 130018
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warnings.
llvm-svn: 129988
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llvm-svn: 129972
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X8664_ELFTargetObjectFile::getFDEEncoding to match reality.
llvm-svn: 129959
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llvm-svn: 129955
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llvm-svn: 129945
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llvm-svn: 129938
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llvm-svn: 129932
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which broke a couple GCC test suite tests at -O0.
llvm-svn: 129914
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These values were not used for anything. Spill size and alignment is a property
of the register class, not the register.
llvm-svn: 129906
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instrument the program to emit .gcda.
TODO: we should emit slightly different .gcda files when .gcno emission is off.
llvm-svn: 129903
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llvm-svn: 129884
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On the x86-64 and thumb2 targets, some registers are more expensive to encode
than others in the same register class.
Add a CostPerUse field to the TableGen register description, and make it
available from TRI->getCostPerUse. This represents the cost of a REX prefix or a
32-bit instruction encoding required by choosing a high register.
Teach the greedy register allocator to prefer cheap registers for busy live
ranges (as indicated by spill weight).
llvm-svn: 129864
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<rdar://problem/7662569>
llvm-svn: 129858
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used by Clang. To help Clang integration, the PTX target has been split
into two targets: ptx32 and ptx64, depending on the desired pointer size.
- Add GCCBuiltin class to all intrinsics
- Split PTX target into ptx32 and ptx64
llvm-svn: 129851
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llvm-svn: 129844
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triple component.
llvm-svn: 129838
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instead.
llvm-svn: 129836
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Triple::OSX once Clang has moved.
llvm-svn: 129833
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llvm-svn: 129815
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llvm-svn: 129806
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llvm-svn: 129801
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llvm-svn: 129800
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llvm-svn: 129799
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llvm-svn: 129798
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Add a avoidWriteAfterWrite() target hook to identify register classes that
suffer from write-after-write hazards. For those register classes, try to avoid
writing the same register in two consecutive instructions.
This is currently disabled by default. We should not spill to avoid hazards!
The command line flag -avoid-waw-hazard can be used to enable waw avoidance.
llvm-svn: 129772
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memory a BumpPtrAllocator allocated.
llvm-svn: 129727
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each instruction.
llvm-svn: 129715
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llvm-svn: 129696
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the generated FastISel. X86 doesn't need to generate code to match ADD16ri8
since ADD16ri will do just fine. This is a small codesize win in the generated
instruction selector.
llvm-svn: 129692
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reduces the number of calls to malloc().
llvm-svn: 129687
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overload that takes no parameters.
llvm-svn: 129686
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matching code.
llvm-svn: 129677
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kind of predicate: one that is specific to imm nodes. The predicate function
specified here just checks an int64_t directly instead of messing around with
SDNode's. The virtue of this is that it means that fastisel and other things
can reason about these predicates.
llvm-svn: 129675
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structure and fix some fixmes. We now have a TreePredicateFn class
that handles all of the decoding of these things. This is an internal
cleanup that has no impact on the code generated by tblgen.
llvm-svn: 129670
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The basic issue here is that bottom-up isel is matching the branch
and compare, and was failing to fold the load into the branch/compare
combo. Fixing this (by allowing folding into any instruction of a
sequence that is selected) allows us to produce things like:
cmpb $0, 52(%rax)
je LBB4_2
instead of:
movb 52(%rax), %cl
cmpb $0, %cl
je LBB4_2
This makes the generated -O0 code run a bit faster, but also speeds up
compile time by putting less pressure on the register allocator and
generating less code.
This was one of the biggest classes of missing load folding. Implementing
this shrinks 176.gcc's c-decl.s (as a random example) by about 4% in (verbose-asm)
line count.
llvm-svn: 129656
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error in foo.o; no .eh_frame_hdr table will be created.
llvm-svn: 129635
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does. Also mostly implement it. Still a work-in-progress, but generates legal
output on crafted test cases.
llvm-svn: 129630
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information generated for an interface.
llvm-svn: 129624
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llvm-svn: 129600
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