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* [AMDGPU] Updae documentation about address spaceYaxun Liu2018-02-081-25/+13
| | | | llvm-svn: 324617
* Revert "AMDGPU: Add 32-bit constant address space"Rafael Espindola2018-02-071-1/+0
| | | | | | | | This reverts commit r324487. It broke clang tests. llvm-svn: 324494
* AMDGPU: Add 32-bit constant address spaceMarek Olsak2018-02-071-0/+1
| | | | | | | | | | | | | | | | | | | | | | | Note: This is a candidate for LLVM 6.0, because it was planned to be in that release but was delayed due to a long review period. Merge conflict in release_60 - resolution: Add "-p6:32:32" into the second (non-amdgiz) string. Only scalar loads support 32-bit pointers. An address in a VGPR will fail to compile. That's OK because the results of loads will only be used in places where VGPRs are forbidden. Updated AMDGPUAliasAnalysis and used SReg_64_XEXEC. The tests cover all uses cases we need for Mesa. Reviewers: arsenm, nhaehnle Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D41651 llvm-svn: 324487
* [AMDGPU] Update relocation documentation and elf flag machine architecture ↵Tony Tye2018-01-301-24/+25
| | | | | | | | numbers Differential Revision: https://reviews.llvm.org/D42714 llvm-svn: 323835
* [AMDGPU] Clarify ReqdWorkGroupSize and MaxFlatWorkGroupSize metadataTony Tye2018-01-301-40/+9
| | | | | | | | - If ReqdWorkGroupSize is present it must have all elements >=1. - If MaxFlatWorkGroupSize must be consistent with ReqdWorkGroupSize. - Remove FixedWorkGroupSize as now equivalent to ReqdWorkGroupSize. llvm-svn: 323829
* fix invalid footnote syntaxTim Hammerquist2018-01-051-3/+0
| | | | llvm-svn: 321839
* [AMDGPU] Rename Bonaire target to be gfx704; remove gfx800 and make Iceland ↵Tony Tye2017-12-121-11/+7
| | | | | | | | | | | | | | | | and Tonga both use gfx802; update target feature handling Correct committed version to match intended accepted review D40051 id=123417 - Rename Bonaire target to be gfx704. - Eliminate gfx800 and make Iceland and Tonga both use gfx802 as they use the same code. - List target features supported by each processor in the processor table together with the default value. - Add xnack flag to e_flags. - Remove xnack from kernel metadata and kernel descriptor since it is now a whole code object property. Differential Revision: https://reviews.llvm.org/D40051 llvm-svn: 320457
* [AMDGPU] Rename Bonaire target to be gfx704; update target feature handlingTony Tye2017-12-111-139/+144
| | | | | | | | | | | | - Rename Bonaire target to be gfx704. - Eliminate gfx800 and make Iceland and Tonga both use gfx802 as they use the same code. - List target features supported by each processor in the processor table together with the default value. - Add xnack flag to e_flags. - Remove xnack from kernel metadata and kernel descriptor since it is now a whole code object property. Differential Revision: https://reviews.llvm.org/D40051 llvm-svn: 320378
* [AMDGPU] Fix typo in Kernel Descriptor for GFX6-GFX9Mark Searles2017-12-071-1/+1
| | | | | | Differential Revision: https://reviews.llvm.org/D40981 llvm-svn: 320087
* AMDGPU: Add num spilled s/vgprs to metadataKonstantin Zhuravlyov2017-11-281-0/+10
| | | | | | | | This was requested by tools. Differential Revision: https://reviews.llvm.org/D40321 llvm-svn: 319192
* [AMDGPU] Correct targets that support XNACKTony Tye2017-11-111-1/+1
| | | | | | Differential Revision: https://reviews.llvm.org/D39887 llvm-svn: 317955
* [AMDGPU] AMDGPUUsage.rst minor correctionsTony Tye2017-11-101-14/+16
| | | | | | Differential Revision: https://reviews.llvm.org/D39887 llvm-svn: 317924
* [AMDGPU] Update code object descriptionTony Tye2017-11-101-295/+368
| | | | | | | | | | | | | | | | | - Use ELF header flags to identify processor. - Remove isa note record. - Add target feature section. - Make metadata for NumVGPRs, NumSGPRs and MaxFlatWorkGroupSize required. - Add FixedWorkGroupSize to CodeProps metadata. - Add ReqdWorkGroupSize* to kernel descriptor and move MaxFlatWorkGroupSize to be adjacent. - Move IsXNACKEnabled in the kernel descriptor to be at the end of the unused flags. - Remove IsDynamicCallStack from the metadata and kernel descriptor. - Remove legacy debugger metadata. - Remove old XNACK enabled processor names. Differential Revision: https://reviews.llvm.org/D39828 llvm-svn: 317855
* [AMDGPU] Emit metadata for hidden arguments for kernel enqueueYaxun Liu2017-10-301-4/+4
| | | | | | | | | | | | | Identifies kernels which performs device side kernel enqueues and emit metadata for the associated hidden kernel arguments. Such kernels are marked with calls-enqueue-kernel function attribute by AMDGPUOpenCLEnqueueKernelLowering pass and later on hidden kernel arguments metadata HiddenDefaultQueue and HiddenCompletionAction are emitted for them. Differential Revision: https://reviews.llvm.org/D39255 llvm-svn: 316907
* AMDGPU/Docs: Fix unreadable charactersKonstantin Zhuravlyov2017-10-191-6/+6
| | | | llvm-svn: 316171
* [AMDGPU] Corrections to memory model description.Tony Tye2017-10-181-174/+376
| | | | | | | | | | - Add description on nontemporal support. - Correct OpenCL sequentially consistent and fence code sequences. - Minor test cleanup. Differential Revision: https://reviews.llvm.org/D39073 llvm-svn: 316131
* AMDGPU/Docs: Make target naming consistentKonstantin Zhuravlyov2017-10-181-18/+17
| | | | | | | | | - R600 Arch: Use Radeon HD XXXX Series - GCN Arch: Use GFXX Differential Revision: https://reviews.llvm.org/D39019 llvm-svn: 316100
* AMDGPU: Rename MaxFlatWorkgroupSize to MaxFlatWorkGroupSize for consistencyKonstantin Zhuravlyov2017-10-181-2/+2
| | | | | | Differential Revision: https://reviews.llvm.org/D38957 llvm-svn: 316097
* Add base relative relocation record that can be used for the following case ↵Tony Tye2017-10-161-1/+8
| | | | | | | | | | | | | | (OpenCL example): static __global int Var = 0; __global int* Ptr[] = {&Var}; ... In this case Var is a non premptable symbol and so its address can be used as the value of Ptr, with a base relative relocation that will add the delta between the ELF address and the actual load address. Such relocations do not require a symbol. Differential Revision: https://reviews.llvm.org/D38909 llvm-svn: 315935
* AMDGPU: Add AMDGPU HSA Kernel DescriptorKonstantin Zhuravlyov2017-10-141-91/+113
| | | | | | | | | | - Update docs to match llvm coding style - Add missing FP16_OVFL bit for gfx9 - Fix the size of the kernel descriptor in the docs Differential Revision: https://reviews.llvm.org/D38902 llvm-svn: 315822
* AMDGPU: Bring HSA metadata on par with the specificationKonstantin Zhuravlyov2017-10-141-3/+4
| | | | | | Differential Revision: https://reviews.llvm.org/D38753 llvm-svn: 315821
* [AMDGPU] Lower enqueued blocks and generate runtime metadataYaxun Liu2017-10-101-0/+10
| | | | | | | | | | | | | | | | | | | | | | | This patch adds a post-linking pass which replaces the function pointer of enqueued block kernel with a global variable (runtime handle) and adds runtime-handle attribute to the enqueued block kernel. In LLVM CodeGen the runtime-handle metadata will be translated to RuntimeHandle metadata in code object. Runtime allocates a global buffer for each kernel with RuntimeHandel metadata and saves the kernel address required for the AQL packet into the buffer. __enqueue_kernel function in device library knows that the invoke function pointer in the block literal is actually runtime handle and loads the kernel address from it and puts it into AQL packet for dispatching. This cannot be done in FE since FE cannot create a unique global variable with external linkage across LLVM modules. The global variable with internal linkage does not work since optimization passes will try to replace loads of the global variable with its initialization value. Differential Revision: https://reviews.llvm.org/D38610 llvm-svn: 315352
* AMDGPU/Docs: Follow up on review feedback in https://reviews.llvm.org/D38387Konstantin Zhuravlyov2017-10-031-2/+2
| | | | llvm-svn: 314848
* AMDGPU: Add ELFOSABI_AMDGPU_MESA3DKonstantin Zhuravlyov2017-10-031-12/+22
| | | | | | Differential Revision: https://reviews.llvm.org/D38387 llvm-svn: 314846
* AMDGPU: Add ELFOSABI_AMDGPU_PALKonstantin Zhuravlyov2017-10-031-12/+26
| | | | llvm-svn: 314843
* Update AMDGPUUsage.rst documentation:Tony Tye2017-08-151-271/+315
| | | | | | | | | | | | 1. Correct description of the kernel initial state for FLAT_SCRATCH_INIT. 2. Add link to GFX9 architecture documentation. 3. Update product names. 4. Rename note record from NT_AMD_AMDGPU_METADATA to NT_AMD_AMDGPU_HSA_METADATA and move description to the AMDHSA coding convention section. 5. Minor typo corrections. Differential Revision: https://reviews.llvm.org/D36549 llvm-svn: 310954
* AMDGPU: Also remove SI from docsKonstantin Zhuravlyov2017-08-081-2/+1
| | | | | | Differential Revision: https://reviews.llvm.org/D36424 llvm-svn: 310335
* Correct GFX9 processor names.Tony Tye2017-07-071-3/+1
| | | | | | Differential Revision: https://reviews.llvm.org/D33736 llvm-svn: 307353
* fix various typosSylvestre Ledru2017-06-261-10/+10
| | | | llvm-svn: 306262
* Correct AMDGPU Hawaii and Kabini target namesTony Tye2017-06-081-3/+3
| | | | | | | | The FirePro and Radeon versions of Hawaii have different 64 bit floating point configurations so use distinct target names for them. Rename the target name for Kabini to accommodate. Differential Revision: https://reviews.llvm.org/D34016 llvm-svn: 304959
* Try to work around possible bugs in version of Shpinx on buildserver.Tony Tye2017-06-071-6/+6
| | | | | | | | Builds sucessfully with Sphinx v1.5.5 Differential Revision: https://reviews.llvm.org/D33736 llvm-svn: 304853
* Add documentation for various aspects of the AMDGPU backend.Tony Tye2017-06-071-1/+1
| | | | | | | | | Remove extra tabs. Builds sucessfully with Sphinx v1.5.5 Differential Revision: https://reviews.llvm.org/D33736 llvm-svn: 304848
* Add documentation for various aspects of the AMDGPU backend.Tony Tye2017-06-061-104/+3462
| | | | | | Differential Revision: https://reviews.llvm.org/D33736 llvm-svn: 304831
* Fixing a malformed RST table to get the documentation bot back to green.Aaron Ballman2017-04-271-1/+1
| | | | llvm-svn: 301545
* AMDGPU: Move trap lowering to DAGMatt Arsenault2017-04-241-3/+2
| | | | | | | | | | | Fixes traps in any block besides the entry block, and fixes depending on a live-in physical register by using a virtual register copy. Also happens to stop emitting a nop in the case debug trap is not supported. llvm-svn: 301206
* [DebugInfo] Emit address space with DW_AT_address_class attribute for ↵Konstantin Zhuravlyov2017-03-081-10/+14
| | | | | | | | pointer and reference types Differential Revision: https://reviews.llvm.org/D29670 llvm-svn: 297320
* AMDGPU : AMDGPU : Update AMDGPU Trap Handler ABI.Wei Ding2017-02-211-41/+49
| | | | | | Differential Revision: http://reviews.llvm.org/D29913 llvm-svn: 295745
* Correcting several sphinx errors; should fix the LLVM documentation build.Aaron Ballman2017-02-111-6/+8
| | | | llvm-svn: 294865
* AMDGPU : Add trap handler support.Wei Ding2017-02-101-0/+39
| | | | | | Differential Revision: http://reviews.llvm.org/D26010 llvm-svn: 294692
* fix some typos in the docSylvestre Ledru2017-01-141-1/+1
| | | | llvm-svn: 292014
* AMDGPU: Improve documentation.Nikolay Haustov2016-09-201-68/+216
| | | | | | | | | | | | | | | | | Summary: Add links to ISA manuals and ABI. Add text about assembler syntax. Add info about instructions operands. Add instruction examples for each encoding. Update directives section, add missing .amdgpu_hsa_kernel. Reviewers: tstellarAMD, SamWot, vpykhtin Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, tony-tye, artem.tamazov, llvm-commits Differential Revision: https://reviews.llvm.org/D24724 llvm-svn: 281962
* This code block breaks the docs build ↵Aaron Ballman2016-07-191-1/+1
| | | | | | (http://lab.llvm.org:8011/builders/llvm-sphinx-docs/builds/11920/steps/docs-llvm-html/logs/stdio), but I cannot see anything immediately wrong with it and cannot reproduce the diagnostic locally. Setting the code highlighting to none instead of nasm to hopefully get the bot stumbling back towards green. llvm-svn: 275998
* Speculatively fix the sphinx build, which does not think the original code ↵Aaron Ballman2016-07-141-4/+4
| | | | | | was valid nasm (http://lab.llvm.org:8011/builders/llvm-sphinx-docs/builds/11854/steps/docs-llvm-html/logs/stdio). llvm-svn: 275408
* AMDGPU: Document address space mappingTom Stellard2016-04-061-0/+23
| | | | | | | | | | | | | | | | | Summary: Address space mapping is described in lib/Target/AMDGPU/AMDGPU.h in Doxygen comments. This patch adds the description to user guide for AMDGPU back-end. Patch By: Vedran Miletić Reviewers: tstellarAMD, arsenm Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D17046 llvm-svn: 265500
* fix the indentation of the exampleSylvestre Ledru2016-02-231-1/+1
| | | | llvm-svn: 261628
* docs/AMDGPUUsage: Update assembly exampleTom Stellard2016-02-221-2/+7
| | | | | | | | | | Reviewers: arsenm, nhaustov Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D17461 llvm-svn: 261550
* AMDGPU/SI: Update amd_kernel_code_t definition and add assembler supportTom Stellard2015-06-261-0/+57
| | | | | | | | | | Reviewers: arsenm Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D10772 llvm-svn: 240839
* AMDGPU/SI: Add hsa code object directivesTom Stellard2015-06-261-0/+26
| | | | | | | | | | Reviewers: arsenm Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D10757 llvm-svn: 240831
* R600 -> AMDGPU renameTom Stellard2015-06-131-0/+94
llvm-svn: 239657
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