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path: root/lldb/source/Plugins/Process/Utility/ARMUtils.h
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* Fix typos.Bruce Mitchener2014-07-081-1/+1
| | | | llvm-svn: 212553
* Ran the static analyzer on the codebase and found a few things.Greg Clayton2012-07-171-2/+6
| | | | llvm-svn: 160338
* When emulating an ill-formed instruction, we should bail out instead of ↵Johnny Chen2011-06-021-35/+87
| | | | | | asserting and bringing down the whole process. llvm-svn: 132506
* Remove asserts that will crash LLDB. These should be changed to returnGreg Clayton2011-06-021-11/+13
| | | | | | | true/false in an extra boolean parameter and not cause the the binary that us using the LLDB framework to crash. llvm-svn: 132501
* While implementing unwind information using UnwindAssemblyInstEmulation I ranGreg Clayton2011-05-091-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into some cleanup I have been wanting to do when reading/writing registers. Previously all RegisterContext subclasses would need to implement: virtual bool ReadRegisterBytes (uint32_t reg, DataExtractor &data); virtual bool WriteRegisterBytes (uint32_t reg, DataExtractor &data, uint32_t data_offset = 0); There is now a new class specifically designed to hold register values: lldb_private::RegisterValue The new register context calls that subclasses must implement are: virtual bool ReadRegister (const RegisterInfo *reg_info, RegisterValue &reg_value) = 0; virtual bool WriteRegister (const RegisterInfo *reg_info, const RegisterValue &reg_value) = 0; The RegisterValue class must be big enough to handle any register value. The class contains an enumeration for the value type, and then a union for the data value. Any integer/float values are stored directly in an appropriate host integer/float. Anything bigger is stored in a byte buffer that has a length and byte order. The RegisterValue class also knows how to copy register value bytes into in a buffer with a specified byte order which can be used to write the register value down into memory, and this does the right thing when not all bytes from the register values are needed (getting a uint8 from a uint32 register value..). All RegiterContext and other sources have been switched over to using the new regiter value class. llvm-svn: 131096
* Fix small bug in ThumbExpandImm_C; arguments to a call to 'bits' wereCaroline Tice2011-03-241-1/+1
| | | | | | in the wrong order. llvm-svn: 128237
* Add emulation for "ADR" operations. Add a ThumbImm8Scaled() convenience ↵Johnny Chen2011-02-231-1/+8
| | | | | | | | function and rename the original ThumbImmScaled() function to ThumbImm7Scaled(). llvm-svn: 126335
* Add two convenience functions: DecodeImmShiftThumb() and DecodeImmShiftARM() ↵Johnny Chen2011-02-221-18/+32
| | | | | | | | to ARMUtils.h. Use them within EmulateInstructionARM.cpp to save repetitive typing. llvm-svn: 126247
* Move Align(val, alignment) utility function to ARMUtils.h.Johnny Chen2011-02-171-0/+5
| | | | llvm-svn: 125753
* Add emulation methods for ROR (immediate), ROR (register), and RRX.Johnny Chen2011-02-161-1/+1
| | | | | | | | | | Turns out that they can be funneled through the helper methods EmulateShiftImm()/ EmulateShiftReg() as well. Modify EmulateShiftImm() to handle SRType_ROR and SRType_RRX. And fix a typo in the impl of utility Shift_C() in ARMUtils.h. llvm-svn: 125689
* Add emulation methods for LSL (immediate), LSL (register), LSR (immediate), ↵Johnny Chen2011-02-161-9/+1
| | | | | | | | | | | and LSR (register). Create two helper methods EmulateShiftImm() and EmulateShiftReg() and have ASR, LSL, and LSR delegate to the helper methods which take an extra ARM_ShifterType parameter. The opcodes tables have not been updated yet to reflect these new entries. llvm-svn: 125633
* Modify the various shift routines to handle cases where the shift amount comesJohnny Chen2011-02-151-13/+23
| | | | | | from the bottom byte of a register. llvm-svn: 125606
* A8.6.14 ASR (immediate)Johnny Chen2011-02-151-0/+6
| | | | | | Add EmulateASRImm() Encodings T1, T2, and A1 to the opcodes tables. llvm-svn: 125592
* Add a bunch of utilities and an enum (ARM_ShifterType) for shift and rotate ↵Johnny Chen2011-02-151-0/+170
| | | | | | | | | operations pertaining to: o A2.2.1 Pseudocode details of shift and rotate operations o A8.4.3 Pseudocode details of instruction-specified shifts and rotates llvm-svn: 125575
* Add comment.Johnny Chen2011-02-141-1/+1
| | | | llvm-svn: 125509
* Enhanced the existing ARMExpandImm() and ThumbExpandImm() functions which expandJohnny Chen2011-02-141-35/+66
| | | | | | | | an imm12 into imm32 for ARM or Thumb so that they now handle carry_in/carry_out. Funnel ARMExpandImm()/ThumbExpandImm() to the enhanced ARMExpandImm_C()/ThumbExpandImm_C() functions. llvm-svn: 125508
* Move #define's out of ARMUtils.h and into a newly created file ARMDefines.h.Johnny Chen2011-01-261-36/+0
| | | | llvm-svn: 124261
* Move the generic instruction bits manipulation routines into a newly created ↵Johnny Chen2011-01-261-14/+3
| | | | | | | | file named InstructionUtils.h and modify some existing code to use them. llvm-svn: 124259
* Add Encoding T1 entry of emulate_sub_sp_imm to the g_thumb_opcodes table.Johnny Chen2011-01-261-0/+7
| | | | | | Update emulate_sub_sp_imm to handle Encoding T1. llvm-svn: 124253
* Add Encoding T2 & T3 entries of emulate_sub_sp_imm to the g_thumb_opcodes table.Johnny Chen2011-01-251-6/+52
| | | | | | Update emulate_sub_sp_imm to handle Encoding T2 & T3. llvm-svn: 124248
* Add an entry to the g_arm_opcodes table named emulate_sub_sp_imm which ↵Johnny Chen2011-01-251-0/+24
| | | | | | | | corresponds to an operation to adjust the stack pointer (allocate space for local storage). llvm-svn: 124237
* Move some #define's to the ARMUtils.h header file.Johnny Chen2011-01-241-1/+37
| | | | llvm-svn: 124141
* Add Encoding T2 & T3 of the PUSH instructions to the g_arm_opcodes table.Johnny Chen2011-01-241-0/+12
| | | | | | Plus add an extra field ARMInstrSize to the table entry type 'ARMOpcode'. llvm-svn: 124140
* Add an ARMUtils.h file to house utility functions for the ARM/Thumb ↵Johnny Chen2011-01-241-0/+23
Instruction Set Architecture. llvm-svn: 124131
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