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* Work around a stepping bug in arm64 android MPavel Labath2016-02-237-95/+354
| | | | | | | | | | | | | | | | | | | | | Summary: On arm64, linux<=4.4 and Android<=M there is a bug, which prevents single-stepping from working when the system comes back from suspend, because of incorrectly initialized CPUs. This did not really affect Android<M, because it did not use software suspend, but it is a problem for M, which uses suspend (doze) quite extensively. Fortunately, it seems that the first CPU is not affected by this bug, so this commit implements a workaround by forcing the inferior to execute on the first cpu whenever we are doing single stepping. While inside, I have moved the implementations of Resume() and SingleStep() to the thread class (instead of process). Reviewers: tberghammer, ovyalov Subscribers: aemerson, rengolin, tberghammer, danalbert, srhines, lldb-commits Differential Revision: http://reviews.llvm.org/D17509 llvm-svn: 261636
* [linux] Remove all traces of signalfd(2)Pavel Labath2016-02-231-1/+0
| | | | | | | | | | | | | | | Summary: Signalfd is not used in the code anymore, and given that the same functionality can be achieved with the new MainLoop class, it's unlikely we will need it in the future. Remove all traces of it. Reviewers: tberghammer, ovyalov Subscribers: tberghammer, danalbert, srhines, lldb-commits Differential Revision: http://reviews.llvm.org/D17510 llvm-svn: 261631
* Revert "Use BKPT instead of UDF for arm/thumb breakpoints"Tamas Berghammer2016-02-161-6/+6
| | | | | | | | | | | This reverts commit 293c18e067d663e0fe93e6f3d800c2a4bfada2b0. The BKPT instruction generates SIGBUS instead of SIGTRAP in the Linux kernel on Nexus 6 - 5.1.1 (kernel version 3.10.40). Revert the CL until we can figure out how can we hanble the SIGBUS or how to get back a SIGTRAP using the BKPT instruction. llvm-svn: 260969
* Use BKPT instead of UDF for arm/thumb breakpointsTamas Berghammer2016-02-101-6/+6
| | | | | | | | | The UDF instruction is deprecated in armv7 and in case of thumb2 instructions set it don't work well together with the IT instruction. Differential revision: http://reviews.llvm.org/D16853 llvm-svn: 260367
* Remove autoconf support from source directories.Eugene Zelenko2016-01-281-17/+0
| | | | | | Differential revision: http://reviews.llvm.org/D16662 llvm-svn: 259098
* Try to fix the mips64 build after rL257447Tamas Berghammer2016-01-121-1/+1
| | | | llvm-svn: 257469
* [LLDB][MIPS] Fix ReadRegisterValue for registers with constant 32 bit size ↵Mohit K. Bhakkad2016-01-121-1/+9
| | | | | | | | | | regardless of ABI Reviewers: clayborg, tberghammer. Subscribers: jaydeep, bhushan, sagar, nitesh.jain, lldb-commits. Differential Revision: http://reviews.llvm.org/D16060 llvm-svn: 257447
* Make the aarch64 lldb-server capable of debugging arm32 applicationsTamas Berghammer2016-01-113-10/+110
| | | | | | Differential revision: http://reviews.llvm.org/D15533 llvm-svn: 257322
* Fix for undefined behavior while updating PC value on arm-linuxOmair Javaid2016-01-051-1/+18
| | | | | | Differential revision: http://reviews.llvm.org/D15877 llvm-svn: 256847
* [LLDB][MIPS] Make register read/write to set/get the size of register ↵Sagar Thakur2016-01-051-3/+9
| | | | | | | | | | | | | | according to abi. Summary: For O32 abi register size should be 4 bytes. For N32 and N64 abi register size should be 8 bytes. This patch will make register read/write to set/get the size of register according to abi. Reviewers: clayborg, tberghammer Subscribers: lldb-commits, nitesh.jain, mohit.bhakkad, bhushan, jaydeep Differential: http://reviews.llvm.org/D15884 llvm-svn: 256834
* [LLDB] Fix Read/Write memory to be compatible with both endiansMohit K. Bhakkad2015-12-231-4/+2
| | | | | | | | Reviewers: tberghammer. Subscribers: jaydeep, bhushan, sagar, nitesh.jain,lldb-commits. Differential Revision: http://reviews.llvm.org/D15738 llvm-svn: 256331
* Remove unused mips typedefs.Oleksiy Vyalov2015-12-121-3/+1
| | | | llvm-svn: 255419
* [LLDB][MIPS] Adding call to IsMSAAvailable() while creating ↵Sagar Thakur2015-12-092-7/+11
| | | | | | | | RegisterInfoInterface This patch will fix the test case test_p_returns_correct_data_size_for_each_qRegisterInfo_attach_llgs_* of TestLldbGdbServer.py on mips. The test fails because we were sending RegisterInfo for msa registers to client even when msa registers are not available. With this commit server will send E45(end of resigters) response if msa registers are not available. llvm-svn: 255108
* [LLDB][MIPS] Using enum instead of a constant to fetch PC and CAUSE registers.Jaydeep Patil2015-12-031-2/+2
| | | | | | | SUMMARY: Using enum instead of a constant to fetch PC and CAUSE registers. llvm-svn: 254590
* PTRACE ABI to read FXSAVE area for 32-bit inferiorAbhishek Aggarwal2015-12-021-3/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: - Problem occurs when: -- 32-bit inferiors run on x86_32 machine and the architecture doesn't have AVX feature -- This causes FPRType to be set to eFPRTypeFXSAVE -- PTRACE_GETFPREGS was being used to read FXSAVE area -- For 32-bit inferiors running on x86_32 machine, PTRACE_GETFPREGS reads FSAVE area and not FXSAVE area - Changed ptrace API to PTRACE_GETREGSET for 32-bit inferiors -- This reads FPR data in FXSAVE format. -- For 64-bit inferiors, no change has been made. - Modified XFAIL for TestReturnValue.py -- Earlier, this test was passing for Linux OS -- Now, it passes for Android OS as well Change-Id: Ieed72bc969b79516fc7b263b32493aa1e7a1a2ac Signed-off-by: Abhishek Aggarwal <abhishek.a.aggarwal@intel.com> Reviewers: ovyalov, jingham, lldb-commits, tberghammer, labath Subscribers: jevinskie, labath, tberghammer, danalbert Differential Revision: http://reviews.llvm.org/D15042 llvm-svn: 254499
* [LLDB][MIPS] Clear bug 25194 - LLDB-Server Assertion raised when single ↵Sagar Thakur2015-12-011-0/+3
| | | | | | | | | | | | | | | | | | | stepping on MIPS This patch will clear bug 25194 - LLDB-Server Assertion raised when single stepping on MIPS. The problem was that while emulating instructions, old and new pc values would have garbage value in their upper 32 bits. Therefore checking if pc was changed (old_pc == new_pc) would always return false, because of which pc was not getting updated. /* If we haven't changed the PC, change it here */ if (old_pc == new_pc) { new_pc += 4; Context context; return false; } Reviewers: tberghammer, clayborg Subscribers: dsanders, lldb-commits, mohit.bhakkad, bhushan, jaydeep, nitesh.jain Differential: http://reviews.llvm.org/D14633 llvm-svn: 254379
* Add 64/128 bit arm neon register definitions on linuxTamas Berghammer2015-11-261-0/+51
| | | | | | Differential revision: http://reviews.llvm.org/D14985 llvm-svn: 254152
* [LLDB][MIPS] Getting 0 index for H/W watchpoint is not necessarily an errorMohit K. Bhakkad2015-11-231-2/+2
| | | | | | | | Reviewers: jaydeep. Subscribers: bhushan, sagar, nitesh.jain, lldb-commits. Differential Revision: http://reviews.llvm.org/D14860 llvm-svn: 253864
* Fix for AArch64 watchpoint cache corruption in case of ptrace failureOmair Javaid2015-11-061-1/+49
| | | | | | | | | | Same fix has been submitted for Arm. Review can be found here: Differential revision: http://reviews.llvm.org/D14051 llvm-svn: 252298
* Fix for Arm watchpoint cache corruption in case of ptrace failureOmair Javaid2015-10-271-0/+48
| | | | | | Differential revision: http://reviews.llvm.org/D14051 llvm-svn: 251386
* Corrects return values and typos in Arm watchpoint codeOmair Javaid2015-10-251-4/+4
| | | | | | | This is just a trivial patch that corrects a couple of return value account to function's return type. Also corrects typo in hardware breakpoint handler. llvm-svn: 251269
* Fix arm lldb-server on aarch64 deviceTamas Berghammer2015-10-232-0/+56
| | | | | | | | | | * Use PTRACE_GETVFPREGS/PTRACE_SETVFPREGS to access the floating point registers instead of the old PTRACE_GETFPREGS/PTRACE_SETFPREGS. The new call is available since armv5. * Work around a kernel issue in PTRACE_POKEUSER with reading out the full register set, modifying the neccessary value and then writing it back. llvm-svn: 251111
* Fix for random watchpoint testsuite failures on AArch64 targets.Omair Javaid2015-10-191-1/+4
| | | | | | | | This patch corrects the number of bytes of debug register resources which are written while installing or removing a breakpoint using ptrace interface on arm64 targets. Differential revision: http://reviews.llvm.org/D12522 llvm-svn: 250700
* [LLDB][MIPS] Use the correct ptrace buffer for writing register value for ↵Sagar Thakur2015-10-191-8/+9
| | | | | | | | | o32 applications For o32 applications on mips we were getting segmentation fault while launching lldb-server because of overwritting stack when using elf_gregset_t in DoWriteRegisterValue. We are now using the GPR_mips_linux buffer in DoWriteRegisterValue as done in DoReadRegisterValue also, which solves the above issue. llvm-svn: 250696
* Fix cast in arm watchpoint handling codeTamas Berghammer2015-10-131-1/+1
| | | | | | | We had an incorrect sign extension when castion from a pointer to an lldb::addr_t what broke the watchpoint hit detection on arm. llvm-svn: 250180
* X86: Change FTAG register size in FXSAVE structureAbhishek Aggarwal2015-10-121-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: - Changed from 16 bits to 8 bits for Intel Architecture -- FXSAVE structure now conforms with the layout of FXSAVE area specified by IA Architecture Software Developer Manual - Modified Linux and FreeBSD specific files to support this change -- MacOSX already uses 8 bits for ftag register - Modified TestRegisters.py and a.cpp: -- Change allows 8 bit comparison of ftag values -- Change resolves Bug 24733: Removed XFAIL for Clang as the test works and passes for Clang compiler as well -- Change provides a Generic/Better way of testing Bug 24457 and Bug 25050 by using 'int3' inline assembly in inferior Signed-off-by: Abhishek Aggarwal <abhishek.a.aggarwal@intel.com> Reviewers: ovyalov, jingham, clayborg Subscribers: tfiala, emaste Differential Revision: http://reviews.llvm.org/D13587 llvm-svn: 250022
* [LLDB][MIPS] Fix gp register value for o32 applications on 64-bit targetSagar Thakur2015-10-011-8/+1
| | | | | | | GP registers for o32 applications were always giving zero value because SetType() on the RegisterValue was causing the accessor functions to pickup the value from m_scalar of RegisterValue which is zero. In this patch byte size and byte order of register value is set at the time of setting the value of the register. llvm-svn: 249020
* Clean up register naming conventions inside lldb. Jason Molenda2015-09-151-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | "gcc" register numbers are now correctly referred to as "ehframe" register numbers. In almost all cases, ehframe and dwarf register numbers are identical (the one exception is i386 darwin where ehframe regnums were incorrect). The old "gdb" register numbers, which I incorrectly thought were stabs register numbers, are now referred to as "Process Plugin" register numbers. This is the register numbering scheme that the remote process controller stub (lldb-server, gdbserver, core file support, kdp server, remote jtag devices, etc) uses to refer to the registers. The process plugin register numbers may not be contiguous - there are remote jtag devices that have gaps in their register numbering schemes. I removed all of the enums for "gdb" register numbers that we had in lldb - these were meaningless - and I put LLDB_INVALID_REGNUM in all of the register tables for the Process Plugin regnum slot. This change is almost entirely mechnical; the one actual change in here is to ProcessGDBRemote.cpp's ParseRegisters() which parses the qXfer:features:read:target.xml response. As it parses register definitions from the xml, it will assign sequential numbers as the eRegisterKindLLDB numbers (the lldb register numberings must be sequential, without any gaps) and if the xml file specifies register numbers, those will be used as the eRegisterKindProcessPlugin register numbers (and those may have gaps). A J-Link jtag device's target.xml does contain a gap in register numbers, and it only specifies the register numbers for the registers after that gap. The device supports many different ARM boards and probably selects different part of its register file as appropriate. http://reviews.llvm.org/D12791 <rdar://problem/22623262> llvm-svn: 247741
* Fix the handling of FPR offsets in Linux arm/aarch64 register contextsTamas Berghammer2015-09-074-8/+31
| | | | | | Differential revision: http://reviews.llvm.org/D12636 llvm-svn: 246959
* Bug 24457 - X87 FPU Special Purpose RegistersAbhishek Aggarwal2015-09-072-4/+25
| | | | | | | | | | | | | | | | | | | | Summary: - For 'register read --all' command on x86_64-Linux Platform: -- Provide correct values of X87 FPU Special Purpose Registers -- Both 32-bit & 64-bit inferiors give correct values on this Platform - Added a Test Vector: -- To verify the expected behaviour of the command Signed-off-by: Abhishek Aggarwal <abhishek.a.aggarwal@intel.com> Reviewers: ashok.thirumurthi, granata.enrico, tfiala, clayborg Differential Revision: http://reviews.llvm.org/D12592 llvm-svn: 246955
* [cmake] Remove LLVM_NO_RTTI.Bruce Mitchener2015-09-031-2/+0
| | | | | | | | | | | | | | Summary: This doesn't exist in other LLVM projects any longer and doesn't do anything. Reviewers: chaoren, labath Subscribers: emaste, tberghammer, lldb-commits, danalbert Differential Revision: http://reviews.llvm.org/D12586 llvm-svn: 246749
* [NativeProcessLinux] Fix detach of multithreaded inferiorsPavel Labath2015-09-011-5/+11
| | | | | | | When detaching, we need to detach from all threads of the inferior and not just the main one. Without this, a multi-threaded inferior would usually crash once the server exits. llvm-svn: 246549
* [NativeProcessLinux] Fix assertion failure when killing a processPavel Labath2015-09-011-1/+10
| | | | | | | | | Linux sometimes sends us a PTRACE_EVENT_EXIT when an inferior process gets a SIGKILL. This can be confusing, since normally we don't expect any events when the inferior is stopped. This commit adds code to handle this situation (resume the thread and let it exit normally) and avoid an assertion failure in ResumeThread(). llvm-svn: 246539
* [LLDB][MIPS] Aligning code with rL245831Mohit K. Bhakkad2015-08-281-1/+1
| | | | | | | | Reviewers: jaydeep Subscribers: lldb-commits. Differential Revision: http://reviews.llvm.org/D12427 llvm-svn: 246293
* Error checking correction in AArch64 hardware watchpoint codeOmair Javaid2015-08-261-13/+68
| | | | | | Differential Revision: http://reviews.llvm.org/D12328 llvm-svn: 246045
* Adds support for hardware watchpoints on Arm targets.Omair Javaid2015-08-252-0/+546
| | | | | | | | | | | | | | http://reviews.llvm.org/D9703 This updated patches correct problems in arm hardware watchpoint support patch posted earlier. This patch has been tested on samsung chromebook (ARM - Linux) and PandaBoard using basic watchpoint test application. Also it was tested on Nexus 7 Android device. On chromebook linux we are able to set and clear all types of watchpoints but on android we end up getting a watchpoint packet error because we are not able to call hardware watchpoint ptrace functions successfully. llvm-svn: 245961
* Fix build on mipsSagar Thakur2015-08-251-10/+3
| | | | | | | | | | Setting and getting register values as bytes instead of depending on the 128 bit integer support in register value. This patch will fix the build failure in the release branch. Reviewers: tberghammer, clayborg, hans Subscribers: bhushan, nitesh.jain, jaydeep, lldb-commits Differential: http://reviews.llvm.org/D12275 llvm-svn: 245927
* Simplify NativeThreadLinux includesPavel Labath2015-08-241-4/+1
| | | | | | | there is no need to include architecture-specific register contexts when the generic one will suffice. llvm-svn: 245839
* [NativeProcessLinux] Pass around threads by referencePavel Labath2015-08-242-249/+185
| | | | | | | | | | | | | | | | Summary: Most NPL private functions took (shared) pointers to threads as arguments. This meant that the callee could not be sure if the pointer was valid and so most functions were peppered with null-checks. Now, I move the check closer to the source, and pass around the threads as references (which are then assumed to be valid). Reviewers: tberghammer Subscribers: lldb-commits Differential Revision: http://reviews.llvm.org/D12237 llvm-svn: 245831
* [NativeProcessLinux] Reduce the number of castsPavel Labath2015-08-212-68/+61
| | | | | | | | | | | | | | | Summary: NPL used to be peppered with casts of the NativeThreadProtocol objects into NativeThreadLinux. I move these closer to the source where we obtain these objects. This way, the rest of the code can assume we are working with the correct type of objects. Reviewers: ovyalov, tberghammer Subscribers: lldb-commits Differential Revision: http://reviews.llvm.org/D12187 llvm-svn: 245681
* [NativeProcessLinux] Fix a bug in instruction-stepping over thread creationPavel Labath2015-08-204-257/+107
| | | | | | | | | | | | | | | | | | | | | | | Summary: There was a bug in NativeProcessLinux, where doing an instruction-level single-step over the thread-creation syscall resulted in loss of control over the inferior. This happened because after the inferior entered the thread-creation maintenance stop, we unconditionally performed a PTRACE_CONT, even though the original intention was to do a PTRACE_SINGLESTEP. This is fixed by storing the original state of the thread before the stop (stepping or running) and then performing the appropriate action when resuming. I also get rid of the callback in the ThreadContext structure, which stored the lambda used to resume the thread, but which was not used consistently. A test verifying the correctness of the new behavior is included. Reviewers: ovyalov, tberghammer Subscribers: lldb-commits Differential Revision: http://reviews.llvm.org/D12104 llvm-svn: 245545
* On Linux, clear the signal mask of the launched inferiorPavel Labath2015-08-191-1/+11
| | | | | | | | | | | | | | | | | | | Summary: Due to fork()/execve(), the launched inferior inherits the signal mask of its parent (lldb-server). But because lldb-server modifies its signal mask (It blocks SIGCHLD, for example), the inferior starts with some signals being initially blocked. One consequence is that TestCallThatRestarts.ExprCommandThatRestartsTestCase (test/expression_command/call-restarts) fails because sigchld_handler() in lotta-signals.c is not called, due to the SIGCHLD signal being blocked. To prevent the signal masking done by lldb-server from affecting the created inferior, the signal mask of the inferior is now cleared before the execve(). Patch by: Yacine Belkadi Reviewers: ovyalov, labath Subscribers: lldb-commits Differential Revision: http://reviews.llvm.org/D12138 llvm-svn: 245436
* Fix lldb-server arm-linux-g++ buildOmair Javaid2015-08-191-1/+1
| | | | llvm-svn: 245428
* [LLGS] Avoid misrepresenting log lines as inferior outputPavel Labath2015-08-181-1/+4
| | | | | | | | | | | | | | | | Summary: in case we are logging to stdout, any log lines from the forked child can be misconstrued to be inferior output. To avoid this, we disable all logging immediately after forking. I also fix the implementatoion of DisableAllLogChannels, which was a no-op before this commit. Reviewers: clayborg, ovyalov Subscribers: dean, lldb-commits Differential Revision: http://reviews.llvm.org/D12083 llvm-svn: 245272
* [LLDB][MIPS] Fix offsets of all register sets and add MSA regset and FRE=1 ↵Sagar Thakur2015-08-173-64/+337
| | | | | | | | | | | | | | | | mode support This patch : - Fixes offsets of all register sets for Mips. - Adds MSA register set and FRE=1 mode support for FP register set. - Separates lldb register numbers and register infos of freebsd/mips64 from linux/mips64. - Re-orders the register numbers of all kinds for mips to be consistent with freebsd order of register numbers. Reviewers: jaydeep, clayborg, jasonmolenda, ovyalov, emaste Subscribers: tberghammer, ovyalov, emaste, mohit.bhakkad, nitesh.jain, bhushan Differential: http://reviews.llvm.org/D10919 llvm-svn: 245217
* Removing redundant check from r244875Ravitheja Addepally2015-08-131-12/+6
| | | | llvm-svn: 244886
* Fix Linux build after r244875Tamas Berghammer2015-08-131-10/+2
| | | | llvm-svn: 244877
* Set orig_eax to -1 for Linux x86 platformsRavitheja Addepally2015-08-131-0/+28
| | | | | | | | | | | | | | | | | Summary: For Linux x86 based environments the orig_eax/orig_rax register should be set to -1 to prevent the instruction pointer to be decremented, which was the cause for the SIGILL exception. Fix for Bug 23659 Reviewers: zturner, ashok.thirumurthi, mikesart, jingham, clayborg Subscribers: clayborg, labath Differential Revision: http://reviews.llvm.org/D11411 llvm-svn: 244875
* [LLDB][MIPS] Handle false positives for MIPS hardware watchpointsJaydeep Patil2015-08-133-1/+116
| | | | | | | | | | | | | | | | SUMMARY: Last 3bits of the watchpoint address are masked by the kernel. For example, n is at 0x120010d00 and m is 0x120010d04. When a watchpoint is set at m, then watch exception is generated even when n is read/written. To handle this case, instruction at PC is emulated to find the base address of the load/store instruction. This address is then appended to the description of the stop-info packet. Client then reads this information to check whether the user has set a watchpoint on this address. Reviewers: jingham, clayborg Subscribers: nitesh.jain, mohit.bhakkad, sagar, bhushan and lldb-commits Differential Revision: http://reviews.llvm.org/D11672 llvm-svn: 244864
* Fix AArch64 watchpoint handlers in NativeRegisterContextLinux_arm64Omair Javaid2015-08-122-60/+81
| | | | | | http://reviews.llvm.org/D11899 llvm-svn: 244750
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