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* [LLVM][MIPS] Add (D)SUBU, (D)ADDU, LUI instructions emulation . Fix ↵Nitesh Jain2016-08-024-41/+301
| | | | | | | | | | | | emulation for (D)ADDIU, SD/SW and LW/LD instructions Reviewers: clayborg, jaydeep, bhushan Subscribers: mohit.bhakkad, slthakur, sdardis, lldb-commits Differential Revision: https://reviews.llvm.org/D20357 llvm-svn: 277426
* [LLDB][MIPS] Fix Emulation of Compact branch and ADDIU instructionsSagar Thakur2016-06-232-32/+33
| | | | | | | | | | | | | | Patch by Nitesh Jain. This patch contains 2 changes: - Corrected target address calculation of compact branch instructions to reflect changes in disassembler (http://reviews.llvm.org/D17540). - Added emulation for (missing) 'Addiu' instruction. Reviewers :jaydeep, bhushan, clayborg Differential: http://reviews.llvm.org/D21064 llvm-svn: 273535
* Fix ARM instruction emulation tests on big-endian systemsUlrich Weigand2016-04-143-62/+70
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Running the ARM instruction emulation test on a big-endian system would fail, since the code doesn't respect endianness properly. In EmulateInstructionARM::TestEmulation, code assumes that an instruction opcode read in from the test file is in target byte order, but it was in fact read in in host byte order. More difficult to fix, the EmulationStateARM structure models the overlapping sregs and dregs by a union in _sd_regs. This only works correctly if the host is a little-endian system. I've removed the union in favor of a simple array containing the 32 sregs, and changed any code accessing dregs to explicitly use the correct two sregs overlaying that dreg in the proper target order. Also, the EmulationStateARM::ReadPseudoMemory and WritePseudoMemory track memory as a map of uint32_t values in host byte order, and implement 64-bit memory accessing by splitting them up into two uint32_t ones. However, callers expect memory contents to be provided in the form of a byte array (in target byte order). This means the uint32_t contents need to be byte-swapped on BE systems, and when splitting up a 64-bit access into two 32-bit ones, byte order has to be respected. Differential Revision: http://reviews.llvm.org/D18984 llvm-svn: 266314
* Make Scalar::GetBytes and RegisterValue::GetBytes constUlrich Weigand2016-04-142-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Scalar::GetBytes provides a non-const access to the underlying bytes of the scalar value, supposedly allowing for modification of those bytes. However, even with the current implementation, this is not really possible. For floating-point scalars, the pointer returned by GetBytes refers to a temporary copy; modifications to that copy will be simply ignored. For integer scalars, the pointer refers to internal memory of the APInt implementation, which isn't supposed to be directly modifyable; GetBytes simply casts aways the const-ness of the pointer ... With my upcoming patch to fix Scalar::GetBytes for big-endian systems, this problem is going to get worse, since there we need temporary copies even for some integer scalars. Therefore, this patch makes Scalar::GetBytes const, fixing all those problems. As a follow-on change, RegisterValues::GetBytes must be made const as well. This in turn means that the way of initializing a RegisterValue by doing a SetType followed by writing to GetBytes no longer works. Instead, I've changed SetValueFromData to do the equivalent of SetType itself, and then re-implemented SetFromMemoryData to work on top of SetValueFromData. There is still a need for RegisterValue::SetType, since some platform-specific code uses it to reinterpret the contents of an already filled RegisterValue. To make this usage work in all cases (even changing from a type implemented via Scalar to a type implemented as a byte buffer), SetType now simply copies the old contents out, and then reloads the RegisterValue from this data using the new type via SetValueFromData. This in turn means that there is no remaining caller of Scalar::SetType, so it can be removed. The only other follow-on change was in MIPS EmulateInstruction code, where some uses of RegisterValue::GetBytes could be made const trivially. Differential Revision: http://reviews.llvm.org/D18980 llvm-svn: 266310
* Consolidate the knowledge of what arm cores are always executingJason Molenda2016-04-051-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | in thumb mode into one method in ArchSpec, replace checks for specific cores in the disassembler with calls to this. Also call this from the arm instruction emulation code. The determination of whether a given ArchSpec is thumb-only is still a bit of a hack, but at least the hack is consolidated into a single place. In my original version of this patch http://reviews.llvm.org/D13578 I was calling into llvm's feature arm feature tables to make this determination, like #include "llvm/Support/TargetRegistry.h" #include "llvm/MC/MCSubtargetInfo.h" #include "llvm/../../lib/Target/ARM/ARMGenRegisterInfo.inc" #include "llvm/../../lib/Target/ARM/ARMFeatures.h" [...] std::string triple (GetTriple().getTriple()); const char *cpu = ""; const char *features_str = ""; const llvm::Target *curr_target = llvm::TargetRegistry::lookupTarget(triple.c_str(), Error); std::unique_ptr<llvm::MCSubtargetInfo> subtarget_info_up (curr_target->createMCSubtargetInfo(triple.c_str(), cpu, features_str)); if (subtarget_info_up->getFeatureBits()[llvm::ARM::FeatureNoARM]) { return true; } but those tables are post-llvm-build generated and linking against them for all of our different build system methods was a big hiccup that I haven't had time to revisit convincingly. I'll keep that reviews.llvm.org patch around to remind myself that I need to take another run at linking against the necessary tables again in llvm. <rdar://problem/23022803> llvm-svn: 265377
* Fix all of the unannotated switch cases to annotate the fall through or do ↵Greg Clayton2016-02-261-1/+1
| | | | | | the right thing and break. llvm-svn: 261950
* Fix handling of the arm IT instruction in the unwinderTamas Berghammer2016-02-102-22/+20
| | | | | | | | | | | | | | | | | | | | | | | | | The IT instruction can specify condition code for up to 4 consecutive instruction and it is used quite often by clang in epilogues causing an issue when trying to unwind from locations covered by the IT instruction and for locatins inmediately after the IT instruction. Changes made to fix it: * Introduce the concept of conditional instruction block what is a list of consecutive instructions with the same condition. We update the unwind information during the conditional instruction block and when we reach the end of it (first instruction with a differemt condition) then we restore the unwind information we had before the condition. * Fix a bug in the ARM instruction emulator where neither PC nor the ITSTATE was advanced when we reached an instruction what we can't decode. After the change we have no regression on android-arm running the regular test suit and TestStandardUnwind also passes when running it with clang as the compiler (previously it failed on an IT instruction). Differential revision: http://reviews.llvm.org/D16814 llvm-svn: 260368
* Fix single stepping over the IT instructionTamas Berghammer2016-02-021-5/+16
| | | | | | | | | | | | | | | | | The ARM instruction emulator had 2 bugs related to the handling of the IT instruction causing an error in single stepping: * We haven't initialized the IT mask from the CPSR so if the last instruction of the IT block is a branch and the condition is false then the emulator evaluated the branch what resulted in an incorrect pc for the next instruction. * The ITSTATE was advanced before the execution of each instruction. As a result the emulator was using the condition of following instruction in every case. The ITSTATE should be edvanced after the execution of an instruction except after an IT instruction. Differential revision: http://reviews.llvm.org/D16772 llvm-svn: 259509
* Remove autoconf support from source directories.Eugene Zelenko2016-01-284-56/+0
| | | | | | Differential revision: http://reviews.llvm.org/D16662 llvm-svn: 259098
* Update for LLVM changeBenjamin Kramer2016-01-262-2/+2
| | | | llvm-svn: 258819
* Fix some compiler warnings with MSVC 2015.Zachary Turner2016-01-131-1/+1
| | | | llvm-svn: 257671
* [LLDB][MIPS] Merge emulation of similar instructions for MIPS64Bhushan D. Attarde2016-01-122-1769/+379
| | | | | | | | | | | SUMMARY: This patch merges emulation of similar instructions into a single function (wherever possible) to remove code duplication. Reviewers: clayborg Subscribers: mohit.bhakkad, sagar, jaydeep, lldb-commits Differential Revision: http://reviews.llvm.org/D16051 llvm-svn: 257442
* Fix build warnings after rL256915Bhushan D. Attarde2016-01-061-8/+8
| | | | llvm-svn: 256929
* [LLDB][MIPS32]Merge emulation of similar instructionsBhushan D. Attarde2016-01-062-1917/+521
| | | | | | | | | | | SUMMARY: This patch merges emulation of similar instructions into a single function (wherever possible) to remove code duplication. Reviewers: clayborg Subscribers: mohit.bhakkad, sagar, jaydeep, lldb-commits Differential Revision: http://reviews.llvm.org/D15886 llvm-svn: 256915
* Fix emulation of the thumb str instructionTamas Berghammer2015-12-211-2/+10
| | | | llvm-svn: 256147
* Fix the emulation of arm strd instructionTamas Berghammer2015-12-181-2/+5
| | | | | | | The incorrect instruction emulation caused issues in the stack unwinding code when strd was used to push 2 register to the stack with writeback. llvm-svn: 256000
* Add support for the new (added last week) llvm::Triple::WatchOS and ::TvOSJason Molenda2015-11-051-1/+2
| | | | | | | | | | in places where we check for Triple::IOS. They're mostly the same as far as lldb is conerned. . Also add a base cass implementation for Process::IsAlive - Greg added this last year but it didn't get upstreamed. llvm-svn: 252227
* Fix Clang-tidy modernize-use-override warnings in some files in ↵Eugene Zelenko2015-10-212-66/+69
| | | | | | | | source/Plugins; other minor fixes. Differential Revision: http://reviews.llvm.org/D13916 llvm-svn: 250872
* Silence some -Wunused-but-set-variable with gcc 5.2.0Saleem Abdulrasool2015-10-181-6/+0
| | | | | | Cleanup some unused variables. NFC. llvm-svn: 250661
* Make use of lldv::Triple::isAndroidTamas Berghammer2015-10-142-2/+2
| | | | | | | | It is a new function added to the llvm::Triple class to simplify the checking if we are targeting android to clean up the confusion between android being an OS or an environment. llvm-svn: 250286
* [LLDB][MIPS64] Adding mips64 reaturn address register for unwind planMohit K. Bhakkad2015-10-141-0/+1
| | | | llvm-svn: 250267
* Addressing warning due to rL249651Mohit K. Bhakkad2015-10-091-3/+0
| | | | llvm-svn: 249809
* [LLDB][MIPS] microMIPS load/store instruction emulation for hardware watchpointsMohit K. Bhakkad2015-10-081-18/+55
| | | | | | | | Reviewers: clayborg. Subscribers: jaydeep, bhushan, sagar, nitesh.jain, lldb-commits. Differential Revision: http://reviews.llvm.org/D13493 llvm-svn: 249651
* Remove GetShortPluginName.Bruce Mitchener2015-10-063-18/+0
| | | | | | | | | | | | Summary: This was deprecated and removed. Reviewers: clayborg Subscribers: lldb-commits Differential Revision: http://reviews.llvm.org/D13463 llvm-svn: 249452
* Fix virtual/override warnings in new MIPS code.Bruce Mitchener2015-10-061-17/+17
| | | | | | | | | | Reviewers: bhushan, tberghammer Subscribers: lldb-commits Differential Revision: http://reviews.llvm.org/D13462 llvm-svn: 249405
* [MIPS] Emulate microMIPS instructionsBhushan D. Attarde2015-10-062-14/+762
| | | | | | | | | | | | | | | | | | | | | | SUMMARY: This patch includes: 1. Emulation of prologue/epilogue and branch instructions for microMIPS. 2. Setting up alternate disassembler (to be used for microMIPS). So there will be two disassembler instances, one for microMIPS and other for MIPS. Appropriate disassembler will be used based on the address class of instruction address. 3. Some of the branch instructions does not have fixed sized delay slot, that means delay slot instruction can be of 2-byte or 4-byte. For this "m_next_inst_size" has been introduced which stores the size of next instruction (i.e size of delay slot instruction in case of branch). This can be used wherever the size of next instruction is required. 4. A minor change to use mips32 register names instead of mips64 names. Reviewers: clayborg, tberghammer Subscribers: mohit.bhakkad, sagar, jaydeep, nitesh.jain, lldb-commits Differential Revision: http://reviews.llvm.org/D13282 llvm-svn: 249381
* Fix register names in EmulateInstructionMIPS.cppTamas Berghammer2015-09-221-78/+78
| | | | llvm-svn: 248281
* [MIPS32] Emulate MSA instructions for MIPS32Sagar Thakur2015-09-222-108/+386
| | | | | | | | | This patch adds MSA branch instruction emulation for MIPS32. Reviewers: tberghammer, jaydeep Subscribers: mohit.bhakkad, bhushan, nitesh.jain Differential: http://reviews.llvm.org/D12898 llvm-svn: 248277
* Clean up register naming conventions inside lldb. Jason Molenda2015-09-152-763/+763
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | "gcc" register numbers are now correctly referred to as "ehframe" register numbers. In almost all cases, ehframe and dwarf register numbers are identical (the one exception is i386 darwin where ehframe regnums were incorrect). The old "gdb" register numbers, which I incorrectly thought were stabs register numbers, are now referred to as "Process Plugin" register numbers. This is the register numbering scheme that the remote process controller stub (lldb-server, gdbserver, core file support, kdp server, remote jtag devices, etc) uses to refer to the registers. The process plugin register numbers may not be contiguous - there are remote jtag devices that have gaps in their register numbering schemes. I removed all of the enums for "gdb" register numbers that we had in lldb - these were meaningless - and I put LLDB_INVALID_REGNUM in all of the register tables for the Process Plugin regnum slot. This change is almost entirely mechnical; the one actual change in here is to ProcessGDBRemote.cpp's ParseRegisters() which parses the qXfer:features:read:target.xml response. As it parses register definitions from the xml, it will assign sequential numbers as the eRegisterKindLLDB numbers (the lldb register numberings must be sequential, without any gaps) and if the xml file specifies register numbers, those will be used as the eRegisterKindProcessPlugin register numbers (and those may have gaps). A J-Link jtag device's target.xml does contain a gap in register numbers, and it only specifies the register numbers for the registers after that gap. The device supports many different ARM boards and probably selects different part of its register file as appropriate. http://reviews.llvm.org/D12791 <rdar://problem/22623262> llvm-svn: 247741
* [LLDB][MIPS] MIPS load/store instruction emulation for hardware watchpointsMohit K. Bhakkad2015-09-094-77/+328
| | | | | | | | Reviewers: clayborg. Subscribers: jaydeep, bhushan, sagar, nitesh.jain, lldb-commits. Differential Revision: http://reviews.llvm.org/D12670 llvm-svn: 247129
* [cmake] Remove LLVM_NO_RTTI.Bruce Mitchener2015-09-034-8/+0
| | | | | | | | | | | | | | Summary: This doesn't exist in other LLVM projects any longer and doesn't do anything. Reviewers: chaoren, labath Subscribers: emaste, tberghammer, lldb-commits, danalbert Differential Revision: http://reviews.llvm.org/D12586 llvm-svn: 246749
* [MIPS64] Emulate MSA branch instructionsSagar Thakur2015-09-032-36/+314
| | | | | | | | | This patch adds MSA branch instruction emulation for MIPS64. Reviewers: tberghammer, jaydeep Subscribers: tberghammer, lldb-commits, nitesh.jain, mohit.bhakkad (Mohit Bhakkad), bhushan (Bhushan Attarde) Differential: http://reviews.llvm.org/D12356 llvm-svn: 246745
* Fix assertion failure caused by r245546Tamas Berghammer2015-08-211-2/+1
| | | | | | | | Change the way EmulateInstruction::eContextPopRegisterOffStack handled in UnwindAssemblyInstEmulation::WriteRegister to accomodate for additional cases when eContextPopRegisterOffStack (pop PC/FLAGS). llvm-svn: 245690
* Improve instruction emulation based stack unwindingTamas Berghammer2015-08-202-8/+13
| | | | | | | | | | | On ARM there is no difference petween a pop and a load instruction so a register can be loaded multiple times during the function. Add check to threat the load as a restore only if it do the restore from the same location where the register was saved. Differential revision: http://reviews.llvm.org/D11947 llvm-svn: 245546
* [LLDB][MIPS] Fix offsets of all register sets and add MSA regset and FRE=1 ↵Sagar Thakur2015-08-172-66/+66
| | | | | | | | | | | | | | | | mode support This patch : - Fixes offsets of all register sets for Mips. - Adds MSA register set and FRE=1 mode support for FP register set. - Separates lldb register numbers and register infos of freebsd/mips64 from linux/mips64. - Re-orders the register numbers of all kinds for mips to be consistent with freebsd order of register numbers. Reviewers: jaydeep, clayborg, jasonmolenda, ovyalov, emaste Subscribers: tberghammer, ovyalov, emaste, mohit.bhakkad, nitesh.jain, bhushan Differential: http://reviews.llvm.org/D10919 llvm-svn: 245217
* [LLDB][MIPS] Handle false positives for MIPS hardware watchpointsJaydeep Patil2015-08-132-19/+90
| | | | | | | | | | | | | | | | SUMMARY: Last 3bits of the watchpoint address are masked by the kernel. For example, n is at 0x120010d00 and m is 0x120010d04. When a watchpoint is set at m, then watch exception is generated even when n is read/written. To handle this case, instruction at PC is emulated to find the base address of the load/store instruction. This address is then appended to the description of the stop-info packet. Client then reads this information to check whether the user has set a watchpoint on this address. Reviewers: jingham, clayborg Subscribers: nitesh.jain, mohit.bhakkad, sagar, bhushan and lldb-commits Differential Revision: http://reviews.llvm.org/D11672 llvm-svn: 244864
* Revert r244308 since it's introducing test regressions on Linux:Oleksiy Vyalov2015-08-102-66/+66
| | | | | | | | - TestLldbGdbServer.py both clang & gcc, i386 and x86_64 - TestConstVariables.py gcc, i386 and x86_64 - 112 failures clang, i386 llvm-svn: 244514
* [LLDB][MIPS] Fix offsets of all register sets and add MSA regset and FRE=1 ↵Sagar Thakur2015-08-072-66/+66
| | | | | | | | | | | | | | | | | | mode support This change : - Fixes offsets of all register sets for Mips. - Adds MSA register set and FRE=1 mode support for FP register set. - Separates lldb register numbers and register infos of freebsd/mips64 from linux/mips64. - Re-orders the register numbers of all kinds for mips to be consistent with freebsd order of register numbers. - Eliminates ENABLE_128_BIT_SUPPORT and union ValueData from Scalar.cpp and uses llvm::APInt and llvm::APFloat for all integer and floating point types. Reviewers : emaste, jaydeep, clayborg Subscribers : emaste, mohit.bhakkad, nitesh.jain, bhushan Differential : http://reviews.llvm.org/D10919 llvm-svn: 244308
* Fix read/write context in EmulateInstructionARM strd/ldrdTamas Berghammer2015-07-291-4/+17
| | | | llvm-svn: 243521
* Remove non-utf-8 characters from EmulateInstructionARMTamas Berghammer2015-07-291-142/+142
| | | | llvm-svn: 243520
* Fix warnings related to virtual functions not being marked as override.Greg Clayton2015-07-221-20/+19
| | | | llvm-svn: 242918
* Improve aarch64 instruction emulationTamas Berghammer2015-07-202-86/+216
| | | | | | | * Add emulation for STR/LDR immediate instructions * Cleanup existing emulation code llvm-svn: 242671
* Improve conditional opcode handling in emulation based unwindingTamas Berghammer2015-07-174-60/+34
| | | | | | | | | | Don't chane the CFI information when a conditional instruction is emulated (eg.: popeq {r0, pc}) because the CFI for the next instruction should be the same as the CFI for the current instruction. Differential revision: http://reviews.llvm.org/D11258 llvm-svn: 242519
* [LLDB][MIPS] Detect MIPS application specific extensions like micromipsJaydeep Patil2015-07-162-2/+28
| | | | | | | | | | | | | | SUMMARY: The patch detects MIPS application specific extensions (ASE) like micromips by reading ELF header.e_flags and SHT_MIPS_ABIFLAGS section. MIPS triple does not contain ASE information like micromips, mips16, DSP, MSA etc. These can be read from header.e_flags or SHT_MIPS_ABIFLAGS section. Reviewers: clayborg Subscribers: mohit.bhakkad, sagar, lldb-commits Differential Revision: http://reviews.llvm.org/D11133 llvm-svn: 242381
* [Makefiles] Align library names with CMake buildKeno Fischer2015-07-144-12/+12
| | | | | | | | | | | | Summary: This aligns the library names used by the Makefile build to be the same as those create by the CMake build to make switching between the two easier. The only major difficulty was lldbHost which was one library in the CMake system and several in the Makefile system. Most of the other changes are trivial renames. Reviewers: labath Subscribers: emaste, tberghammer, lldb-commits Differential Revision: http://reviews.llvm.org/D11154 llvm-svn: 242196
* Add branch emulation to aarch64 instruction emulatorTamas Berghammer2015-06-262-48/+374
| | | | | | | | | The emulation of the branches are required by the new stack unwinding logic to reinstantiate the prologue at the right place. Differential revision: http://reviews.llvm.org/D10702 llvm-svn: 240769
* Remove unused variableEd Maste2015-06-241-1/+0
| | | | llvm-svn: 240547
* Improve instruction emulation based stack unwinding on ARMTamas Berghammer2015-06-242-117/+204
| | | | | | | | | | | | | | | | | | | | | | | * Add and fix the emulation of several instruction. * Disable frame pointer usage on Android. * Specify return address register for the unwind plan instead of explict tracking the value of RA. * Replace prologue detection heuristics (unreliable in several cases) with a logic to follow the branch instructions and restore the CFI value based on them. The target address for a branch should have the same CFI as the source address (if they are in the same function). * Handle symbols in ELF files where the symbol size is not specified with calcualting their size based on the next symbol (already done in MachO files). * Fix architecture in FuncUnwinders with filling up the inforamtion missing from the object file with the architecture of the target. * Add code to read register wehn the value is set to "IsSame" as it meanse the value of a register in the parent frame is the same as the value in the current frame. Differential revision: http://reviews.llvm.org/D10447 llvm-svn: 240533
* [LLDB][MIPS] MIPS32 branch emulation and single-steppingJaydeep Patil2015-06-233-106/+2598
| | | | | | | | | | | | | | | SUMMARY: This patch implements 1. Emulation of MIPS32 branch instructions 2. Enable single-stepping for MIPS32 instructions 3. Correction in emulation of MIPS64 branch instructions with delay slot 4. Adjust breakpoint address when breakpoint is hit in a forbidden slot of compact branch instruction Reviewers: clayborg Subscribers: mohit.bhakkad, sagar, bhushan, lldb-commits, emaste, nitesh.jain Differential Revision: http://reviews.llvm.org/D10596 llvm-svn: 240373
* Test CommitJaydeep Patil2015-06-221-0/+2
| | | | llvm-svn: 240280
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