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* Add impl for EmulateMvnRdImm() -- "MVN (immediate)". Plus zero out the arg0 ↵Johnny Chen2011-02-141-6/+64
| | | | | | | | | field of the context of eContextImmediate type, since the immediate value is known from the argument value to WriteRegisterUnsigned() callback already. llvm-svn: 125518
* Add entries for Encodings T1 and A1 of "MVN (immediate)" to g_arm_opcodes ↵Johnny Chen2011-02-122-0/+39
| | | | | | | | and g_thumb_opcodes tables. The corresponding EmulateMvnRdImm() method impl is empty for now. llvm-svn: 125425
* Add helper methods InITBlock() and LastInITBlock() to EmulateInstructionARM ↵Johnny Chen2011-02-122-15/+32
| | | | | | | | | class instead of calling out to m_it_session.InITBlock()/LastInITBlock(), which simplifies the coding a bit. llvm-svn: 125421
* Add EmulateBXRm() ("Branch and Exchange") to both g_arm_opcodes and ↵Johnny Chen2011-02-122-3/+62
| | | | | | g_thumb_opcodes table. llvm-svn: 125418
* - Add three more instruction contexts to EmulateInstruction:Caroline Tice2011-02-112-11/+215
| | | | | | | | | | | | | | eContextAdjustBaseRegister, eContextRegisterStore and eContextWriteMemoryRandomBits. - Implement a version of WriteBits32UnknownToMemory for writing to memory. - Modify EmulateLDM, EmulateLDMDA, EmulateLDMDB and EmulateLDMIB to use the eContextAdjustBaseRegister context when appropriate. - Add code to emulate the STM/STMIA/STMEA Arm instruction. llvm-svn: 125414
* Add EmulateCmpRnRm() for Encodings T1 & T2 to the g_thumb_opcodes table to ↵Johnny Chen2011-02-112-0/+72
| | | | | | | | emulate CMP (register) operations. llvm-svn: 125413
* Rearraned some emulate instruction entries under the appropriate category.Johnny Chen2011-02-111-9/+9
| | | | llvm-svn: 125405
* Handle the case of interworking branch for EmulateLDMDA.Johnny Chen2011-02-111-1/+2
| | | | llvm-svn: 125392
* Add Thumb2 LDR (literal) instruction into the g_thumb_opcodes table.Johnny Chen2011-02-112-11/+52
| | | | | | | Change the method name from *LDRRdPCRelative to *LDRRtPCRelative to be compliant with the ARM Arch Manual which uses Rt for the destination register. llvm-svn: 125390
* Fix build.Johnny Chen2011-02-111-0/+1
| | | | llvm-svn: 125379
* Add new instruction context, eContextWriteRegisterRandomBits.Caroline Tice2011-02-112-7/+167
| | | | | | | | | | | Add new utility function, WriteBits32Unknown Modify the LDM* instruction emulation functions to call WriteBits32Unknown. Add missing overview comments to the LDM* instruction emulation functions. Add code to emulate LDMDA Arm instruction. llvm-svn: 125377
* Add an entry for CMP (immediate) (Encoding T1) to the g_thumb_opcodes table.Johnny Chen2011-02-112-4/+58
| | | | llvm-svn: 125333
* Add a helper method AddWithCarry() to the EmulateInstructionARM class.Johnny Chen2011-02-112-0/+31
| | | | llvm-svn: 125329
* Namings are important. Renamed Bits32(const uint32_t val, uint32_t bit) to ↵Johnny Chen2011-02-101-25/+25
| | | | | | | | Bit32(val, bit) and SetBits32(uint32_t &bits, uint32_t bit, uint32_t val) to SetBit32(bits, bit, val). llvm-svn: 125312
* Some refactorings to use the convenience function: Bits32(const uint32_t ↵Johnny Chen2011-02-101-23/+23
| | | | | | value, const uint32_t bit). llvm-svn: 125303
* Add some comment markers.Johnny Chen2011-02-101-0/+12
| | | | llvm-svn: 125302
* Add a generic EmulateMovRdRm() method and modify/add entries to the ↵Johnny Chen2011-02-102-4/+46
| | | | | | | | g_thumb_opcodes table. Also add some more defines and convenience functions. llvm-svn: 125300
* Rearrange the order of g_thumb_opcodes entries.Johnny Chen2011-02-101-3/+4
| | | | llvm-svn: 125295
* Add EmulateLDRRtRnImm() for EncodingT1 of LDR (immediate, Thumb) to the ↵Johnny Chen2011-02-102-1/+120
| | | | | | | | g_thumb_opcodes table, and a helper method UnalignedSupport(). llvm-svn: 125258
* Add a new member variable m_new_inst_cpsr to catch the to-be-updated stateJohnny Chen2011-02-092-4/+7
| | | | | | | | of the CPSR during the course of executing an opcode, and modified SelectInstrSet() to update this variable instead of the original m_inst_cpsr, which should be the cached copy of the CPSR at the beginning of executing the opcode. llvm-svn: 125244
* Add EmulateAddRdnRm() for EncodingT2 of ADD(register) to the g_thumb_opcodes ↵Johnny Chen2011-02-092-0/+104
| | | | | | | | table, and a helper method ALUWritePC(Context&, uint32_t). llvm-svn: 125241
* Modified existing Emulate* methods to call LoadWritePC(context, data) where ↵Johnny Chen2011-02-091-3/+6
| | | | | | | | appropriate to effect an interworking branch if the ArchVersion() is ARMv5T and above. llvm-svn: 125227
* Modified EmulatePop impl to use the helper method LoadWritePC(context, data) ↵Johnny Chen2011-02-091-1/+2
| | | | | | | | since if PC is in the list of registers to be load and we're in ARMv5T and above, this is an interworking branch. llvm-svn: 125212
* If the CPSR is changed due to switching between ARM and Thumb ISETSTATE,Johnny Chen2011-02-091-2/+19
| | | | | | | we want to record it and issue a WriteRegister callback so the clients can track the mode changes accordingly. llvm-svn: 125209
* Patch from Kirk Beitz to make things compile on MinGW minus the putenv part.Greg Clayton2011-02-091-3/+4
| | | | llvm-svn: 125199
* Add some helper methods to the EmulateInstructionARM class as a first step ↵Johnny Chen2011-02-092-12/+61
| | | | | | | | | in the refactorings of EmulateInstructionARM.cpp file, which will be modified later to take advantage of these helper methods. llvm-svn: 125148
* Add code to emulate the LDMIB Arm instruction.Caroline Tice2011-02-082-30/+127
| | | | | | | | Modify code for LDM and LDMDB instructions to only create one context and to reuse it, rather than creating multiple contexts. llvm-svn: 125139
* Fix typos.Johnny Chen2011-02-081-4/+4
| | | | llvm-svn: 125138
* Add EmulateCB() entry to the g_thumb_opcodes table to represent "Compare and ↵Johnny Chen2011-02-082-12/+68
| | | | | | | | Branch on NonZero and Compare and Branch on Zero" operations. llvm-svn: 125134
* Add code to emulate LDMDB Arm instruction.Caroline Tice2011-02-082-2/+143
| | | | llvm-svn: 125133
* Add code to emulate the LDM ARM instruction.Caroline Tice2011-02-082-3/+152
| | | | llvm-svn: 125118
* Add missing implementation for "BL, BLX (immediate)" Encoding T1 and an ↵Johnny Chen2011-02-081-17/+41
| | | | | | | | entry for "bl <label>" into g_thumb_opcodes table. llvm-svn: 125112
* Add missing implementation for "BL, BLX (immediate)" Encoding A1.Johnny Chen2011-02-081-0/+7
| | | | llvm-svn: 125103
* Add implementation for EmulateInstructionARM::EmulateB() and fixed two typos ↵Johnny Chen2011-02-082-52/+163
| | | | | | | | | | | | in g_thumb_opcodes as pointed out By Caroline. Refactored a little bit by adding two new helper methods to the EmulateInstructionARM class: o BranchWritePC() o BXWritePC() llvm-svn: 125059
* Add EmulateInstructionARM::EmulateB entries to the g_arm_opcodes and ↵Johnny Chen2011-02-072-2/+40
| | | | | | | | g_thumb_opcodes tables. EmulateB() has empty impl. and needs to be filled in later. llvm-svn: 125048
* Header patch, virtual dtor patch and missed UUID patch from Kirk Beitz.Greg Clayton2011-02-051-1/+1
| | | | llvm-svn: 124931
* Handle the thumb branch instructions which have their cond bits embedded in ↵Johnny Chen2011-02-051-0/+17
| | | | | | the instruction stream. llvm-svn: 124925
* Add EmulateInstructionARM::EmulateIT() to the g_thumb_opcodes table,Johnny Chen2011-02-052-4/+49
| | | | | | | | | to represent the the 'If Then' instruction which makes up to four following instructions (the IT block)conditional. Hook up ITSession utility class as a member variable of EmulateInstructionARM. llvm-svn: 124915
* Add a utility class ITSession to maintain the ITState for the Thumb ISA.Johnny Chen2011-02-042-0/+88
| | | | llvm-svn: 124906
* Add EmulateInstructionARM::EmulateSVC() to the g_arm_opcodes and ↵Johnny Chen2011-02-042-2/+65
| | | | | | | | g_thumb_opcodes tables, to represent the supervisor call instruction (previosuly software interrupt). llvm-svn: 124840
* Add EmulateBLXImmediate() and EmulateBLXRm() to the g_arm_opcodes and ↵Johnny Chen2011-02-022-4/+169
| | | | | | | | g_thumb_opcodes tables, which represent "bl <label>", "blx <label>", and "blx <Rm>" instructions. llvm-svn: 124710
* Remove the 'lldb_private::' namespace resolution operator.Johnny Chen2011-02-011-34/+34
| | | | llvm-svn: 124671
* Add EmulateVPOP() to the g_arm_opcodes and g_thumb_opcodes tables, which ↵Johnny Chen2011-02-012-5/+106
| | | | | | | | represents an operation to load multiple extension registers from the stack. llvm-svn: 124670
* Cleaned up the EmulateInstructionARM to have the evaluate instructionGreg Clayton2011-02-012-207/+294
| | | | | | callbacks use member functions. llvm-svn: 124636
* Made the EmulateInstruction class into a plug-in interface and moved theGreg Clayton2011-02-012-0/+1354
source files around into the places they need to go. llvm-svn: 124631
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