summaryrefslogtreecommitdiffstats
path: root/lldb/source/Plugins/Instruction
Commit message (Collapse)AuthorAgeFilesLines
...
* Add ARM encoding entries for "CMP (immediate)" and "CMP (register)" operations.Johnny Chen2011-02-222-20/+167
| | | | | | | Add ARM/Thumb encoding entries for "CMN (immediate)" and "CMN (register)" operations, with the EmulateCMNImm()/Reg() methods not implemented yet for now. llvm-svn: 126178
* Add emulation methods for "MVN (immediate)" and "MVN (register)".Johnny Chen2011-02-222-20/+106
| | | | llvm-svn: 126172
* Add emulation methods for "EOR (Immediate)", "EOR (register)",Johnny Chen2011-02-212-6/+322
| | | | | | "TEQ (immediate)", and "TEQ (register)" operations. llvm-svn: 126160
* Add emulation methods for "TST (immediate)" and "TST (register)".Johnny Chen2011-02-212-6/+151
| | | | | | | Plus modified EmulateANDImm/Reg to delegate to TSTImm/Reg for Thumb2 32-bit instructions when Rd == '1111' and setflags is true. llvm-svn: 126144
* Make the helper method ReadCoreReg(uint32_t reg, bool *success) more genericJohnny Chen2011-02-191-65/+97
| | | | | | | which now handles R0-R12, SP, LR, as well as PC. And refactored a lot of calls to ReadRegisterUnsigned() to now funnel through ReadCoreReg(), instead. llvm-svn: 126010
* Add code to emulate LDRB (register) Arm instruction.Caroline Tice2011-02-182-2/+163
| | | | llvm-svn: 125994
* Add emulation methods for "ORR (immediate)" and "ORR (register)".Johnny Chen2011-02-181-8/+200
| | | | | | | Add Encoding T3 of "MOV (register)" to EmulateMOVRdRm() method and fixed some bugs in EmulateMOVRdImm() and EmulateMOVRdRm() methods. llvm-svn: 125992
* Add code to emulate LDRB (literal) Arm instruction.Caroline Tice2011-02-181-0/+86
| | | | llvm-svn: 125975
* Add emulation methods for "ADC (immediate)" and "ADC (register)".Johnny Chen2011-02-182-74/+207
| | | | | | | Plus add a helper method ReadCoreReg(uint32_t regnum, bool *success) to simplify coding a bit. llvm-svn: 125961
* Add code to emulate LDRB (immediate, Thumb) instruction.Caroline Tice2011-02-181-0/+141
| | | | llvm-svn: 125959
* Add emulation methods for "AND (immediate)" and "AND (register)".Johnny Chen2011-02-182-16/+225
| | | | | | Plus add macro definitions for APSR_C and APSR_V to simplify code. llvm-svn: 125947
* Add code to emulate LDR (register) Arm instruction.Caroline Tice2011-02-181-9/+224
| | | | llvm-svn: 125945
* Fix typo.Johnny Chen2011-02-181-1/+1
| | | | llvm-svn: 125812
* Add emulation of Encoding A1 "A8.6.6 ADD (register)" and "A8.6.5 ADD ↵Johnny Chen2011-02-182-11/+91
| | | | | | (immediate, ARM)". llvm-svn: 125809
* Add code to emulate LDR (immediate,ARM) instruction.Caroline Tice2011-02-181-0/+141
| | | | llvm-svn: 125808
* Finished renamings to make the emulation method names consistent case-wise.Johnny Chen2011-02-182-19/+19
| | | | llvm-svn: 125801
* Some renamings to make the emulation method names consistent case-wise.Johnny Chen2011-02-182-50/+50
| | | | llvm-svn: 125800
* Removed redundant entry EmulateTBB() (there's an existing one EmulateTB()) ↵Johnny Chen2011-02-171-8/+4
| | | | | | | | and fixed some typos in section headings. llvm-svn: 125796
* Fix a bug in EmulateTB() (TBB, TBH) where the branch length should be "twice"Johnny Chen2011-02-171-1/+1
| | | | | | the value of the byte/halfword returned from the table. llvm-svn: 125793
* Add header declarations for the remaining instructions we need toCaroline Tice2011-02-171-0/+203
| | | | | | emulate, to cover those that can change the PC. llvm-svn: 125791
* Refactoring. Abstracted the set flags operation into its own helper methodJohnny Chen2011-02-172-64/+71
| | | | | | | WriteFlags() and renamed WriteCoreRegisterWithFlags() to WriteCoreRegOptionalFlags(). Modified the call sites to use the helper methods. llvm-svn: 125788
* A8.6.6 ADD (register)Johnny Chen2011-02-172-8/+34
| | | | | | | Renamed EmulateAddRdnRm() to EmulateAddReg(), and added Encoding T1 to it. Where Encoding T2 can potentially modify the PC, causing a brnach. llvm-svn: 125782
* Add EmulateTB() method to emulate "Table Branch Byte" and "Table Branch ↵Johnny Chen2011-02-172-0/+89
| | | | | | | | Halfword" operations for Thumb2. llvm-svn: 125767
* Add stubs for pseudocode functions "MemA[]" amd "MemU[]", corresponding to ↵Caroline Tice2011-02-172-34/+103
| | | | | | | | | | | | | | aligned and unaligned memory accesses. The new stub functions are MemARead, MemAWrite, MemURead, and MemUWrite. At the moment these stubs just call ReadMemoryUnsigned or WriteMemoryUnsigned, but we can fill them out further later if we decide we need more accurate emulation of the memory system. Replaced all the direct calls to ReadMemoryUnsigned and WriteMemoryUnsigned in EmulateInstructionARM.cpp with calls to the appropriate new stub function. llvm-svn: 125766
* Move Align(val, alignment) utility function to ARMUtils.h.Johnny Chen2011-02-171-5/+0
| | | | llvm-svn: 125753
* Add comment for the helper method WriteCoreRegisterWithFlags().Johnny Chen2011-02-171-0/+3
| | | | llvm-svn: 125703
* Refactoring. Wrap the following pseudocode from the ARM Architecture ↵Johnny Chen2011-02-172-117/+90
| | | | | | | | | | | | | | | | | | | | | Reference Manul: // if d == 15 then // Can only occur for encoding A1 // ALUWritePC(result); // setflags is always FALSE here // else // R[d] = result; // if setflags then // APSR.N = result<31>; // APSR.Z = IsZeroBit(result); // APSR.C = carry; // // APSR.V unchanged into a helper method WriteCoreRegisterWithFlags, and modified the existing methods to take advantage of it. Plus add two emulation methods (declaration only for now) for ORR (immediate) and ORR (register). llvm-svn: 125701
* Add emulation methods for ROR (immediate), ROR (register), and RRX.Johnny Chen2011-02-162-5/+126
| | | | | | | | | | Turns out that they can be funneled through the helper methods EmulateShiftImm()/ EmulateShiftReg() as well. Modify EmulateShiftImm() to handle SRType_ROR and SRType_RRX. And fix a typo in the impl of utility Shift_C() in ARMUtils.h. llvm-svn: 125689
* Add code to emulate STRB (Thumb) instruction.Caroline Tice2011-02-162-1/+147
| | | | llvm-svn: 125686
* Add encoding entries for LSL (immediate and register) and LSR (immediate and ↵Johnny Chen2011-02-161-1/+21
| | | | | | | | register) to ARM and Thumb opcode tables. llvm-svn: 125683
* Add tagging for EmulateLDRRtRnImm().Johnny Chen2011-02-161-0/+1
| | | | llvm-svn: 125671
* Minor comment change.Johnny Chen2011-02-161-2/+2
| | | | llvm-svn: 125634
* Add emulation methods for LSL (immediate), LSL (register), LSR (immediate), ↵Johnny Chen2011-02-162-21/+160
| | | | | | | | | | | and LSR (register). Create two helper methods EmulateShiftImm() and EmulateShiftReg() and have ASR, LSL, and LSR delegate to the helper methods which take an extra ARM_ShifterType parameter. The opcodes tables have not been updated yet to reflect these new entries. llvm-svn: 125633
* Add documentation tags for LDM/STM instruction families.Caroline Tice2011-02-162-2/+211
| | | | | | Add code to emulate STR (register) Arm instruction. llvm-svn: 125623
* Section heading for EmulateB().Johnny Chen2011-02-161-1/+1
| | | | llvm-svn: 125620
* Add section headings corresponding to some of the ARM/Thumb emulation ↵Johnny Chen2011-02-161-5/+28
| | | | | | methods for better documentation. llvm-svn: 125618
* A8.6.14 ASR (register)Johnny Chen2011-02-152-3/+109
| | | | | | Add EmulateASRReg() Encodings T1, T2, and A1 to the opcodes tables. llvm-svn: 125614
* Add eContextRegisterLoad instruction emulation context.Caroline Tice2011-02-152-2/+170
| | | | | | Add code to emulate STR (Immediate, Thumb) instruction. llvm-svn: 125610
* Made lldb_private::ArchSpec contain much more than just an architecture. ItGreg Clayton2011-02-152-31/+16
| | | | | | | | | | now, in addition to cpu type/subtype and architecture flavor, contains: - byte order (big endian, little endian) - address size in bytes - llvm::Triple for true target triple support and for more powerful plug-in selection. llvm-svn: 125602
* Remove the "Register &reg" parameter from the BXWritePC(), LoadWritePC(), ↵Johnny Chen2011-02-152-35/+25
| | | | | | | | | and ALUWritePC() methods of EmulateInstructionARM class. The context data structure should provide sufficient information already. llvm-svn: 125596
* Fix wrong mask and encoding for T2 of ASR (immediate).Johnny Chen2011-02-151-1/+1
| | | | llvm-svn: 125593
* A8.6.14 ASR (immediate)Johnny Chen2011-02-152-0/+112
| | | | | | Add EmulateASRImm() Encodings T1, T2, and A1 to the opcodes tables. llvm-svn: 125592
* Add code to emulate STMIB Arm instruction.Caroline Tice2011-02-152-11/+145
| | | | llvm-svn: 125580
* Add code to emulate STMDB Arm instruction.Caroline Tice2011-02-152-2/+176
| | | | | | Add some bit-mask fixes to code for getting register bits for various LDM and STM instructions. llvm-svn: 125578
* Remove the unnecessary assignment of m_inst_cpsr inside EvaluateInstruction(),Johnny Chen2011-02-151-4/+0
| | | | | | because it's already been done within ReadInstruction(). llvm-svn: 125569
* Add code to emulate the STMDA Arm instruction.Caroline Tice2011-02-152-1/+134
| | | | llvm-svn: 125542
* Add missing logic (if BadReg(d) then UNPREDICTABLE;) for Encoding T2 of ↵Johnny Chen2011-02-141-0/+2
| | | | | | EmulateMovRdImm(). llvm-svn: 125533
* Fix build warning (unused variable).Johnny Chen2011-02-141-4/+0
| | | | llvm-svn: 125531
* - Rearrange instruction emulation contexts to use a union for theCaroline Tice2011-02-142-203/+238
| | | | | | | | | | | | | | | various types and numbers of arguments rather than trying to keep a constant number of arguments for all the types. - Also create a Register type within the instructions, to hold register type and number. - Modify EmulateInstructionArm.cpp to use the new register and context types in all the instruction emulation functions. - Add code to emulate the STM Arm instruction. llvm-svn: 125528
* Add entries for EmulateMovRdImm() -- "MOV (immediate)" -- Encodings T1 & T2 ↵Johnny Chen2011-02-142-5/+101
| | | | | | | | | | into g_thumb_opcodes table. Modify EmulateInstructionARM::EvaluateInstruction() so that if the cpsr has changed during evaluate instruction, we flush out the change into m_inst_cpsr in preparation for the next instruction. llvm-svn: 125524
OpenPOWER on IntegriCloud