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* Fill in EmulateSTRBImmARM to emulate the STRB (immediate, ARM) instruction.Caroline Tice2011-03-301-8/+83
| | | | llvm-svn: 128527
* Fill in EmulateSTREX to emulate the STREX ARM instruction.Caroline Tice2011-03-301-1/+94
| | | | llvm-svn: 128525
* Fill in code in EmulateSUBReg to emulate the SUB (register) ARM instruction.Caroline Tice2011-03-291-2/+111
| | | | llvm-svn: 128508
* Fill in code in EmulateADDRegShift, to emulate the ADDCaroline Tice2011-03-292-3/+83
| | | | | | (register-shifted register) ARM instruction. llvm-svn: 128500
* Add subtraction context.Caroline Tice2011-03-292-65/+887
| | | | | | | | Add code to emulate SUB (SP minus register) ARM instruction. Add stubs for other ARM emulation functions that need to be written. llvm-svn: 128491
* Add missing encodings for EmulateMOVRdImm (MOV register) function.Caroline Tice2011-03-291-15/+63
| | | | llvm-svn: 128479
* Fix single quote characters throughout the ARM emulation stuff.Caroline Tice2011-03-281-274/+281
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix bugs in various ARM istruction emulation functions: EmulateVPUSH - Fix context. - Fix bug calculating register numbers. EmulateVPOP - Fix context. - Fix bug calculating register numbers. EmulateShiftIMM - Fix bug in assert statement. EmulateLDMDA - Fix context. EmulateLDMDB - Fix context. EmulateLDMIB - Fix context. EmulateSTM - Fix bug calculating lowest_set_bit. EmulateSTMDA - Fix context. - Fix bug calculating lowest_set_bit. EmulateSTMDB - Fix context. - Fix bug calculating lowest_set_bit. EmulateSTMIB - FIx context EmulateLDRSBImmed - Fix test to match correction in corrected manual llvm-svn: 128409
* Made the lldb_private::Opcode struct into a real boy... I mean class.Greg Clayton2011-03-242-633/+351
| | | | | | | | | | | Modified the Disassembler::Instruction base class to contain an Opcode instance so that we can know the bytes for an instruction without needing to keep the data around. Modified the DisassemblerLLVM's instruction class to correctly extract the opcode bytes if all goes well. llvm-svn: 128248
* Fixed the LLDB build so that we can have private types, private enums andGreg Clayton2011-03-242-54/+54
| | | | | | | | public types and public enums. This was done to keep the SWIG stuff from parsing all sorts of enums and types that weren't needed, and allows us to abstract our API better. llvm-svn: 128239
* Add missing encodings for EmulateLDRRtRnImm (ARM insn emulation funciton).Caroline Tice2011-03-241-22/+82
| | | | llvm-svn: 128229
* More fixes for ARM instruction emulation code:Caroline Tice2011-03-221-13/+36
| | | | | | | | - Remove duplicate write from EmulateLDRRtPCRelative. - Add a missing encoding to EmulateADDSPImm. - Fix minor problems in Thumb instruction tables. llvm-svn: 128115
* Split all of the core of LLDB.framework/lldb.so into aGreg Clayton2011-03-201-2/+2
| | | | | | | | | | | | | | | | | | | | static archive that can be linked against. LLDB.framework/lldb.so exports a very controlled API. Splitting the API into a static library allows other tools (debugserver for now) to use the power of the LLDB debugger core, yet not export it as its API is not portable or maintainable. The Host layer and many of the other internal only APIs can now be statically linked against. Now LLDB.framework/lldb.so links against "liblldb-core.a" instead of compiling the .o files only for the shared library. This fix is only for compiling with Xcode as the Makefile based build already does this. The Xcode projecdt compiler has been changed to LLVM. Anyone using Xcode 3 will need to manually change the compiler back to GCC 4.2, or update to Xcode 4. llvm-svn: 127963
* Fix various small problems with EmulateInstructionARM::EmulateSTRRtSP.Caroline Tice2011-03-181-14/+39
| | | | llvm-svn: 127898
* Make all the codee that attempts to read the PC consistently useCaroline Tice2011-03-171-18/+17
| | | | | | | | | ReadCoreReg (which 'does the right thing', adding to pc when needed); fixed places in code where extra addition was being passed along. Fix bug in insn tables. llvm-svn: 127838
* Add code to emulate STRH (Register) Arm instruction.Caroline Tice2011-03-162-4/+197
| | | | | | | | Remove inaccurate comments from EmulateInstruction::Context definition. Fix contexts in a few arm instruction emulation routines. llvm-svn: 127770
* Fix various small bugs found in the instruction emulation functions.Caroline Tice2011-03-161-6/+10
| | | | llvm-svn: 127712
* LLDB now has "Platform" plug-ins. Platform plug-ins are plug-ins that provideGreg Clayton2011-03-081-19/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | an interface to a local or remote debugging platform. By default each host OS that supports LLDB should be registering a "default" platform that will be used unless a new platform is selected. Platforms are responsible for things such as: - getting process information by name or by processs ID - finding platform files. This is useful for remote debugging where there is an SDK with files that might already or need to be cached for debug access. - getting a list of platform supported architectures in the exact order they should be selected. This helps the native x86 platform on MacOSX select the correct x86_64/i386 slice from universal binaries. - Connect to remote platforms for remote debugging - Resolving an executable including finding an executable inside platform specific bundles (macosx uses .app bundles that contain files) and also selecting the appropriate slice of universal files for a given platform. So by default there is always a local platform, but remote platforms can be connected to. I will soon be adding a new "platform" command that will support the following commands: (lldb) platform connect --name machine1 macosx connect://host:port Connected to "machine1" platform. (lldb) platform disconnect macosx This allows LLDB to be well setup to do remote debugging and also once connected process listing and finding for things like: (lldb) process attach --name x<TAB> The currently selected platform plug-in can now auto complete any available processes that start with "x". The responsibilities for the platform plug-in will soon grow and expand. llvm-svn: 127286
* Add code to emulate RFE Arm instruction.Caroline Tice2011-03-032-2/+241
| | | | | | | | | Add new instruction context for RFE instruction. Add several new helper functions to help emulate RFE instruction (including CurrentModeIsPrivileged, BadMode, and CPSRWriteByInstr). llvm-svn: 126965
* Add code to emulate UXTH Arm instruction.Caroline Tice2011-03-031-2/+87
| | | | llvm-svn: 126954
* Add code to emulate UXTB Arm instruction.Caroline Tice2011-03-031-6/+92
| | | | llvm-svn: 126953
* Add code to emulate SXTH Arm instruction.Caroline Tice2011-03-031-5/+93
| | | | llvm-svn: 126951
* Add code to emulate SXTB Arm instruction.Caroline Tice2011-03-031-4/+101
| | | | llvm-svn: 126949
* Fix bug where bitwise-AND was being used and it should have been bitwise-OR.Caroline Tice2011-03-031-5/+5
| | | | llvm-svn: 126904
* Add code to emulate ADD (immediate, Thumb) Arm instruction.Caroline Tice2011-03-022-0/+125
| | | | | | Add addition context to EmulateInstruction contexts. llvm-svn: 126903
* Add code to emulate MUL Arm instruction.Caroline Tice2011-03-021-0/+140
| | | | | | Add new context type & info structure for mul instruction. llvm-svn: 126891
* Add code to emulate LDRSH (register) Arm instruction.Caroline Tice2011-03-021-1/+184
| | | | llvm-svn: 126881
* Add code to emulate LDRSH (literal) Arm instruction.Caroline Tice2011-03-021-0/+108
| | | | llvm-svn: 126866
* Add code to emulate LDRSH (immediate) Arm instruction.Caroline Tice2011-03-021-0/+167
| | | | llvm-svn: 126807
* Add code to emulate LDRSB (register) Arm instruction.Caroline Tice2011-03-011-0/+162
| | | | llvm-svn: 126802
* Add code to emulate LDRSB (literal) Arm instruction.Caroline Tice2011-03-011-0/+95
| | | | llvm-svn: 126789
* Add code to emulate LDRSB (immediate) Arm instruction.Caroline Tice2011-03-011-0/+153
| | | | llvm-svn: 126783
* Add code to emulate LDRH (register) Arm instruction.Caroline Tice2011-03-011-2/+181
| | | | llvm-svn: 126758
* Add code to emulate LDRH (literal) Arm instruction.Caroline Tice2011-02-281-0/+113
| | | | llvm-svn: 126709
* Add code to emulate LDRH (immediate, Thumb) arm instruction.Caroline Tice2011-02-282-2/+158
| | | | llvm-svn: 126692
* Add emulation for Encoding A1 of A8.6.97 MOV (register).Johnny Chen2011-02-251-0/+11
| | | | llvm-svn: 126456
* Fix typos in the opcode entries for branch instructions.Johnny Chen2011-02-241-3/+3
| | | | llvm-svn: 126442
* Add emulation for BXJ (Branch and Exchange Jazelle), assuming that the ↵Johnny Chen2011-02-242-1/+71
| | | | | | | | attempt to switch to Jazelle state fails, thus treating BXJ as a BX operation. llvm-svn: 126423
* Add emulation methods for Bitwise Bit Clear (immediate and register) operations.Johnny Chen2011-02-242-4/+178
| | | | llvm-svn: 126355
* Add emulation methods for "SUB (immediate, Thumb)" and "SUB (immediate, ↵Johnny Chen2011-02-232-4/+181
| | | | | | ARM)" operations. llvm-svn: 126343
* Add emulation for "ADR" operations. Add a ThumbImm8Scaled() convenience ↵Johnny Chen2011-02-232-5/+103
| | | | | | | | function and rename the original ThumbImmScaled() function to ThumbImm7Scaled(). llvm-svn: 126335
* Modify EmulateSUBSPImm() to handle the cases with generic Rd value instead ofJohnny Chen2011-02-232-15/+41
| | | | | | Rd == 13. Add opcode entries for the generic "sub (sp minus immediate)" operations. llvm-svn: 126293
* Add emulation methods for "SBC (immediate)" and "SBC (register)" operations.Johnny Chen2011-02-232-4/+170
| | | | llvm-svn: 126283
* Abtracted all mach-o and ELF out of ArchSpec. This patch is a modified formGreg Clayton2011-02-231-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | of Stephen Wilson's idea (thanks for the input Stephen!). What I ended up doing was: - Got rid of ArchSpec::CPU (which was a generic CPU enumeration that mimics the contents of llvm::Triple::ArchType). We now rely upon the llvm::Triple to give us the machine type from llvm::Triple::ArchType. - There is a new ArchSpec::Core definition which further qualifies the CPU core we are dealing with into a single enumeration. If you need support for a new Core and want to debug it in LLDB, it must be added to this list. In the future we can allow for dynamic core registration, but for now it is hard coded. - The ArchSpec can now be initialized with a llvm::Triple or with a C string that represents the triple (it can just be an arch still like "i386"). - The ArchSpec can still initialize itself with a architecture type -- mach-o with cpu type and subtype, or ELF with e_machine + e_flags -- and this will then get translated into the internal llvm::Triple::ArchSpec + ArchSpec::Core. The mach-o cpu type and subtype can be accessed using the getter functions: uint32_t ArchSpec::GetMachOCPUType () const; uint32_t ArchSpec::GetMachOCPUSubType () const; But these functions are just converting out internal llvm::Triple::ArchSpec + ArchSpec::Core back into mach-o. Same goes for ELF. All code has been updated to deal with the changes. This should abstract us until later when the llvm::TargetSpec stuff gets finalized and we can then adopt it. llvm-svn: 126278
* Renamed macro definition of CPSR_C to be CPSR_C_POS to avoid confusions and ↵Johnny Chen2011-02-231-6/+6
| | | | | | subtle bugs. llvm-svn: 126271
* Add emulation methods for "RSC (immediate)" and "RSC (register)" operations.Johnny Chen2011-02-232-7/+144
| | | | llvm-svn: 126267
* Add emulation methods for "RSB (immediate)" and "RSB (register)".Johnny Chen2011-02-222-3/+181
| | | | | | Plus add missing break stmts for "case" blocks. llvm-svn: 126265
* Add two convenience functions: DecodeImmShiftThumb() and DecodeImmShiftARM() ↵Johnny Chen2011-02-221-20/+20
| | | | | | | | to ARMUtils.h. Use them within EmulateInstructionARM.cpp to save repetitive typing. llvm-svn: 126247
* Add "cmp<c>.w <Rn>, #<const>" emulation to EmulateCMPImm() method,Johnny Chen2011-02-221-12/+18
| | | | | | and implement EmulateCMNImm() and EMulateCMNReg() methods. llvm-svn: 126236
* Fix the 'variants' field of "CMN (immediate)" Encoding T1 entry, it should ↵Johnny Chen2011-02-221-1/+1
| | | | | | be ARMV6T2_ABOVE, not ARMvAll. llvm-svn: 126234
* Add ARM encoding entries for "CMN (immediate)" and "CMN (register)" operations.Johnny Chen2011-02-221-0/+4
| | | | llvm-svn: 126179
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