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* Fix arm instruction emulation of add (imm) and sub (imm)Tamas Berghammer2015-05-131-35/+48
| | | | | | Differential revision: http://reviews.llvm.org/D9704 llvm-svn: 237240
* Fixed a ton of gcc compile warningsVince Harron2015-05-131-1/+1
| | | | | | | | | | Removed some unused variables, added some consts, changed some casts to const_cast. I don't think any of these changes are very controversial. Differential Revision: http://reviews.llvm.org/D9674 llvm-svn: 237218
* Fix thumb condition extraction in ARM instrcution emulatorTamas Berghammer2015-05-111-2/+2
| | | | llvm-svn: 236988
* Fix condition detection in EmulateInstructionARMTamas Berghammer2015-04-241-2/+1
| | | | | | | | | | | | | The condition detection code is calculating the result of the condition based on the first 3 bit of the condition and then negate it if the LSB of the condition is set. It works for the normal conditions but 0b1110 and 0b1111 are special as both of them should evaluate to true independently the value of CPSR. This CL removes the negating logic from those cases. Differential revision: http://reviews.llvm.org/D9219 llvm-svn: 235715
* Fix order of b and blx instrction in EmulateInstructionARMTamas Berghammer2015-04-241-2/+2
| | | | | | | | | | In the previous ordering some "blx <label>" instruction was recognised as "b #imm24" instructions causing a failure in the instruction emulator. Differential revision: http://reviews.llvm.org/D9218 llvm-svn: 235714
* Fix write register context for arm "add<c> <Rd>, sp, #imm"Tamas Berghammer2015-04-241-1/+5
| | | | | | Differential revision: http://reviews.llvm.org/D9213 llvm-svn: 235713
* Update cpsr register in BLX instruction emulationTamas Berghammer2015-04-231-0/+7
| | | | | | | | | Write the new cpsr value into the cpsr register if the BL or the BLX instruction change the instruction set on arm. Differential revision: http://reviews.llvm.org/D9188 llvm-svn: 235585
* UnwindPlan::Row refactor -- add support for CFA set by a DWARF expressionPavel Labath2015-02-231-1/+1
| | | | | | | | | | | | | | | | | | | Summary: This change refactors UnwindPlan::Row to be able to store the fact that the CFA is value is set by evaluating a dwarf expression (DW_CFA_def_cfa_expression). This is achieved by creating a new class CFAValue and moving all CFA setting/getting code there. Note that code using the new CFAValue::isDWARFExpression is not yet present and will be added in a follow-up patch. Therefore, this patch should not change the functionality in any way. Test Plan: Ran tests on Mac and Linux. No regressions detected. Reviewers: jasonmolenda, clayborg Subscribers: lldb-commits Differential Revision: http://reviews.llvm.org/D7755 llvm-svn: 230210
* Add #if 0 around unreachable block of code to suppress warnings.Jason Molenda2014-10-171-0/+2
| | | | | | clang warnings. llvm-svn: 220025
* Replace uint32_t by lldb::RegisterKing in register context API.Jean-Daniel Dupas2014-07-022-4/+6
| | | | llvm-svn: 212172
* lldb: remove adhoc implementation of array_sizeofSaleem Abdulrasool2014-06-271-2/+3
| | | | | | | | Replace adhoc inline implementation of llvm::array_lengthof in favour of the implementation in LLVM. This is simply a cleanup change, no functional change intended. llvm-svn: 211868
* Fix a few typos.Bruce Mitchener2014-06-271-9/+9
| | | | llvm-svn: 211851
* Update the checks in EmulateInstructionARM::GetFramePointerRegisterNumber Jason Molenda2014-01-061-12/+40
| | | | | | | | | | and EmulateInstructionARM::GetFramePointerDWARFRegisterNumber to recognize the Apple arm convention (of using r7 for the frame pointer, regardless of thumb or arm) even if the OS does not match Darwin/MacOSX/iOS. Also corrects the behavior for thumb code on non-Apple platforms. <rdar://problem/14661537> llvm-svn: 198648
* Handle endianness in the Opcode classEd Maste2013-12-091-6/+6
| | | | | | | | | Previously, an opcode set via SetOpcode32 (for example) was later extracted via GetData() as a byte sequence in host order rather than target order. Review: http://llvm-reviews.chandlerc.com/D1838 llvm-svn: 196808
* Fix header comment line lengthEd Maste2013-11-111-1/+1
| | | | llvm-svn: 194397
* Roll back the changes I made in r193907 which created a new FrameJason Molenda2013-11-042-3/+3
| | | | | | | | | | pure virtual base class and made StackFrame a subclass of that. As I started to build on top of that arrangement today, I found that it wasn't working out like I intended. Instead I'll try sticking with the single StackFrame class -- there's too much code duplication to make a more complicated class hierarchy sensible I think. llvm-svn: 193983
* Add a new base class, Frame. It is a pure virtual function whichJason Molenda2013-11-022-3/+3
| | | | | | | | | | | | | | | | | | | | | defines a protocol that all subclasses will implement. StackFrame is currently the only subclass and the methods that Frame vends are nearly identical to StackFrame's old methods. Update all callers to use Frame*/Frame& instead of pointers to StackFrames. This is almost entirely a mechanical change that touches a lot of the code base so I'm committing it alone. No new functionality is added with this patch, no new subclasses of Frame exist yet. I'll probably need to tweak some of the separation, possibly moving some of StackFrame's methods up in to Frame, but this is a good starting point. <rdar://problem/15314068> llvm-svn: 193907
* Correct typo: Intructions -> InstructionsEd Maste2013-10-042-4/+4
| | | | llvm-svn: 191972
* Convert to UNIX line endings.Joerg Sonnenberger2013-09-251-6/+6
| | | | llvm-svn: 191367
* Rename EmulationStateARM::sd_regs to avoid name clash (MSVC).Virgile Bello2013-08-271-1/+1
| | | | llvm-svn: 189366
* Fixed the instruction emulation so that it doesn'tSean Callanan2013-06-251-0/+6
| | | | | | | | | print to standard output as part of normal operation. <rdar://problem/14247606> llvm-svn: 184797
* Fix some more mismatched integer types causing compiler warnings.Andy Gibbs2013-06-242-14/+14
| | | | llvm-svn: 184737
* Update countTrailingZeros function usage to match llvm's r182667.Filipe Cabecinhas2013-05-241-2/+2
| | | | llvm-svn: 182683
* <rdar://problem/13854277>Greg Clayton2013-05-102-10/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | <rdar://problem/13594769> Main changes in this patch include: - cleanup plug-in interface and use ConstStrings for plug-in names - Modfiied the BSD Archive plug-in to be able to pick out the correct .o file when .a files contain multiple .o files with the same name by using the timestamp - Modified SymbolFileDWARFDebugMap to properly verify the timestamp on .o files it loads to ensure we don't load updated .o files and cause problems when debugging The plug-in interface changes: Modified the lldb_private::PluginInterface class that all plug-ins inherit from: Changed: virtual const char * GetPluginName() = 0; To: virtual ConstString GetPluginName() = 0; Removed: virtual const char * GetShortPluginName() = 0; - Fixed up all plug-in to adhere to the new interface and to return lldb_private::ConstString values for the plug-in names. - Fixed all plug-ins to return simple names with no prefixes. Some plug-ins had prefixes and most ones didn't, so now they all don't have prefixed names, just simple names like "linux", "gdb-remote", etc. llvm-svn: 181631
* After discussing with Chris Lattner, we require C++11, so lets get rid of ↵Greg Clayton2013-04-181-2/+2
| | | | | | the macros and just use C++11. llvm-svn: 179805
* Since we use C++11, we should switch over to using std::unique_ptr when ↵Greg Clayton2013-04-181-2/+2
| | | | | | | | C++11 is being used. To do this, we follow what we have done for shared pointers and we define a STD_UNIQUE_PTR macro that can be used and it will "do the right thing". Due to some API differences in std::unique_ptr and due to the fact that we need to be able to compile without C++11, we can't use move semantics so some code needed to change so that it can compile with either C++. Anyone wanting to use a unique_ptr or auto_ptr should now use the "STD_UNIQUE_PTR(TYPE)" macro. llvm-svn: 179779
* Adding CMake build system to LLDB. Some known issues remain:Daniel Malea2013-02-211-0/+6
| | | | | | | | | | | | | | - generate-vers.pl has to be called by cmake to generate the version number - parallel builds not yet supported; dependency on clang must be explicitly specified Tested on Linux. - Building on Mac will require code-signing logic to be implemented. - Building on Windows will require OS-detection logic and some selective directory inclusion Thanks to Carlo Kok (who originally prepared these CMakefiles for Windows) and Ben Langmuir who ported them to Linux! llvm-svn: 175795
* More Linux warnings fixes (remove default labels as needed):Daniel Malea2012-12-072-4/+0
| | | | | | | | - as per http://llvm.org/docs/CodingStandards.html#don-t-use-default-labels-in-fully-covered-switches-over-enumerations Patch by Matt Kopec! llvm-svn: 169633
* Fix the bit pattern for vst1 in ↵Jason Molenda2012-10-311-1/+1
| | | | | | | | EmulateInstructionARM::GetThumbOpcodeForInstruction so it is recognized correctly. The second patch needed for <rdar://problem/10652166>. llvm-svn: 167094
* Add a new capability to RegisterContextLLDB: To recognize when theJason Molenda2012-10-261-4/+2
| | | | | | | | | | | | | | | | | | | | | | | | | Full UnwindPlan is trying to do an impossible unwind; in that case invalidate the Full UnwindPlan and replace it with the architecture default unwind plan. This is a scenario that happens occasionally with arm unwinds in particular; the instruction analysis based full unwindplan can mis-parse the functions and the stack walk stops prematurely. Now we can do a simpleminded frame-chain walk to find the caller frame and continue the unwind. It's not ideal but given the complicated nature of analyzing the arm functions, and the lack of eh_frame information on iOS, it is a distinct improvement and fixes some long-standing problems with the unwinder on that platform. This is fixing <rdar://problem/12091421>. I may re-use this invalidate feature in the future if I can identify other cases where the full unwindplan's unwind information is clearly incorrect. This checkin also includes some cleanup for the volatile register definition in the arm ABI plugin for <rdar://problem/10652166> although work remains to be done for that bug. llvm-svn: 166757
* Reimplemented the code that backed the "settings" in lldb. There were many ↵Greg Clayton2012-08-224-2/+4
| | | | | | | | | | | | | issues with the previous implementation: - no setting auto completion - very manual and error prone way of getting/setting variables - tons of code duplication - useless instance names for processes, threads Now settings can easily be defined like option values. The new settings makes use of the "OptionValue" classes so we can re-use the option value code that we use to set settings in command options. No more instances, just "does the right thing". llvm-svn: 162366
* Ran the static analyzer on the codebase and found a few things.Greg Clayton2012-07-171-4/+20
| | | | llvm-svn: 160338
* Switch nearly all of the use of the UnwindPlan::Row's to go throughJason Molenda2012-07-141-3/+3
| | | | | | | | | | | | | | a shared pointer to ease some memory management issues with a patch I'm working on. The main complication with using SPs for these objects is that most methods that build up an UnwindPlan will construct a Row to a given instruction point in a function, then add additional regsaves in the next instruction point to that row and push it again. A little care is needed to not mutate the previous instruction point's Row once these are switched to being held behing shared pointers. llvm-svn: 160214
* <rdar://problem/11358639>Greg Clayton2012-05-081-8/+26
| | | | | | | | Switch over to the "*-apple-macosx" for desktop and "*-apple-ios" for iOS triples. Also make the selection process for auto selecting platforms based off of an arch much better. llvm-svn: 156354
* Make sure EmulateInstructionARM doesn't have to have "armv4", "armv6", ↵Greg Clayton2012-04-181-4/+4
| | | | | | "armv7" as the exact architecture name, the arch name can just start with any of these strings. We need to be able to recognize different variants that might come along and not fail to backtrace completely (which happens when we aren't able to find an architecture that matches) when we don't have exact matches. llvm-svn: 155045
* Add armv7s to recognized cpu type for arm instruction emulation.Jason Molenda2012-04-181-8/+10
| | | | llvm-svn: 154974
* rdar://problem/11031743Johnny Chen2012-03-131-1/+1
| | | | | | | | | | | | For EmulateInstructionARM::EmulatePUSH(), fix the logical branch for when pc is pushed to behave like the other cases where: context.SetRegisterToRegisterPlusOffset (reg_info, sp_reg, addr - sp); is called to inform of the operation to set a register value to a memory location calculated from a base register plus an offset. llvm-svn: 152670
* Fixed some warnings after enabling some stricter warnings in the Xcode projectGreg Clayton2011-10-311-2/+2
| | | | | | | | | settings. Also fixed an issue where we weren't creating anonymous namepaces correctly: <rdar://problem/10371295> llvm-svn: 143403
* Fix two logic errors uncovered by the static analyzer.Johnny Chen2011-08-161-3/+3
| | | | | | | | | For the default case (illegal encoding type), just return false instead of break. A8.6.84 LDRSH (register) A8.6.309 VLD1 (single element to all lanes) llvm-svn: 137699
* Fix a logic error (Division by zero) uncovered by the static analyzer.Johnny Chen2011-08-121-1/+1
| | | | | | | A8.6.391 VST1 (multiple single elements) alignment = if align == '00' then 1 else 4 << UInt(align); llvm-svn: 137477
* Fix some warnings from static analyzer.Johnny Chen2011-08-121-5/+5
| | | | | | The initialization of 'replicated_element' to 0 is needed, otherwise we get a garbage value to start with. llvm-svn: 137405
* Fixed some issues with ARM backtraces by not processing any push/pop Greg Clayton2011-07-062-38/+75
| | | | | | | | | | | | | | instructions if they are conditional. Also fixed issues where the PC wasn't getting bit zero stripped for ARM targets when a stack frame was thumb. We now properly call through the GetOpcodeLoadAddress() functions to make sure the addresses are properly stripped for any targets that may decorate up their addresses. We now don't pass the SIGSTOP signals along. We can revisit this soon, but currently this was interfering with debugging some older ARM targets that don't have vCont support in the GDB server. llvm-svn: 134461
* Bail out if we have an invalid thumb instruction.Johnny Chen2011-06-021-2/+4
| | | | llvm-svn: 132511
* Turn the commented-out assert()'s into appropriate bail-out actions.Johnny Chen2011-06-021-2/+5
| | | | llvm-svn: 132507
* When emulating an ill-formed instruction, we should bail out instead of ↵Johnny Chen2011-06-021-35/+100
| | | | | | asserting and bringing down the whole process. llvm-svn: 132506
* Remove asserts that will crash LLDB. These should be changed to returnGreg Clayton2011-06-021-14/+14
| | | | | | | true/false in an extra boolean parameter and not cause the the binary that us using the LLDB framework to crash. llvm-svn: 132501
* EmulateShiftReg() also accepts shifter type of SRType_ROR.Johnny Chen2011-06-021-1/+4
| | | | llvm-svn: 132484
* Fixed an issue in the EmulateInstructionARM there the IT opcode was trying toGreg Clayton2011-05-232-6/+51
| | | | | | | | | | | | | | | | | | | | | | | | parse NOP instructions. I added the new table entries for the NOP for the plain NOP, Yield, WFE, WFI, and SEV variants. Modified the opcode emulation function EmulateInstructionARM::EmulateMOVRdSP(...) to notify us when it is creating a frame. Also added an abtract way to detect the frame pointer register for both the standard ARM ABI and for Darwin. Fixed GDBRemoteRegisterContext::WriteAllRegisterValues(...) to correctly be able to individually write register values back if case the 'G' packet is not implemented or returns an error. Modified the StopInfoMachException to "trace" stop reasons. On ARM we currently use the BVR/BCR register pairs to say "stop when the PC is not equal to the current PC value", and this results in a EXC_BREAKPOINT mach exception that has 0x102 in the code. Modified debugserver to create the short option string from long option definitions to make sure it doesn't get out of date. The short option string was missing many of the newer short option values due to a modification of the long options defs, and not modifying the short option string. llvm-svn: 131911
* Added a way to resolve an load address from a target:Greg Clayton2011-05-181-1/+4
| | | | | | | | | | | | | | | | | | | | bool Address::SetLoadAddress (lldb::addr_t load_addr, Target *target); Added an == and != operator to RegisterValue. Modified the ThreadPlanTracer to use RegisterValue objects to store the register values when single stepping. Also modified the output to be a bit less wide. Fixed the ABIMacOSX_arm to not overwrite stuff on the stack. Also made the trivial function call be able to set the ARM/Thumbness of the target correctly, and also sets the return value ARM/Thumbness. Fixed the encoding on the arm s0-s31 and d16 - d31 registers when the default register set from a standard GDB server register sets. llvm-svn: 131517
* Moved all code from ArchDefaultUnwindPlan and ArchVolatileRegs into theirGreg Clayton2011-05-111-4/+3
| | | | | | | | | | | | | | | respective ABI plugins as they were plug-ins that supplied ABI specfic info. Also hookep up the UnwindAssemblyInstEmulation so that it can generate the unwind plans for ARM. Changed the way ABI plug-ins are handed out when you get an instance from the plug-in manager. They used to return pointers that would be mananged individually by each client that requested them, but now they are handed out as shared pointers since there is no state in the ABI objects, they can be shared. llvm-svn: 131193
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