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* Add code to emulate UXTB Arm instruction.Caroline Tice2011-03-031-6/+92
| | | | llvm-svn: 126953
* Add code to emulate SXTH Arm instruction.Caroline Tice2011-03-031-5/+93
| | | | llvm-svn: 126951
* Add code to emulate SXTB Arm instruction.Caroline Tice2011-03-031-4/+101
| | | | llvm-svn: 126949
* Fix bug where bitwise-AND was being used and it should have been bitwise-OR.Caroline Tice2011-03-031-5/+5
| | | | llvm-svn: 126904
* Add code to emulate ADD (immediate, Thumb) Arm instruction.Caroline Tice2011-03-022-0/+125
| | | | | | Add addition context to EmulateInstruction contexts. llvm-svn: 126903
* Add code to emulate MUL Arm instruction.Caroline Tice2011-03-021-0/+140
| | | | | | Add new context type & info structure for mul instruction. llvm-svn: 126891
* Add code to emulate LDRSH (register) Arm instruction.Caroline Tice2011-03-021-1/+184
| | | | llvm-svn: 126881
* Add code to emulate LDRSH (literal) Arm instruction.Caroline Tice2011-03-021-0/+108
| | | | llvm-svn: 126866
* Add code to emulate LDRSH (immediate) Arm instruction.Caroline Tice2011-03-021-0/+167
| | | | llvm-svn: 126807
* Add code to emulate LDRSB (register) Arm instruction.Caroline Tice2011-03-011-0/+162
| | | | llvm-svn: 126802
* Add code to emulate LDRSB (literal) Arm instruction.Caroline Tice2011-03-011-0/+95
| | | | llvm-svn: 126789
* Add code to emulate LDRSB (immediate) Arm instruction.Caroline Tice2011-03-011-0/+153
| | | | llvm-svn: 126783
* Add code to emulate LDRH (register) Arm instruction.Caroline Tice2011-03-011-2/+181
| | | | llvm-svn: 126758
* Add code to emulate LDRH (literal) Arm instruction.Caroline Tice2011-02-281-0/+113
| | | | llvm-svn: 126709
* Add code to emulate LDRH (immediate, Thumb) arm instruction.Caroline Tice2011-02-282-2/+158
| | | | llvm-svn: 126692
* Add emulation for Encoding A1 of A8.6.97 MOV (register).Johnny Chen2011-02-251-0/+11
| | | | llvm-svn: 126456
* Fix typos in the opcode entries for branch instructions.Johnny Chen2011-02-241-3/+3
| | | | llvm-svn: 126442
* Add emulation for BXJ (Branch and Exchange Jazelle), assuming that the ↵Johnny Chen2011-02-242-1/+71
| | | | | | | | attempt to switch to Jazelle state fails, thus treating BXJ as a BX operation. llvm-svn: 126423
* Add emulation methods for Bitwise Bit Clear (immediate and register) operations.Johnny Chen2011-02-242-4/+178
| | | | llvm-svn: 126355
* Add emulation methods for "SUB (immediate, Thumb)" and "SUB (immediate, ↵Johnny Chen2011-02-232-4/+181
| | | | | | ARM)" operations. llvm-svn: 126343
* Add emulation for "ADR" operations. Add a ThumbImm8Scaled() convenience ↵Johnny Chen2011-02-232-5/+103
| | | | | | | | function and rename the original ThumbImmScaled() function to ThumbImm7Scaled(). llvm-svn: 126335
* Modify EmulateSUBSPImm() to handle the cases with generic Rd value instead ofJohnny Chen2011-02-232-15/+41
| | | | | | Rd == 13. Add opcode entries for the generic "sub (sp minus immediate)" operations. llvm-svn: 126293
* Add emulation methods for "SBC (immediate)" and "SBC (register)" operations.Johnny Chen2011-02-232-4/+170
| | | | llvm-svn: 126283
* Abtracted all mach-o and ELF out of ArchSpec. This patch is a modified formGreg Clayton2011-02-231-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | of Stephen Wilson's idea (thanks for the input Stephen!). What I ended up doing was: - Got rid of ArchSpec::CPU (which was a generic CPU enumeration that mimics the contents of llvm::Triple::ArchType). We now rely upon the llvm::Triple to give us the machine type from llvm::Triple::ArchType. - There is a new ArchSpec::Core definition which further qualifies the CPU core we are dealing with into a single enumeration. If you need support for a new Core and want to debug it in LLDB, it must be added to this list. In the future we can allow for dynamic core registration, but for now it is hard coded. - The ArchSpec can now be initialized with a llvm::Triple or with a C string that represents the triple (it can just be an arch still like "i386"). - The ArchSpec can still initialize itself with a architecture type -- mach-o with cpu type and subtype, or ELF with e_machine + e_flags -- and this will then get translated into the internal llvm::Triple::ArchSpec + ArchSpec::Core. The mach-o cpu type and subtype can be accessed using the getter functions: uint32_t ArchSpec::GetMachOCPUType () const; uint32_t ArchSpec::GetMachOCPUSubType () const; But these functions are just converting out internal llvm::Triple::ArchSpec + ArchSpec::Core back into mach-o. Same goes for ELF. All code has been updated to deal with the changes. This should abstract us until later when the llvm::TargetSpec stuff gets finalized and we can then adopt it. llvm-svn: 126278
* Renamed macro definition of CPSR_C to be CPSR_C_POS to avoid confusions and ↵Johnny Chen2011-02-231-6/+6
| | | | | | subtle bugs. llvm-svn: 126271
* Add emulation methods for "RSC (immediate)" and "RSC (register)" operations.Johnny Chen2011-02-232-7/+144
| | | | llvm-svn: 126267
* Add emulation methods for "RSB (immediate)" and "RSB (register)".Johnny Chen2011-02-222-3/+181
| | | | | | Plus add missing break stmts for "case" blocks. llvm-svn: 126265
* Add two convenience functions: DecodeImmShiftThumb() and DecodeImmShiftARM() ↵Johnny Chen2011-02-221-20/+20
| | | | | | | | to ARMUtils.h. Use them within EmulateInstructionARM.cpp to save repetitive typing. llvm-svn: 126247
* Add "cmp<c>.w <Rn>, #<const>" emulation to EmulateCMPImm() method,Johnny Chen2011-02-221-12/+18
| | | | | | and implement EmulateCMNImm() and EMulateCMNReg() methods. llvm-svn: 126236
* Fix the 'variants' field of "CMN (immediate)" Encoding T1 entry, it should ↵Johnny Chen2011-02-221-1/+1
| | | | | | be ARMV6T2_ABOVE, not ARMvAll. llvm-svn: 126234
* Add ARM encoding entries for "CMN (immediate)" and "CMN (register)" operations.Johnny Chen2011-02-221-0/+4
| | | | llvm-svn: 126179
* Add ARM encoding entries for "CMP (immediate)" and "CMP (register)" operations.Johnny Chen2011-02-222-20/+167
| | | | | | | Add ARM/Thumb encoding entries for "CMN (immediate)" and "CMN (register)" operations, with the EmulateCMNImm()/Reg() methods not implemented yet for now. llvm-svn: 126178
* Add emulation methods for "MVN (immediate)" and "MVN (register)".Johnny Chen2011-02-222-20/+106
| | | | llvm-svn: 126172
* Add emulation methods for "EOR (Immediate)", "EOR (register)",Johnny Chen2011-02-212-6/+322
| | | | | | "TEQ (immediate)", and "TEQ (register)" operations. llvm-svn: 126160
* Add emulation methods for "TST (immediate)" and "TST (register)".Johnny Chen2011-02-212-6/+151
| | | | | | | Plus modified EmulateANDImm/Reg to delegate to TSTImm/Reg for Thumb2 32-bit instructions when Rd == '1111' and setflags is true. llvm-svn: 126144
* Make the helper method ReadCoreReg(uint32_t reg, bool *success) more genericJohnny Chen2011-02-191-65/+97
| | | | | | | which now handles R0-R12, SP, LR, as well as PC. And refactored a lot of calls to ReadRegisterUnsigned() to now funnel through ReadCoreReg(), instead. llvm-svn: 126010
* Add code to emulate LDRB (register) Arm instruction.Caroline Tice2011-02-182-2/+163
| | | | llvm-svn: 125994
* Add emulation methods for "ORR (immediate)" and "ORR (register)".Johnny Chen2011-02-181-8/+200
| | | | | | | Add Encoding T3 of "MOV (register)" to EmulateMOVRdRm() method and fixed some bugs in EmulateMOVRdImm() and EmulateMOVRdRm() methods. llvm-svn: 125992
* Add code to emulate LDRB (literal) Arm instruction.Caroline Tice2011-02-181-0/+86
| | | | llvm-svn: 125975
* Add emulation methods for "ADC (immediate)" and "ADC (register)".Johnny Chen2011-02-182-74/+207
| | | | | | | Plus add a helper method ReadCoreReg(uint32_t regnum, bool *success) to simplify coding a bit. llvm-svn: 125961
* Add code to emulate LDRB (immediate, Thumb) instruction.Caroline Tice2011-02-181-0/+141
| | | | llvm-svn: 125959
* Add emulation methods for "AND (immediate)" and "AND (register)".Johnny Chen2011-02-182-16/+225
| | | | | | Plus add macro definitions for APSR_C and APSR_V to simplify code. llvm-svn: 125947
* Add code to emulate LDR (register) Arm instruction.Caroline Tice2011-02-181-9/+224
| | | | llvm-svn: 125945
* Fix typo.Johnny Chen2011-02-181-1/+1
| | | | llvm-svn: 125812
* Add emulation of Encoding A1 "A8.6.6 ADD (register)" and "A8.6.5 ADD ↵Johnny Chen2011-02-182-11/+91
| | | | | | (immediate, ARM)". llvm-svn: 125809
* Add code to emulate LDR (immediate,ARM) instruction.Caroline Tice2011-02-181-0/+141
| | | | llvm-svn: 125808
* Finished renamings to make the emulation method names consistent case-wise.Johnny Chen2011-02-182-19/+19
| | | | llvm-svn: 125801
* Some renamings to make the emulation method names consistent case-wise.Johnny Chen2011-02-182-50/+50
| | | | llvm-svn: 125800
* Removed redundant entry EmulateTBB() (there's an existing one EmulateTB()) ↵Johnny Chen2011-02-171-8/+4
| | | | | | | | and fixed some typos in section headings. llvm-svn: 125796
* Fix a bug in EmulateTB() (TBB, TBH) where the branch length should be "twice"Johnny Chen2011-02-171-1/+1
| | | | | | the value of the byte/halfword returned from the table. llvm-svn: 125793
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