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* [MIPS] Fix PLT entries generation in case of linking regular and microMIPS codeSimon Atanasyan2017-10-021-18/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently LLD calls the `isMicroMips` routine to determine type of PLT entries needs to be generated: regular or microMIPS. This routine checks ELF header flags in the `FirstObj` to retrieve type of linked object files. So if the first file does not contain microMIPS code, LLD will generate PLT entries with regular (non-microMIPS) code only. Ideally, if a PLT entry is referenced by microMIPS code only this entry should contain microMIPS code, if a PLT entry is referenced by regular code this entry should contain regular code. In a "mixed" case the PLT entry can be either microMIPS or regular, but each "cross-mode-call" has additional cost. It's rather difficult to implement this ideal solution. But we can assume that if there is an input object file with microMIPS code, the most part of the code is microMIPS too. So we need to deduce type of PLT entries based on finally calculated ELF header flags and do not check only the first input object file. This change implements this. - The `getMipsEFlags` renamed to the `calcMipsEFlags`. The function called from the `LinkerDriver::link`. Result is stored in the Configuration::MipsEFlags field. - The `isMicroMips` and `isMipsR6` routines access the `MipsEFlags` field to get and check calculated ELF flags. - New types of PLT records created when necessary. Differential revision: https://reviews.llvm.org/D37747 llvm-svn: 314675
* [MIPS] Explicitly list supported relocations for MIPS target. NFCSimon Atanasyan2017-09-211-3/+26
| | | | | | | This is change is inspired by the D28611 patch. New supported relocations have been added to the switch statement. llvm-svn: 313882
* [MIPS] Initial support of microMIPS code linkingSimon Atanasyan2017-09-121-4/+239
| | | | | | | | | | | | | | | | The patch implements initial support of microMIPS code linking: - Handle microMIPS specific relocations. - Emit both R1-R5 and R6 microMIPS PLT records. For now linking mixed set of regular and microMIPS object files is not supported. Also the patch does not handle (setup and clear) the least-significant bit of an address which is utilized as the ISA mode bit and allows to make jump between regular and microMIPS code without any thunks. Differential revision: https://reviews.llvm.org/D37335 llvm-svn: 313028
* [MIPS] Convert template parameters to function arguments. NFCSimon Atanasyan2017-09-041-22/+23
| | | | | | | | Pass BSIZE and SHIFT as a function arguments to the `writeRelocation` routine. It does not make a sense to have so many `writeRelocation's` instances. llvm-svn: 312495
* [MIPS] Add curly brackets to improve code readability. NFC.Simon Atanasyan2017-09-041-2/+2
| | | | llvm-svn: 312494
* [MIPS] Remove unused function's argument. NFCSimon Atanasyan2017-08-281-19/+19
| | | | llvm-svn: 311889
* [MIPS] Merge multiple functions for writing relocation result into the ↵Simon Atanasyan2017-08-241-47/+30
| | | | | | single one. NFC llvm-svn: 311712
* [MIPS] Keep all code read addends in the `getImplicitAddend` functionSimon Atanasyan2017-08-241-0/+4
| | | | | | | | | | Currently LLD reads the R_MIPS_HI16's addends in the `computeMipsAddend` function, the R_MIPS_LO16's addends in both `computeMipsAddend` and `getImplicitAddend` functions. This patch moves reading all addends to the `getImplicitAddend` function. As a side effect it fixes a "paired" HI16/LO16 addend calculation if "LO16" part of a pair is not found. llvm-svn: 311711
* [MIPS] Remove redundant function getPcRelocAddend. NFCSimon Atanasyan2017-08-241-13/+6
| | | | llvm-svn: 311710
* Fix which file is in an error message.Rafael Espindola2017-08-041-1/+2
| | | | | | | When reporting an invalid relocation we were blaming the destination file instead of the file with the relocation. llvm-svn: 310084
* Add trap instructions for ARM and MIPS.Rui Ueyama2017-06-261-0/+1
| | | | | | | This patch fills holes in executable sections with 0xd4 (ARM) or 0xef (MIPS). These trap instructions were suggested by Theo de Raadt. llvm-svn: 306322
* Do not use make<> to allocate TargetInfo. NFC.Rui Ueyama2017-06-161-7/+7
| | | | llvm-svn: 305577
* Split Target.cpp into small files.Rui Ueyama2017-06-161-0/+422
Target.cpp contains code for all the targets that LLD supports. It was simple and easy, but as the number of supported targets increased, it got messy. This patch splits the file into per-target files under ELF/arch directory. Differential Revision: https://reviews.llvm.org/D34222 llvm-svn: 305565
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