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* Implement aarch64 neon instruction set AdvSIMD (Across).Jiangning Liu2013-10-051-4/+12
| | | | llvm-svn: 192029
* Implement aarch64 neon instruction set AdvSIMD (3V elem).Jiangning Liu2013-10-041-16/+94
| | | | llvm-svn: 191945
* Implement aarch64 neon instruction set AdvSIMD (3V Diff), covering the ↵Jiangning Liu2013-09-091-15/+175
| | | | | | | | following 26 instructions, SADDL, UADDL, SADDW, UADDW, SSUBL, USUBL, SSUBW, USUBW, ADDHN, RADDHN, SABAL, UABAL, SUBHN, RSUBHN, SABDL, UABDL, SMLAL, UMLAL, SMLSL, UMLSL, SQDMLAL, SQDMLSL, SMULL, UMULL, SQDMULL, PMULL llvm-svn: 190289
* Inplement aarch64 neon instructions in AdvSIMD(shift). About 24 shift ↵Hao Liu2013-09-041-6/+54
| | | | | | | | | | instructions: sshr,ushr,ssra,usra,srshr,urshr,srsra,ursra,sri,shl,sli,sqshlu,sqshl,uqshl,shrn,sqrshr$ and 4 convert instructions: scvtf,ucvtf,fcvtzs,fcvtzu llvm-svn: 189926
* mangle aarch64 Neon ACLE scalar instrinsic name with BHSD suffix.Kevin Qin2013-08-291-12/+45
| | | | llvm-svn: 189574
* Clang and AArch64 backend patches to support shll/shl and vmovl instructions ↵Hao Liu2013-08-151-7/+8
| | | | | | and ACLE functions llvm-svn: 188452
* AArch64: initial NEON supportTim Northover2013-08-011-132/+442
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Patch by Ana Pazos - Completed implementation of instruction formats: AdvSIMD three same AdvSIMD modified immediate AdvSIMD scalar pairwise - Completed implementation of instruction classes (some of the instructions in these classes belong to yet unfinished instruction formats): Vector Arithmetic Vector Immediate Vector Pairwise Arithmetic - Initial implementation of instruction formats: AdvSIMD scalar two-reg misc AdvSIMD scalar three same - Intial implementation of instruction class: Scalar Arithmetic - Initial clang changes to support arm v8 intrinsics. Note: no clang changes for scalar intrinsics function name mangling yet. - Comprehensive test cases for added instructions To verify auto codegen, encoding, decoding, diagnosis, intrinsics. llvm-svn: 187568
* [NeonIntrinsicTestEmitter] vld1/vst1 do not require the :64 hint.Michael Gottesman2013-06-241-2/+0
| | | | llvm-svn: 184786
* [NeonIntrinsicTestEmitter] Fix incorrect FileCheck pattern where we were ↵Michael Gottesman2013-06-241-2/+2
| | | | | | expecting a ',' prefix to alignment hints. llvm-svn: 184785
* [NeonIntrinsicTestEmitter] Add requirement to arm neon intrinsic tests for ↵Michael Gottesman2013-06-241-0/+2
| | | | | | | | | the feature long_tests. This will prevent the tests from running on normal make check. You will need to actually pass in --param run_long_tests=true to LIT in order to run these. llvm-svn: 184784
* ARM: Improve codegen for vget_low_* and vget_high_ intrinsics.Jim Grosbach2013-05-151-4/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These intrinsics use the __builtin_shuffle() function to extract the low and high half, respectively, of a 128-bit NEON vector. Currently, they're defined to use bitcasts to simplify the emitter, so we get code like: uint16x4_t vget_low_u32(uint16x8_t __a) { return (uint32x2_t) __builtin_shufflevector((int64x2_t) __a, (int64x2_t) __a, 0); } While this works, it results in those bitcasts going all the way through to the IR, resulting in code like: %1 = bitcast <8 x i16> %in to <2 x i64> %2 = shufflevector <2 x i64> %1, <2 x i64> undef, <1 x i32> %zeroinitializer %3 = bitcast <1 x i64> %2 to <4 x i16> We can instead easily perform the operation directly on the input vector like: uint16x4_t vget_low_u16(uint16x8_t __a) { return __builtin_shufflevector(__a, __a, 0, 1, 2, 3); } Not only is that much easier to read on its own, it also results in cleaner IR like: %1 = shufflevector <8 x i16> %in, <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> This is both easier to read and easier for the back end to reason about effectively since the operation is obfuscating the source with bitcasts. rdar://13894163 llvm-svn: 181865
* [neonemitter tests] Change triple of emitted tests to thumbv7s to match the ↵Michael Gottesman2013-04-251-1/+1
| | | | | | target cpu being swift. Also specify the target-abi to apcs-gnu. llvm-svn: 180233
* [6/6] ARM Neon Intrinsic Tablegen Test Generator.Michael Gottesman2013-04-161-1/+462
| | | | | | | | | Added GenerateChecksForIntrinsic method to generate FileCheck patterns for generated arm neon tests. Reviewed by Bob Wilson. llvm-svn: 179644
* [5/6] ARM Neon Intrinsic Tablegen Test Generator.Michael Gottesman2013-04-161-1/+2
| | | | | | | | Changed the test generation target cpu type from cortex-a9 to swift. Reviewed by Bob Wilson. llvm-svn: 179642
* [4/6] ARM Neon Intrinsic Tablegen Test Generator.Michael Gottesman2013-04-161-3/+9
| | | | | | | | | Added code to NeonEmitter::runTests so that GenTest gets all of the needed arguments to invoke the neon test generation methods. Reviewed by Bob Wilson. llvm-svn: 179640
* [3/6] ARM Neon Intrinsic Tablegen Test Generator.Michael Gottesman2013-04-161-28/+44
| | | | | | | | | Refactored out the method InstructionTypeCode from MangleName for use in further patches which perform neon tablegen test generation. Reviewed by Bob Wilson. llvm-svn: 179636
* [2/6] ARM Neon Intrinsic Tablegen Test Generator.Michael Gottesman2013-04-161-1/+17
| | | | | | | | | | This patch causes OpInst records to be silently identified with their Non-Op inst counterparts so that the same test generation infrastructure can be used to generate tests. Reviewed by Bob Wilson. llvm-svn: 179628
* Define Neon intrinsics as "static inline" to avoid warning. rdar://13108414Bob Wilson2013-04-121-1/+1
| | | | | | | | | | | We had been defining Neon intrinsics as "static" with always_inline attributes. If you use them from an extern inline function, you get a warning, e.g.: static function 'vadd_u8' is used in an inline function with external linkage This change simply adds the inline keyword to avoid that warning. llvm-svn: 179406
* Don't throw exceptions in clang-tblgen by switching to PrintFatalError.Joerg Sonnenberger2012-10-251-13/+15
| | | | | | Add locations in a number of places, where they are available for free. llvm-svn: 166691
* Placate the mingw32 buildbot by suffixing 64-bit constants with ULL.Richard Smith2012-08-141-2/+2
| | | | llvm-svn: 161831
* Fix undefined behavior (and wrong code, as far as I can tell) in NEON builtinRichard Smith2012-08-141-3/+3
| | | | | | | | | tablegen code, found by -fcatch-undefined-behavior. I would appreciate if someone more familiar with the NEON code could point me in the direction of how to write a test for this. We appear to have essentially no test coverage whatsoever for these builtins. llvm-svn: 161827
* TableGen: Remove extraneous \ character from arm_neon.h definitions.Jim Grosbach2012-08-031-1/+1
| | | | llvm-svn: 161244
* Make clang-tblgen backends functions instead of TableGenBackends.Jakob Stoklund Olesen2012-06-131-3/+204
| | | | | | | | Get rid of a bunch of header files. TableGen output should be unaffected. Patch by Sean Silva! llvm-svn: 158388
* TableGen: Remove extraneous '\' at EOL in generated tests.Jim Grosbach2012-05-301-1/+1
| | | | llvm-svn: 157700
* ARM: Support marking intrinsic definitions as 'unavailable'Jim Grosbach2012-05-091-4/+8
| | | | llvm-svn: 156490
* Remove unreachable code in Clang. (replace with llvm_unreachable where ↵David Blaikie2012-01-171-11/+1
| | | | | | appropriate or when GCC requires it) llvm-svn: 148292
* Relax type checking for a few Neon intrinsics. <rdar://problem/10538555>Bob Wilson2011-12-201-0/+11
| | | | | | | | | | | | Not long ago, I tightened up the type checking for pointer arguments of Neon intrinsics to match the specifications provided by ARM. One consequence was that it became impossible to access the unaligned versions of a few Neon load/store operations. Since there are just a few of these intrinsics where it makes a difference, I think it's better to relax the type checking than to either introduce new non-standard unaligned intrinsics or to disallow intrinsics for the unaligned operations. llvm-svn: 146963
* Fix Neon builtin pointer argument checking for "sret" builtins.Bob Wilson2011-11-161-6/+24
| | | | | | | | | | | The code for checking Neon builtin pointer argument types was assuming that there would only be one pointer argument. But, for vld2-4 builtins, the first argument is a special sret pointer where the result will be stored. So, instead of scanning all the arguments to find a pointer, have TableGen figure out the index of the pointer argument that needs checking. That's better than scanning all the arguments regardless. <rdar://problem/10448804> llvm-svn: 144834
* Check pointer types for arguments of Neon load/store macros. rdar://9958031Bob Wilson2011-11-081-10/+18
| | | | | | | | | | | The Neon load/store intrinsics need to be implemented as macros to avoid hiding alignment attributes on the pointer arguments, and the macros can only evaluate those pointer arguments once (in case they have side effects), so it has been hard to get the right type checking for those pointers. I tried various alternatives in the arm_neon.h header, but it's much more straightforward to just check directly in Sema. llvm-svn: 144075
* Clean up type flags for overloaded Neon builtins. No functional change.Bob Wilson2011-11-081-13/+9
| | | | | | | | | This patch just adds a simple NeonTypeFlags class to replace the various hardcoded constants that had been used until now. Unfortunately I couldn't figure out a good way to avoid duplicating that class between clang and TableGen, but since it's small and rarely changes, that's not so bad. llvm-svn: 144054
* Add __nodebug__ attribute to functions in arm_neon.hBob Wilson2011-10-141-1/+1
| | | | | | This matches what we do for Intel vector intrinsics. <rdar://problem/10280207> llvm-svn: 141958
* Add the Clang tblgen backends to Clang, and flip the switch to causePeter Collingbourne2011-10-061-0/+1551
the build systems to use clang-tblgen. llvm-svn: 141291
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