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* [X86] Add rdpid command line option and intrinsics.Craig Topper2018-01-202-0/+5
| | | | | | | | | | | | | | Summary: This patch adds -mrdpid/-mno-rdpid and the rdpid intrinsic. The corresponding LLVM commit has already been made. Reviewers: RKSimon, spatel, zvi, AndreiGrischenko Reviewed By: RKSimon Subscribers: cfe-commits Differential Revision: https://reviews.llvm.org/D42272 llvm-svn: 323047
* [X86] Add missing check for RDSEED to ICL, CNL, SKX sections of ↵Craig Topper2018-01-191-0/+6
| | | | | | test/Preprocessor/predefined-arch-macros.c llvm-svn: 322912
* Revert 319303: Add _Float128 as alias to __float128 to enable compilations ↵Erich Keane2018-01-151-10/+10
| | | | | | | | on Fedora27/glibc2 Differential Revision: https://reviews.llvm.org/D40673 llvm-svn: 322518
* [RISCV] Add the RISCV target and compiler driverAlex Bradbury2018-01-111-0/+395
| | | | | | | | | As RV64 codegen has not yet been upstreamed into LLVM, we focus on RV32 driver support (RV64 to follow). Differential Revision: https://reviews.llvm.org/D39963 llvm-svn: 322276
* Preserve unknown STDC pragma through preprocessorSteven Wu2018-01-051-2/+18
| | | | | | | | | | | | | | | | | | | Summary: #pragma STDC FP_CONTRACT handler is only registered in parser so we should keep the unknown STDC pragma through preprocessor and we also should not emit warning for unknown STDC pragma during preprocessor. rdar://problem/35724351 Reviewers: efriedma, rsmith, arphaman Reviewed By: efriedma Subscribers: cfe-commits Differential Revision: https://reviews.llvm.org/D41780 llvm-svn: 321909
* Use backslash escape, replacing xargs -0 in test macro-multiline.cHubert Tong2018-01-041-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: xargs supports escaping of newline characters with backslash. xargs -0 is neither part of POSIX nor the LSB. This patch removes the -0 option and adjusts the input to xargs accordingly; that is, the input is a text file not ending in an incomplete line, and the newline of interest is preceded by a backslash. Note: The treatment of escaped newline characters is not as clearly specified by POSIX as for escaped blank characters; however, the same can be said for escaped backslashes. It is slightly more clear for the case where the -I option is used; however, -I is also of limited portability. Reviewers: bruno Reviewed By: bruno Subscribers: bruno, rcraik, cfe-commits Differential Revision: https://reviews.llvm.org/D41544 llvm-svn: 321828
* Revert r321504 "[X86] Don't accidentally enable PKU on cannon lake and ↵Craig Topper2017-12-291-6/+6
| | | | | | | | | | | | | | icelake or CLWB on cannonlake." I based that commit on what was in Intel's public documentation here https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf Which specifically said CLWB wasn't until Icelake. But I've since cross checked with SDE and it thinks these features exist on CNL and ICL. So now I don't know what to believe. I've added test coverage of the current behavior as part of the revert so at least now have proof of what we're doing. llvm-svn: 321547
* Avoid int to string conversion in Twine or raw_ostream contexts.Benjamin Kramer2017-12-283-41/+41
| | | | | | Some output changes from uppercase hex to lowercase hex, no other functionality change intended. llvm-svn: 321526
* [X86] Don't accidentally enable PKU on cannon lake and icelake or CLWB on ↵Craig Topper2017-12-271-0/+6
| | | | | | | | cannonlake. We have cannonlake and icelake inheriting from skylake server in a switch using fallthroughs. But they aren't perfect supersets of skylake server. llvm-svn: 321504
* [X86] Test that -march=skx enables PKU.Craig Topper2017-12-271-0/+2
| | | | llvm-svn: 321503
* [X86] Enable avx512vpopcntdq and clwb for icelake.Craig Topper2017-12-271-0/+4
| | | | | | Per table 1-1 of the October 2017 edition of Intel® Architecture Instruction Set Extensions and Future Features Programming Reference llvm-svn: 321502
* [x86][icelake][vbmi2]Coby Tayree2017-12-272-0/+23
| | | | | | | | | | | | | | | added vbmi2 feature recognition added intrinsics support for vbmi2 instructions _mm[128,256,512]_mask[z]_compress_epi[16,32] _mm[128,256,512]_mask_compressstoreu_epi[16,32] _mm[128,256,512]_mask[z]_expand_epi[16,32] _mm[128,256,512]_mask[z]_expandloadu_epi[16,32] _mm[128,256,512]_mask[z]_sh[l,r]di_epi[16,32,64] _mm[128,256,512]_mask_sh[l,r]dv_epi[16,32,64] matching a similar work on the backend (D40206) Differential Revision: https://reviews.llvm.org/D41557 llvm-svn: 321487
* [x86][icelake][vnni]Coby Tayree2017-12-271-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | added vnni feature recognition added intrinsics support for VNNI instructions _mm256_mask_dpbusd_epi32 _mm256_maskz_dpbusd_epi32 _mm256_dpbusd_epi32 _mm256_mask_dpbusds_epi32 _mm256_maskz_dpbusds_epi32 _mm256_dpbusds_epi32 _mm256_mask_dpwssd_epi32 _mm256_maskz_dpwssd_epi32 _mm256_dpwssd_epi32 _mm256_mask_dpwssds_epi32 _mm256_maskz_dpwssds_epi32 _mm256_dpwssds_epi32 _mm128_mask_dpbusd_epi32 _mm128_maskz_dpbusd_epi32 _mm128_dpbusd_epi32 _mm128_mask_dpbusds_epi32 _mm128_maskz_dpbusds_epi32 _mm128_dpbusds_epi32 _mm128_mask_dpwssd_epi32 _mm128_maskz_dpwssd_epi32 _mm128_dpwssd_epi32 _mm128_mask_dpwssds_epi32 _mm128_maskz_dpwssds_epi32 _mm128_dpwssds_epi32 _mm512_mask_dpbusd_epi32 _mm512_maskz_dpbusd_epi32 _mm512_dpbusd_epi32 _mm512_mask_dpbusds_epi32 _mm512_maskz_dpbusds_epi32 _mm512_dpbusds_epi32 _mm512_mask_dpwssd_epi32 _mm512_maskz_dpwssd_epi32 _mm512_dpwssd_epi32 _mm512_mask_dpwssds_epi32 _mm512_maskz_dpwssds_epi32 _mm512_dpwssds_epi32 matching a similar work on the backend (D40208) Differential Revision: https://reviews.llvm.org/D41558 llvm-svn: 321484
* [x86][icelake][bitalg]Coby Tayree2017-12-272-0/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | added bitalg feature recognition added intrinsics support for bitalg instructions _mm512_popcnt_epi16 _mm512_mask_popcnt_epi16 _mm512_maskz_popcnt_epi16 _mm512_popcnt_epi8 _mm512_mask_popcnt_epi8 _mm512_maskz_popcnt_epi8 _mm512_mask_bitshuffle_epi64_mask _mm512_bitshuffle_epi64_mask _mm256_popcnt_epi16 _mm256_mask_popcnt_epi16 _mm256_maskz_popcnt_epi16 _mm128_popcnt_epi16 _mm128_mask_popcnt_epi16 _mm128_maskz_popcnt_epi16 _mm256_popcnt_epi8 _mm256_mask_popcnt_epi8 _mm256_maskz_popcnt_epi8 _mm128_popcnt_epi8 _mm128_mask_popcnt_epi8 _mm128_maskz_popcnt_epi8 _mm256_mask_bitshuffle_epi32_mask _mm256_bitshuffle_epi32_mask _mm128_mask_bitshuffle_epi16_mask _mm128_bitshuffle_epi16_mask matching a similar work on the backend (D40222) Differential Revision: https://reviews.llvm.org/D41564 llvm-svn: 321483
* [x86][icelake][vpclmulqdq]Coby Tayree2017-12-272-0/+11
| | | | | | | | | | | added vpclmulqdq feature recognition added intrinsics support for vpclmulqdq instructions _mm256_clmulepi64_epi128 _mm512_clmulepi64_epi128 matching a similar work on the backend (D40101) Differential Revision: https://reviews.llvm.org/D41573 llvm-svn: 321480
* [x86][icelake][gfni]Coby Tayree2017-12-272-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | added gfni feature recognition added intrinsics support for gfni instructions _mm_gf2p8affineinv_epi64_epi8 _mm_mask_gf2p8affineinv_epi64_epi8 _mm_maskz_gf2p8affineinv_epi64_epi8 _mm256_gf2p8affineinv_epi64_epi8 _mm256_mask_gf2p8affineinv_epi64_epi8 _mm256_maskz_gf2p8affineinv_epi64_epi8 _mm512_gf2p8affineinv_epi64_epi8 _mm512_mask_gf2p8affineinv_epi64_epi8 _mm512_maskz_gf2p8affineinv_epi64_epi8 _mm_gf2p8affine_epi64_epi8 _mm_mask_gf2p8affine_epi64_epi8 _mm_maskz_gf2p8affine_epi64_epi8 _mm256_gf2p8affine_epi64_epi8 _mm256_mask_gf2p8affine_epi64_epi8 _mm256_maskz_gf2p8affine_epi64_epi8 _mm512_gf2p8affine_epi64_epi8 _mm512_mask_gf2p8affine_epi64_epi8 _mm512_maskz_gf2p8affine_epi64_epi8 _mm_gf2p8mul_epi8 _mm_mask_gf2p8mul_epi8 _mm_maskz_gf2p8mul_epi8 _mm256_gf2p8mul_epi8 _mm256_mask_gf2p8mul_epi8 _mm256_maskz_gf2p8mul_epi8 _mm512_gf2p8mul_epi8 _mm512_mask_gf2p8mul_epi8 _mm512_maskz_gf2p8mul_epi8 matching a similar work on the backend (D40373) Differential Revision: https://reviews.llvm.org/D41582 llvm-svn: 321477
* [x86][icelake][vaes]Coby Tayree2017-12-272-0/+13
| | | | | | | | | | | | | | | added vaes feature recognition added intrinsics support for vaes instructions, matching a similar work on the backend (D40078) _mm256_aesenc_epi128 _mm512_aesenc_epi128 _mm256_aesenclast_epi128 _mm512_aesenclast_epi128 _mm256_aesdec_epi128 _mm512_aesdec_epi128 _mm256_aesdeclast_epi128 _mm512_aesdeclast_epi128 llvm-svn: 321474
* [X86] Add missing check lines for the silvermont cases in ↵Craig Topper2017-12-221-0/+8
| | | | | | predefined-arch-macros.c test. llvm-svn: 321343
* [X86] Add 'prfchw' to the correct CPUs to match the backend.Craig Topper2017-12-221-0/+18
| | | | llvm-svn: 321341
* __is_target_environment: Check the environment after parsing itAlex Lorenz2017-12-151-0/+6
| | | | | | | This ensures that target triples with environment versions can still work with __is_target_environment. llvm-svn: 320854
* __is_target_arch: Check the arch and subarch instead of the arch nameAlex Lorenz2017-12-151-0/+10
| | | | | | | | | This ensures that when compiling for "arm64" __is_target_arch will succeed for both "arm64" and "aarch64". Thanks to Bob Wilson who pointed this out! llvm-svn: 320853
* Commit missing tests for r320734Alex Lorenz2017-12-144-0/+166
| | | | llvm-svn: 320735
* [Hexagon] Add front-end support for Hexagon V65Krzysztof Parzyszek2017-12-131-0/+14
| | | | llvm-svn: 320579
* Revert 320391: Certain targets are failing, pulling back to diagnose.Erich Keane2017-12-111-5/+5
| | | | llvm-svn: 320398
* For Linux/gnu compatibility, preinclude <stdc-predef.h> if the file is availableErich Keane2017-12-111-5/+5
| | | | | | | | | | | | | | | | | | | | As reported in llvm bugzilla 32377. Here’s a patch to add preinclude of stdc-predef.h. The gcc documentation says “On GNU/Linux, <stdc-predef.h> is pre-included.” See https://gcc.gnu.org/gcc-4.8/porting_to.html; The preinclude is inhibited with –ffreestanding. Basically I fixed the failing test cases by adding –ffreestanding which inhibits this behavior. I fixed all the failing tests, including some in extra/test, there's a separate patch for that which is linked here Note: this is a recommit after a test failure took down the original (r318669) Patch By: mibintc Differential Revision: https://reviews.llvm.org/D34158 llvm-svn: 320391
* Add a test that the __STDC_VERSION__ macro reports the correct value for ↵Aaron Ballman2017-12-081-0/+4
| | | | | | -std=c17. llvm-svn: 320131
* Correct line endings that got mixed up in r320088; NFC.Aaron Ballman2017-12-071-12/+12
| | | | llvm-svn: 320115
* Add support for the __has_c_attribute builtin preprocessor macro.Aaron Ballman2017-12-071-0/+12
| | | | | | This behaves similar to the __has_cpp_attribute builtin macro in that it allows users to detect whether an attribute is supported with the [[]] spelling syntax, which can be enabled in C with -fdouble-square-bracket-attributes. llvm-svn: 320088
* Stringizing raw string literals containing newlineTaewook Oh2017-12-061-0/+11
| | | | | | | | | | | | | | Summary: This patch implements 4.3 of http://open-std.org/jtc1/sc22/wg21/docs/papers/2014/n4220.pdf. If a raw string contains a newline character, replace each newline character with the \n escape code. Without this patch, included test case (macro_raw_string.cpp) results compilation failure. Reviewers: rsmith, doug.gregor, jkorous-apple Reviewed By: jkorous-apple Subscribers: jkorous-apple, vsapsai, cfe-commits Differential Revision: https://reviews.llvm.org/D39279 llvm-svn: 319904
* Add __WINT_MAX__.Ed Schouten2017-12-051-0/+4
| | | | | | | This definition is similar to __WCHAR_MAX__, except that it applies to wint_t. It's also documented as being supported by GCC 4.5 and later. llvm-svn: 319746
* Add _Float128 as alias to __float128 to enable compilations on ↵Erich Keane2017-12-041-10/+10
| | | | | | | | | | | | | | | | | Fedora27/glibc2-26 Fedora27 is using a new version of glibc that refers to the _Float128 type. This patch adds that name as an alias to float128. I also added some predefined macro values for the digits, mantissa, epilon, etc (FloatMacros). For the test case, I copied an existing float128 test. This functionality needs work long term, but it should be sufficient to tread water for a while. At Intel we have test servers running our LLVM compiler with various open source workloads, the server has been upgraded to Fedora27 so many workloads are failing due to _Float128. Patch-By: mibintc Differential Revision: https://reviews.llvm.org/D40673 llvm-svn: 319703
* [OpenCL] Define __IMAGE_SUPPORT__ macro for SPIRSven van Haastregt2017-12-041-0/+4
| | | | | | | | | | | Add #define __IMAGE_SUPPORT__ 1 for SPIR targets to indicate that SPIR supports images. Patch by Dmitry Borisenkov. Differential Revision: https://reviews.llvm.org/D40252 llvm-svn: 319658
* Revert [ARM] disable FPU features when using soft floating point.Keith Walker2017-11-301-264/+45
| | | | | | | This reverts r319420 It is failing the test Driver/arm-mfpu.c so reverting while I investigate the failure. llvm-svn: 319425
* [ARM] disable FPU features when using soft floating point.Keith Walker2017-11-301-45/+264
| | | | | | | | | | | | | | | | | | | | | | | | | | | To be compatible with GCC if soft floating point is in effect any FPU specified is effectively ignored, eg, -mfloat-abi=soft -fpu=neon If any floating point features which require FPU hardware are enabled they must be disable. There was some support for doing this for NEON, but it did not handle VFP, nor did it prevent the backend from emitting the build attribute Tag_FP_arch describing the generated code as using the floating point hardware if a FPU was specified (even though soft float does not use the FPU). Disabling the hardware floating point features for targets which are compiling for soft float has meant that some tests which were incorrectly checking for hardware support also needed to be updated. In such cases, where appropriate the tests have been updated to check compiling for soft float and a non-soft float variant (usually softfp). This was usually because the target specified in the test defaulted to soft float. Differential Revision: https://reviews.llvm.org/D40256 llvm-svn: 319420
* Toolchain: Normalize dwarf, sjlj and seh ehMartell Malone2017-11-292-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a re-apply of r319294. adds -fseh-exceptions and -fdwarf-exceptions flags clang will check if the user has specified an exception model flag, in the absense of specifying the exception model clang will then check the driver default and append the model flag for that target to cc1 -fno-exceptions has a higher priority then specifying the model move __SEH__ macro definitions out of Targets into InitPreprocessor behind the -fseh-exceptions flag move __ARM_DWARF_EH__ macrodefinitions out of verious targets and into InitPreprocessor behind the -fdwarf-exceptions flag and arm|thumb check remove unused USESEHExceptions from the MinGW Driver fold USESjLjExceptions into a new GetExceptionModel function that gives the toolchain classes more flexibility with eh models Reviewers: rnk, mstorsjo Differential Revision: https://reviews.llvm.org/D39673 llvm-svn: 319297
* Revert "Toolchain: Normalize dwarf, sjlj and seh eh"Martell Malone2017-11-292-3/+0
| | | | | | | | This reverts rL319294. The windows sanitizer does not like seh on x86. Will re apply with None type for x86 llvm-svn: 319295
* Toolchain: Normalize dwarf, sjlj and seh ehMartell Malone2017-11-292-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | adds -fseh-exceptions and -fdwarf-exceptions flags clang will check if the user has specified an exception model flag, in the absense of specifying the exception model clang will then check the driver default and append the model flag for that target to cc1 clang cc1 assumes dwarf is the default if none is passed and -fno-exceptions has a higher priority then specifying the model move __SEH__ macro definitions out of Targets into InitPreprocessor behind the -fseh-exceptions flag move __ARM_DWARF_EH__ macrodefinitions out of verious targets and into InitPreprocessor behind the -fdwarf-exceptions flag and arm|thumb check remove unused USESEHExceptions from the MinGW Driver fold USESjLjExceptions into a new GetExceptionModel function that gives the toolchain classes more flexibility with eh models Reviewers: rnk, mstorsjo Differential Revision: https://reviews.llvm.org/D39673 llvm-svn: 319294
* Control-Flow Enforcement Technology - Shadow Stack and Indirect Branch ↵Oren Ben Simhon2017-11-261-0/+4
| | | | | | | | | | | | | | | | | | Tracking support (Clang side) Shadow stack solution introduces a new stack for return addresses only. The stack has a Shadow Stack Pointer (SSP) that points to the last address to which we expect to return. If we return to a different address an exception is triggered. This patch includes shadow stack intrinsics as well as the corresponding CET header. It includes CET clang flags for shadow stack and Indirect Branch Tracking. For more information, please see the following: https://software.intel.com/sites/default/files/managed/4d/2a/control-flow-enforcement-technology-preview.pdf Differential Revision: https://reviews.llvm.org/D40224 Change-Id: I79ad0925a028bbc94c8ecad75f6daa2f214171f1 llvm-svn: 318995
* [MINGW] normalize WIN32 macrosMartell Malone2017-11-211-0/+58
| | | | | | | | | | | | | | move _WIN64 and _WIN32 defines to lib/Basic/Targets/OSTargets.h move WIN32, WIN64 and __MINGW64__ to addMinGWDefines fixes __MINGW64__ not being defined for aarch64 adds WIN32 definition for x64 Reviewers: mstorsjo Differential Revision: https://reviews.llvm.org/D40285 llvm-svn: 318755
* [MS] add an init test for thumbv7-windows-msvcMartell Malone2017-11-211-0/+5
| | | | llvm-svn: 318736
* [MS] Increase default new alignment for win64 and test itReid Kleckner2017-11-211-3/+5
| | | | | | | | | | | | | | | | | | Summary: This raises __STDCPP_DEFAULT_NEW_ALIGNMENT__ from 8 to 16 on Win64. This matches platforms that follow the usual `2 * sizeof(void*)` alignment requirement for malloc. We might want to consider making that the default rather than relying on long double alignment. Fixes PR35356 Reviewers: STL_MSFT, rsmith Subscribers: cfe-commits Differential Revision: https://reviews.llvm.org/D40277 llvm-svn: 318723
* Revert r318669/318694Erich Keane2017-11-201-5/+5
| | | | | | Broke some libclang tests, so reverting for now. llvm-svn: 318698
* For Linux/gnu compatibility, preinclude <stdc-predef.h> if the file is availableErich Keane2017-11-201-5/+5
| | | | | | | | | | | | | | | | | | | | | | As reported in llvm bugzilla 32377. Here’s a patch to add preinclude of stdc-predef.h. The gcc documentation says “On GNU/Linux, <stdc-predef.h> is pre-included.” See https://gcc.gnu.org/gcc-4.8/porting_to.html; The preinclude is inhibited with –ffreestanding. Basically I fixed the failing test cases by adding –ffreestanding which inhibits this behavior. I fixed all the failing tests, including some in extra/test, there's a separate patch for that which is linked here Patch By: mibintc Differential Revision: https://reviews.llvm.org/D34158 llvm-svn: 318669
* [X86] Add icelake CPU support for -march.Craig Topper2017-11-191-0/+89
| | | | llvm-svn: 318617
* [X86] Set __corei7__ preprocessor defines for skylake server and cannonlake.Craig Topper2017-11-191-6/+12
| | | | | | This is the resolution we came to in D38824. llvm-svn: 318616
* [MinGW] Define __ARM_DWARF_EH__ for MinGW/ARMMartin Storsjo2017-11-171-0/+4
| | | | | | | | | Since SVN r318510, the MinGW/ARM configuration defaults to dwarf exception handling. Differential Revision: https://reviews.llvm.org/D39533 llvm-svn: 318511
* [X86] Define i586 and pentium preprocessor defines for -march=lakemont to ↵Craig Topper2017-11-011-7/+11
| | | | | | match GCC llvm-svn: 317069
* Basic: improve coverage for Darwin targets and fix ABISaleem Abdulrasool2017-10-281-0/+62
| | | | | | | | The existing coverage for the Darwin targets wasn't enough to catch all the variations. Improve the coverage a bit further and fix a few cases for Darwin targets. llvm-svn: 316826
* ARM: centralise SizeType, PtrDiffType, and IntPtrTypeSaleem Abdulrasool2017-10-271-0/+5
| | | | | | | | | Centralise the definitions of these compiler vended types to aid inspection to ensure that they are defined similarly. The one case that stands out is the Darwin case where the types do not match up. This fixes the API conformance for APCS-GNU as well. llvm-svn: 316810
* [X86] Make -march=i686 an alias of -march=pentiumproCraig Topper2017-10-261-0/+2
| | | | | | | | I think the only reason they are different is because we don't set tune_i686 for -march=i686 to match GCC. But GCC 4.9.0 seems to have changed this behavior and they do set it now. So I think they can aliases now. Differential Revision: https://reviews.llvm.org/D39349 llvm-svn: 316712
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