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* Fix what looks like accidentally repeated file contents. No behavior change.Nico Weber2015-07-282-6/+0
| | | | llvm-svn: 243376
* [Targets] Define _M_AMD64 and _M_X64 to a more appropriate valueDavid Majnemer2015-07-261-2/+2
| | | | | | We used to define them to 1, we should have defined them to 100. llvm-svn: 243255
* ARM: actually define __ARM_ARCH_7S__ for the armv7s sliceTim Northover2015-07-211-1/+8
| | | | | | | We ended up with the wrong predefine after the recent TargetParser shuffle, and I accidentally solidified it with a test. This should fix it. llvm-svn: 242841
* Allow case-insensitive values for -mtune for AArch64 target in line with GCC.Gabor Ballabas2015-07-201-0/+5
| | | | | | | | | GCC allows case-insensitive values for -mcpu, -march and -mtune options. This patch implements the same behaviour for the -mtune option for the AArch64 target. Differential Revision: http://reviews.llvm.org/D10563 llvm-svn: 242663
* R600: Add macro defs for all supported OpenCL extensionsTom Stellard2015-07-171-1/+8
| | | | llvm-svn: 242523
* [Targets] Define __BOOL_DEFINED for Windows targets in C++ modeDavid Majnemer2015-07-151-0/+2
| | | | | | | | | | MSVC 4.2 didn't have bool as a builtin type but MSVC 5.0 does. When they added it, they added a macro (__BOOL_DEFINED) which allows build scripts and the like to know if they should provide their own bool. Clang always supports bool as a builtin type in C++ mode. llvm-svn: 242307
* Avoid false positive/negative test results from line directive interference.NFC.Chad Rosier2015-06-261-5/+8
| | | | | | | http://reviews.llvm.org/D10443 Patch by Geoff Berry. llvm-svn: 240801
* Add __nonnull/__nullable/__null_unspecified predefines for Darwin.Douglas Gregor2015-06-241-0/+12
| | | | | | Addresses the rest of rdar://problem/21530726. llvm-svn: 240597
* Allow case-insensitive values for -march for AArch64 target in line with GCC.Gabor Ballabas2015-06-181-0/+4
| | | | | | | GCC allows case-insensitive values for -mcpu, -march and -mtune options. This patch implements the same behaviour for the -march option for the AArch64 target. llvm-svn: 240019
* Commit some test changes somehow missed in r239789.Richard Smith2015-06-161-1/+1
| | | | llvm-svn: 239791
* According to the OpenMP spec, all the preprocessor macros should be Samuel Antao2015-06-151-0/+31
| | | | | | expanded in OpenMP pragmas. This patch adds support for that in -E. llvm-svn: 239784
* Allow case-insensitive values for -mcpu for AArch64 target in line with GCC.Gabor Ballabas2015-06-121-0/+6
| | | | | | | GCC allows case-insensitive values for -mcpu, -march and -mtune options. This patch implements the same behaviour for the -mcpu option for the AArch64 target. llvm-svn: 239619
* [ARM] Use TargetParser to determine FPU subtarget featuresJohn Brawn2015-06-051-2/+2
| | | | | | | | | | | | | | | The main effect of this is to fix anomalies where certain -mfpu options didn't disable everything that they should causing strange behaviour when combined with -mcpu or -march values that themselves enabled fpu subtarget features, e.g. -mfpu=fpv5-dp-d16 with -march=armv7em previously behaved the same as -mfpu=fpv5-sp-d16 due to fp-only-sp not being disabled. Invalid -mfpu options now also give an error, which is consistent with the handling of the .fpu directive. Differential Revision: http://reviews.llvm.org/D10239 llvm-svn: 239152
* [SPARC] Fix types of size_t, intptr_t, and ptrdiff_t on Linux.James Y Knight2015-06-041-7/+16
| | | | | | | | They should be 'int' instead of 'long int' everywhere else except NetBSD too, from what I gather in GCC's spec files. So, optimistically changing it for everyone else, too. llvm-svn: 239046
* ARM: fix ACLE predefine for iOS's "-arch armv7s".Tim Northover2015-05-291-0/+1
| | | | | | We were getting "#define __ARM_ARCH_7 -S__ 1" which is really not a good idea. llvm-svn: 238614
* [Basic] Define __declspec for cygwinDavid Majnemer2015-05-281-0/+10
| | | | | | | | Cygwin (and MinGW) targets define __declspec to __attribute__ unless -fms-extensions is specified. It turns out that cygwin headers rely on the existence of this macro. llvm-svn: 238394
* Bug fix for PR23577 (https://llvm.org/bugs/show_bug.cgi?id=23577#c0).Alexander Musman2015-05-251-1/+44
| | | | | | | | | | | | "1-4" specifiers are returned as numeric constants, not identifiers, and should be treated as such. Currently pragma handler incorrectly assumes that they are returned as identifiers. Patch by Andrey Bokhanko. Differential Revision: http://reviews.llvm.org/D9856 llvm-svn: 238129
* Testing for the fix for bug 23429.Nemanja Ivanovic2015-05-141-0/+13
| | | | | | | | | Follow-up to commit for revision 236848. Just a test case for the macro definition under the right CPU/Arch. One combination was actually missed in the initial fix: - powerpc64-unknown-unknown -mcpu=pwr8 (rather than -mcpu=power8). llvm-svn: 237386
* [ARM] Add v8.1a architectureVladimir Sukharev2015-05-141-0/+5
| | | | | | | | | | | | | | Add support for ARMv8.1a architecture. Briefly it is described on http://community.arm.com/groups/processors/blog/2014/12/02/the-armv8-a-architecture-and-its-ongoing-development Reviewers: jmolloy, rengolin Subscribers: cfe-commits Differential Revision: http://reviews.llvm.org/D8799 llvm-svn: 237349
* [Sparc] Add support for 'sparcel' to clang.Douglas Katzman2015-05-111-0/+33
| | | | | | Differential Revision: http://reviews.llvm.org/D8784 llvm-svn: 237001
* Disable __has_cpp_attribute when not compiling in C++ mode. As this feature ↵Aaron Ballman2015-05-111-1/+4
| | | | | | | | test macro only supports C++ style attributes, it doesn't apply to code compiled as C code, and can lead to diagnostics when given a scoped attribute. This addresses PR23435. llvm-svn: 236996
* [MSVC] Mimic MSVC whitespace collapse for incompatible token pastingWill Wilson2015-04-171-0/+7
| | | | | | | | | | In public MS headers for XAudio, clang would fail to generate a valid UUID due to the UUID components being combined with the '-' UUID separators. Clang would attempting to recover but would preserve the leading whitespace from the tokens after each failed paste leading to spaces creeping into the UUID and causing an error in the __declspace(uuid()) parsing. Reference: Microsoft DirectX SDK (June 2010)\Include\XAudio2.h(51) Resolves http://llvm.org/pr23071 llvm-svn: 235186
* [AArch64] Add v8.1a architectureVladimir Sukharev2015-04-161-0/+8
| | | | | | | | | | | | Add support for AArch64 v8.1 architecture. Briefly it is described on http://community.arm.com/groups/processors/blog/2014/12/02/the-armv8-a-architecture-and-its-ongoing-development Reviewers: jmolloy Subscribers: cfe-commits Differential Revision: http://reviews.llvm.org/D8493 llvm-svn: 235110
* [Mips] Generate warning for invalid '-mnan' and '-march' combinationsPetar Jovanovic2015-04-141-1/+6
| | | | | | | | | | | | This patch generates a warning for invalid combination of '-mnan' and '-march' options, it properly sets NaN encoding for a given '-march', and it passes a proper NaN encoding to the assembler. Patch by Vladimir Radosavljevic. Differential Revision: http://reviews.llvm.org/D8170 llvm-svn: 234882
* [ARM] add support for Cortex-R4/R4FJaved Absar2015-04-091-0/+18
| | | | | | | | Adds ARM Cortex-R4 and R4F support and tests in Clang. Though Cortex-R4 support was present, the support for hwdiv in thumb-mode was not defined or tested properly. This has also been added. llvm-svn: 234488
* Set the type of ptrdiff_t to signed on NVPTX targetsEli Bendersky2015-04-011-3/+3
| | | | | | | It was unsigned before, which is unlike any other target and also doesn't make much sense. llvm-svn: 233836
* Set NVPTX64 target's size_t to match other 64-bit targetsEli Bendersky2015-04-011-8/+8
| | | | llvm-svn: 233830
* [SystemZ] Support transactional execution on zEC12Ulrich Weigand2015-04-011-0/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The zEC12 provides the transactional-execution facility. This is exposed to users via a set of builtin routines on other compilers. This patch adds clang support to enable those builtins. In partciular, the patch: - enables the transactional-execution feature by default on zEC12 - allows to override presence of that feature via the -mhtm/-mno-htm options - adds a predefined macro __HTM__ if the feature is enabled - adds support for the transactional-execution GCC builtins - adds Sema checking to verify the __builtin_tabort abort code - adds the s390intrin.h header file (for GCC compatibility) - adds s390 sections to the htmintrin.h and htmxlintrin.h header files Since this is first use of target-specific intrinsics on the platform, the patch creates the include/clang/Basic/BuiltinsSystemZ.def file and hooks it up in TargetBuiltins.h and lib/Basic/Targets.cpp. An associated LLVM patch adds the required LLVM IR intrinsics. For reference, the transactional-execution instructions are documented in the z/Architecture Principles of Operation for the zEC12: http://publibfp.boulder.ibm.com/cgi-bin/bookmgr/download/DZ9ZR009.pdf The associated builtins are documented in the GCC manual: http://gcc.gnu.org/onlinedocs/gcc/S_002f390-System-z-Built-in-Functions.html The htmxlintrin.h intrinsics provided for compatibility with the IBM XL compiler are documented in the "z/OS XL C/C++ Programming Guide". llvm-svn: 233804
* [SystemZ] Fix definition of IntMaxType / Int64TypeUlrich Weigand2015-03-302-26/+26
| | | | | | | | Like on other 64-bit platforms, Int64Type should be SignedLong on SystemZ, not SignedLongLong as per default. This could cause ABI incompatibilities in certain cases (e.g. name mangling). llvm-svn: 233544
* [lex] Don't create a garbage token if parsing of __has_include fails.Benjamin Kramer2015-03-291-0/+12
| | | | | | It will crash downstream somewhere. Found by afl-fuzz. llvm-svn: 233493
* Make the msse4/mno-sse4 flags aliases of the maximum sse valuesEric Christopher2015-03-251-0/+4
| | | | | | | | | | | | | they enable/disable. This fixes two things: a) sse4 isn't actually a target feature, don't treat it as one. b) we weren't correctly disabling sse4.1 when we'd pass -mno-sse4 after enabling it, thus passing preprocessor directives and (soon) passing the function attribute as well when we shouldn't. llvm-svn: 233223
* Disable this test for PS4 target because PS4 issues different diagnostics.Yunzhong Gao2015-03-251-0/+1
| | | | llvm-svn: 233210
* Adds a warning for unrecognized argument to #pragma comment() on PS4.Yunzhong Gao2015-03-231-0/+27
| | | | | | | | | | | PS4 target recognizes the #pragma comment() syntax as in -fms-extensions, but only handles the case of #pragma comment(lib). This patch adds a warning if any other arguments are encountered. This patch also refactors the code in ParsePragma.cpp a little bit to make it more obvious that some codes are being shared between -fms-extensions and PS4. llvm-svn: 233015
* Lex: Don't call getIdentifierInfo on annotation tokensDavid Majnemer2015-03-181-0/+8
| | | | | | | | These calls are usually guarded by checks for isAnnotation() but it looks like we missed a spot. This would cause the included test to crash clang. llvm-svn: 232616
* [PowerPC] ABI support for the QPX vector instruction setHal Finkel2015-03-111-0/+1
| | | | | | | | | | | | | | Support for the QPX vector instruction set, used on the IBM BG/Q supercomputer, has recently been added to the LLVM PowerPC backend. This vector instruction set requires some ABI modifications because the ABI on the BG/Q expects <4 x double> vectors to be provided with 32-byte stack alignment, and to be handled as native vector types (similar to how Altivec vectors are handled on mainline PPC systems). I've named this ABI variant elfv1-qpx, have made this the default ABI when QPX is supported, and have updated the ABI handling code to provide QPX vectors with the correct stack alignment and associated register-assignment logic. llvm-svn: 231960
* Add target information for CloudABI on x86-64.Ed Schouten2015-03-111-0/+305
| | | | | | | | | | | CloudABI can be identified by the __CloudABI__ preprocessor definition. The system uses ELF executables. CloudABI uses Unicode 7.0.0 for the encoding of wchar_t. As Unicode 7.0.0 is synchronized with ISO/IEC 10646:2012 (released on 2012-06-01), __STDC_ISO_10646__ is defined as 201206L. llvm-svn: 231912
* Add Clang support for PPC cryptography builtinsNemanja Ivanovic2015-03-041-0/+6
| | | | | | Review: http://reviews.llvm.org/D7951 llvm-svn: 231291
* Add __ARM_DWARF_EH__ to signify the use of Itanium ABI for unwind instructions.Renato Golin2015-02-271-0/+7
| | | | | | | | Equally to NetBSD, Bitrig will be using .eh_frame unwinding on ARM. Patch by Patrick Wildt. llvm-svn: 230763
* AMDGCN: Define cl_khr_fp64 when compiling OpenCL programsTom Stellard2015-02-271-0/+3
| | | | llvm-svn: 230761
* Add -fuse-line-directive flag to control usage of #line with -EReid Kleckner2015-02-261-6/+6
| | | | | | | | | | | | | | | | | | Currently -fms-extensions controls this behavior, which doesn't make much sense. It means we can't identify what is and isn't a system header when compiling our own preprocessed output, because #line doesn't represent this information. If someone is feeding Clang's preprocessed output to another compiler, they can use this flag. Fixes PR20553. Reviewers: rsmith Differential Revision: http://reviews.llvm.org/D5217 llvm-svn: 230587
* Commit patch for PR19649. Set the correct sign of wide character for ↵Michael Wong2015-02-242-0/+12
| | | | | | | | | | literals based on underlying type of wchar_t. Reviewed: http://reviews.llvm.org/D7559 Patch by Rachel Craig; Test cases by Hubert Tong. llvm-svn: 230333
* Add C11 *_DECIMAL_DIG.Ed Schouten2015-02-231-37/+40
| | | | | | | | | | | | | | | Before C11 there was only the DECIMAL_DIG definition. As of C11, we now have one definition per floating point type (e.g. DBL_DECIMAL_DIG). Change the existing code to define the new versions. To remain backward compatible, define __DECIMAL_DIG__ as __LDBL_DECIMAL_DIG__. Also update the tests. It seems that some of the existing test vectors were incorrect. Change all tests for __DECIMAL_DIG__ to expect __LDBL_DECIMAL_DIG__. Add tests for *_DECIMAL_DIG for FreeBSD/amd64, as I happen to have such a system laying around. I've validated that the values are in sync with <float.h>. llvm-svn: 230207
* [Mips] Support mips32r3, mips32r5, mips64r3, mips64r5 MIPS ISA namesSimon Atanasyan2015-02-201-0/+36
| | | | | | | | | The patch teaches the clang's driver to understand new MIPS ISA names, pass appropriate options to the assembler, defines corresponding macros etc http://reviews.llvm.org/D7737 llvm-svn: 230092
* [ARM] Add missing M/R class CPUsBradley Smith2015-02-181-0/+13
| | | | | | | | | | | | Add some of the missing M and R class Cortex CPUs, namely: Cortex-M0+ (called Cortex-M0plus for GCC compatibility) Cortex-M1 SC000 SC300 Cortex-R5 llvm-svn: 229661
* [mips] Partially revert r223927: Removing __SIZEOF_INT128__ macro for MIPS64Vasileios Kalintiris2015-02-121-2/+2
| | | | | | | | Partially revert r223927 because LLVM gained support for 128-bit integers in r227089. Modify and keep the tests that verify the definition of the macro __SIZEOF_INT128__ for MIPS64 BE & LE in the preprocessor. llvm-svn: 228918
* Preprocessor: support __BIGGEST_ALIGNMENT__ macroTim Northover2015-02-061-0/+224
| | | | | | | | | | | For compatibility with GCC (and because it's generally helpful information otherwise inaccessible to the preprocessor). This appears to be canonically the alignment of max_align_t (e.g. on i386, __BIGGEST_ALIGNMENT__ is 4 even though vector types will be given greater alignment). Patch mostly by Mats Petersson llvm-svn: 228367
* Teaches the Clang driver to accept Cortex-A72Renato Golin2015-02-041-0/+2
| | | | | | | | | A previous commit added Cortex-A72 to LLVM, this teaches Clang to accept it as well. Patch by Ranjeet Singh. llvm-svn: 228141
* No longer SCE_PRIVATE ;)Sean Silva2015-01-271-1/+0
| | | | llvm-svn: 227200
* Begin to teach clang about the PS4.Alex Rosenberg2015-01-271-0/+114
| | | | llvm-svn: 227194
* [Mips] Fix type of 64-bit integer in case of MIPS N64 ABISimon Atanasyan2015-01-222-58/+672
| | | | | | Differential Revision: http://reviews.llvm.org/D7127 llvm-svn: 226877
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