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* [ARM] add support for Cortex-R4/R4FJaved Absar2015-04-091-0/+18
| | | | | | | | Adds ARM Cortex-R4 and R4F support and tests in Clang. Though Cortex-R4 support was present, the support for hwdiv in thumb-mode was not defined or tested properly. This has also been added. llvm-svn: 234488
* [ARM] Add missing M/R class CPUsBradley Smith2015-02-181-0/+13
| | | | | | | | | | | | Add some of the missing M and R class Cortex CPUs, namely: Cortex-M0+ (called Cortex-M0plus for GCC compatibility) Cortex-M1 SC000 SC300 Cortex-R5 llvm-svn: 229661
* [ARM] Define __ARM_FEATURE_DSP macro for CPUs that have DSP instructionsSergey Dmitrouk2014-11-251-1/+32
| | | | | | | | | | | | | | | | | Summary: This resolves [[ http://llvm.org/bugs/show_bug.cgi?id=17391 | PR17391 ]]. GCC's sources were used as a guide (couldn't find much information in ARM documentation). Reviewers: doug.gregor, asl Reviewed By: asl Subscribers: asl, aemerson, cfe-commits Differential Revision: http://reviews.llvm.org/D6339 llvm-svn: 222741
* Adds support for the Cortex-A17 processor to ClangRenato Golin2014-10-131-0/+19
| | | | | | Patch by Matthew Wahab. llvm-svn: 219607
* [ARM] Add support for Cortex-M7, FPv5-SP and FPv5-DPOliver Stannard2014-10-011-0/+4
| | | | | | | | | The Cortex-M7 has 3 options for its FPU: none, FPv5-SP-D16 and FPv5-DP-D16. FPv5 has the same instructions as FP-ARMv8, so it can be modeled using the same target feature, and all double-precision operations are already disabled by the fp-only-sp target features. llvm-svn: 218748
* [ARM] Add ACLE predefines: maxmin, rounding and h/w integer divisionJames Molloy2014-09-151-0/+8
| | | | | | Patch by Assad Hashmi! llvm-svn: 217760
* test: add missed file in previous commitSaleem Abdulrasool2014-06-151-3/+3
| | | | llvm-svn: 210992
* Fix broken CHECK linesNico Rieck2014-02-161-1/+1
| | | | llvm-svn: 201477
* [ARM] Add ACLE enum/wchar size predefinesBradley Smith2014-01-201-0/+9
| | | | llvm-svn: 199642
* Added support for mcpu kraitAna Pazos2013-12-061-0/+10
| | | | | | | | | | | | - krait processor currently modeled with the same features as A9. - Krait processor additionally has VFP4 (fused multiply add/sub) and hardware division features enabled. - krait has currently the same Schedule model as A9 - krait cpu flag is not recognized by the GNU assembler yet, it is replaced with march=armv7-a to avoid a lower march from being used. llvm-svn: 196618
* [ARM] Enable FeatureMP for Cortex-A5 by default.Amara Emerson2013-11-251-0/+22
| | | | | | Patch by Oliver Stannard. llvm-svn: 195641
* Add support for Cortex-A12.Richard Barton2013-11-221-0/+20
| | | | | | Patch by Oliver Stannard! llvm-svn: 195449
* [ARM] add basic support for Cortex-A7 and VFPv4 to ClangArtyom Skrobov2013-11-211-0/+25
| | | | llvm-svn: 195359
* ARM: Add -m[no-]crc to dis/enable CRC subtargetfeature from clangBernard Ogden2013-10-291-0/+3
| | | | | | | | Allow users to disable or enable CRC subtarget feature. Differential Revision: http://llvm-reviews.chandlerc.com/D2037 llvm-svn: 193600
* Add driver support for FP, SIMD and crypto defaults.Bernard Ogden2013-10-241-0/+17
| | | | | | | | | Although we wire up a bit for v8fp for macro setting purposes, we don't set a macro yet. Need to ask list about that. Change-Id: Ic9819593ce00882fbec72757ffccc6f0b18160a0 llvm-svn: 193367
* Set the default hardware division features for ARM cpus. Also set it as ↵Silviu Baranga2013-10-211-0/+126
| | | | | | default for A32 armv8. llvm-svn: 193075
* [ARMv8] Add builtins for CRC instructions.Joey Gouly2013-09-181-0/+11
Patch by Bradley Smith! llvm-svn: 190931
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