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* [Clang][Darwin] Define __ARM_DWARF_EH__ for WatchABIChris Bieneman2016-04-291-0/+1
| | | | | | | | | | | | Summary: The Darwin armv7k ABI uses Dwarf EH, so we need to set the OS define correctly. Without this the gcc_personality fails to build. Reviewers: t.p.northover Subscribers: aemerson, cfe-commits, rengolin Differential Revision: http://reviews.llvm.org/D19693 llvm-svn: 268078
* Add accidentally dropped test to r267880.Tim Northover2016-04-281-0/+10
| | | | | | Forgot "git add". llvm-svn: 267881
* Clean up a couple more preprocessor tests to use match-full-lines.James Y Knight2016-04-011-179/+179
| | | | llvm-svn: 265187
* Combine identical check-prefixes in Clang ↵Artyom Skrobov2016-03-231-149/+75
| | | | | | | | | | | | test/Preprocessor/arm-target-features.c Reviewers: rengolin, t.p.northover Subscribers: aemerson, cfe-commits, rengolin Differential Revision: http://reviews.llvm.org/D18391 llvm-svn: 264155
* [ARM] Clang tests for ARM Cortex-A32 supportRenato Golin2016-03-211-10/+12
| | | | | | Patch by Sam Parker. llvm-svn: 263957
* Add more ARM Cortex-R8 regression tests to Clang.Pablo Barrio2016-03-161-10/+12
| | | | | | | | | | | | | | Summary: This patch adds Clang tests for Cortex-R8 related to FP capabilities and hardware integer divide. Reviewers: rengolin, bsmith Subscribers: aemerson, cfe-commits, rengolin Differential Revision: http://reviews.llvm.org/D18193 llvm-svn: 263632
* Test commit - Remove some trailing whitespacePablo Barrio2016-03-151-1/+1
| | | | llvm-svn: 263574
* [ARM] Add Clang targeting for ARMv8-M Baseline/MainlineBradley Smith2016-03-031-0/+36
| | | | llvm-svn: 262619
* [ARM] Add command-line options for ARMv8.2-AOliver Stannard2016-02-111-0/+6
| | | | | | | | | | | | | | | | | This allows ARMv8.2-A to be targeted either by using "armv8.2a" in the triple, or by using -march=armv8.2-a (or the alias -march=armv8.2a). The FP16 extension can be enabled with the "+fp16" suffix to the -march or -mcpu option. This is consistent with the AArch64 option, rather than the usual ARM option of -mfpu. We have agreed with the team which will be upstreaming this to GCC that we want to use this new option format for new architecture extensions for both ARM and AArch64. Most of the work for this was done by the TargetParser patch in llvm. Differential Revision: http://reviews.llvm.org/D15040 llvm-svn: 260533
* ARM v8.1a adds Advanced SIMD instructions for Rounding Double MultiplyAlexandros Lamprineas2015-11-291-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | Add/Subtract. The following instructions are added to AArch32 instruction set: - VQRDMLAH: Vector Saturating Rounding Doubling Multiply Accumulate Returning High Half - VQRDMLSH: Vector Saturating Rounding Doubling Multiply Subtract Returning High Half The following instructions are added to AArch64 instruction set: - SQRDMLAH: Signed Saturating Rounding Doubling Multiply Accumulate Returning High Half - SQRDMLSH: Signed Saturating Rounding Doubling Multiply Subtract Returning High Half This patch adds intrinsic and ACLE macro support for these instructions, as well as corresponding tests. Differential Revision: http://reviews.llvm.org/D14982 llvm-svn: 254250
* Support watchOS and tvOS driver optionsTim Northover2015-10-301-3/+2
| | | | | | | | This patch should add support for almost all command-line options and driver tinkering necessary to produce a correct "clang -cc1" invocation for watchOS and tvOS. llvm-svn: 251706
* Fix __ARM_FP value for sp-only FPUs with Half-precisionRichard Barton2015-10-211-10/+61
| | | | | | | | | The logic for parsing FP capabilities to set __ARM_FP was mistakenly removing the Half-Precision capability when handling fp-only-sp resulting in a value of 0x4. Section 6.5.1 of ACLE states that for such FP architectures the value should be 0x6 llvm-svn: 250888
* Implement ACLE 2.0 macros of chapters 6.6 and 6.7 for [ARM] and [Aarch64] ↵Alexandros Lamprineas2015-10-021-0/+9
| | | | | | | | targets. Differential Revision: http://reviews.llvm.org/D12633 llvm-svn: 249140
* [ARM] Allow passing/returning of __fp16 argumentsOliver Stannard2015-09-031-0/+2
| | | | | | | | | | | | | | | | | | | | | The ACLE (ARM C Language Extensions) 2.0 allows the __fp16 type to be used as a functon argument or return type (ACLE 1.1 did not). The current public release of the AAPCS (2.09) states that __fp16 values should be converted to single-precision before being passed or returned, but AAPCS 2.10 (to be released shortly) changes this, so that they are passed in the least-significant 16 bits of either a GPR (for base AAPCS) or a single-precision register (for AAPCS-VFP). This does not change how arguments are passed if they get passed on the stack. This patch brings clang up to compliance with the latest versions of both of these specs. We can now set the __ARM_FP16_ARGS ACLE predefine, and we have always been able to set the __ARM_FP16_FORMAT_IEEE predefine (we do not support the alternative format). llvm-svn: 246764
* Revert 246755 as it breaks buildbotsOliver Stannard2015-09-031-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | Original commit message: [ARM] Allow passing/returning of __fp16 arguments The ACLE (ARM C Language Extensions) 2.0 allows the __fp16 type to be used as a functon argument or return type (ACLE 1.1 did not). The current public release of the AAPCS (2.09) states that __fp16 values should be converted to single-precision before being passed or returned, but AAPCS 2.10 (to be released shortly) changes this, so that they are passed in the least-significant 16 bits of either a GPR (for base AAPCS) or a single-precision register (for AAPCS-VFP). This does not change how arguments are passed if they get passed on the stack. This patch brings clang up to compliance with the latest versions of both of these specs. We can now set the __ARM_FP16_ARGS ACLE predefine, and we have always been able to set the __ARM_FP16_FORMAT_IEEE predefine (we do not support the alternative format). llvm-svn: 246760
* [ARM] Allow passing/returning of __fp16 argumentsOliver Stannard2015-09-031-0/+2
| | | | | | | | | | | | | | | | | | | | | The ACLE (ARM C Language Extensions) 2.0 allows the __fp16 type to be used as a functon argument or return type (ACLE 1.1 did not). The current public release of the AAPCS (2.09) states that __fp16 values should be converted to single-precision before being passed or returned, but AAPCS 2.10 (to be released shortly) changes this, so that they are passed in the least-significant 16 bits of either a GPR (for base AAPCS) or a single-precision register (for AAPCS-VFP). This does not change how arguments are passed if they get passed on the stack. This patch brings clang up to compliance with the latest versions of both of these specs. We can now set the __ARM_FP16_ARGS ACLE predefine, and we have always been able to set the __ARM_FP16_FORMAT_IEEE predefine (we do not support the alternative format). llvm-svn: 246755
* ARM: actually define __ARM_ARCH_7S__ for the armv7s sliceTim Northover2015-07-211-1/+8
| | | | | | | We ended up with the wrong predefine after the recent TargetParser shuffle, and I accidentally solidified it with a test. This should fix it. llvm-svn: 242841
* [ARM] Use TargetParser to determine FPU subtarget featuresJohn Brawn2015-06-051-2/+2
| | | | | | | | | | | | | | | The main effect of this is to fix anomalies where certain -mfpu options didn't disable everything that they should causing strange behaviour when combined with -mcpu or -march values that themselves enabled fpu subtarget features, e.g. -mfpu=fpv5-dp-d16 with -march=armv7em previously behaved the same as -mfpu=fpv5-sp-d16 due to fp-only-sp not being disabled. Invalid -mfpu options now also give an error, which is consistent with the handling of the .fpu directive. Differential Revision: http://reviews.llvm.org/D10239 llvm-svn: 239152
* ARM: fix ACLE predefine for iOS's "-arch armv7s".Tim Northover2015-05-291-0/+1
| | | | | | We were getting "#define __ARM_ARCH_7 -S__ 1" which is really not a good idea. llvm-svn: 238614
* [ARM] Add v8.1a architectureVladimir Sukharev2015-05-141-0/+5
| | | | | | | | | | | | | | Add support for ARMv8.1a architecture. Briefly it is described on http://community.arm.com/groups/processors/blog/2014/12/02/the-armv8-a-architecture-and-its-ongoing-development Reviewers: jmolloy, rengolin Subscribers: cfe-commits Differential Revision: http://reviews.llvm.org/D8799 llvm-svn: 237349
* [ARM] add support for Cortex-R4/R4FJaved Absar2015-04-091-0/+18
| | | | | | | | Adds ARM Cortex-R4 and R4F support and tests in Clang. Though Cortex-R4 support was present, the support for hwdiv in thumb-mode was not defined or tested properly. This has also been added. llvm-svn: 234488
* [ARM] Add missing M/R class CPUsBradley Smith2015-02-181-0/+13
| | | | | | | | | | | | Add some of the missing M and R class Cortex CPUs, namely: Cortex-M0+ (called Cortex-M0plus for GCC compatibility) Cortex-M1 SC000 SC300 Cortex-R5 llvm-svn: 229661
* [ARM] Define __ARM_FEATURE_DSP macro for CPUs that have DSP instructionsSergey Dmitrouk2014-11-251-1/+32
| | | | | | | | | | | | | | | | | Summary: This resolves [[ http://llvm.org/bugs/show_bug.cgi?id=17391 | PR17391 ]]. GCC's sources were used as a guide (couldn't find much information in ARM documentation). Reviewers: doug.gregor, asl Reviewed By: asl Subscribers: asl, aemerson, cfe-commits Differential Revision: http://reviews.llvm.org/D6339 llvm-svn: 222741
* Adds support for the Cortex-A17 processor to ClangRenato Golin2014-10-131-0/+19
| | | | | | Patch by Matthew Wahab. llvm-svn: 219607
* [ARM] Add support for Cortex-M7, FPv5-SP and FPv5-DPOliver Stannard2014-10-011-0/+4
| | | | | | | | | The Cortex-M7 has 3 options for its FPU: none, FPv5-SP-D16 and FPv5-DP-D16. FPv5 has the same instructions as FP-ARMv8, so it can be modeled using the same target feature, and all double-precision operations are already disabled by the fp-only-sp target features. llvm-svn: 218748
* [ARM] Add ACLE predefines: maxmin, rounding and h/w integer divisionJames Molloy2014-09-151-0/+8
| | | | | | Patch by Assad Hashmi! llvm-svn: 217760
* test: add missed file in previous commitSaleem Abdulrasool2014-06-151-3/+3
| | | | llvm-svn: 210992
* Fix broken CHECK linesNico Rieck2014-02-161-1/+1
| | | | llvm-svn: 201477
* [ARM] Add ACLE enum/wchar size predefinesBradley Smith2014-01-201-0/+9
| | | | llvm-svn: 199642
* Added support for mcpu kraitAna Pazos2013-12-061-0/+10
| | | | | | | | | | | | - krait processor currently modeled with the same features as A9. - Krait processor additionally has VFP4 (fused multiply add/sub) and hardware division features enabled. - krait has currently the same Schedule model as A9 - krait cpu flag is not recognized by the GNU assembler yet, it is replaced with march=armv7-a to avoid a lower march from being used. llvm-svn: 196618
* [ARM] Enable FeatureMP for Cortex-A5 by default.Amara Emerson2013-11-251-0/+22
| | | | | | Patch by Oliver Stannard. llvm-svn: 195641
* Add support for Cortex-A12.Richard Barton2013-11-221-0/+20
| | | | | | Patch by Oliver Stannard! llvm-svn: 195449
* [ARM] add basic support for Cortex-A7 and VFPv4 to ClangArtyom Skrobov2013-11-211-0/+25
| | | | llvm-svn: 195359
* ARM: Add -m[no-]crc to dis/enable CRC subtargetfeature from clangBernard Ogden2013-10-291-0/+3
| | | | | | | | Allow users to disable or enable CRC subtarget feature. Differential Revision: http://llvm-reviews.chandlerc.com/D2037 llvm-svn: 193600
* Add driver support for FP, SIMD and crypto defaults.Bernard Ogden2013-10-241-0/+17
| | | | | | | | | Although we wire up a bit for v8fp for macro setting purposes, we don't set a macro yet. Need to ask list about that. Change-Id: Ic9819593ce00882fbec72757ffccc6f0b18160a0 llvm-svn: 193367
* Set the default hardware division features for ARM cpus. Also set it as ↵Silviu Baranga2013-10-211-0/+126
| | | | | | default for A32 armv8. llvm-svn: 193075
* [ARMv8] Add builtins for CRC instructions.Joey Gouly2013-09-181-0/+11
Patch by Bradley Smith! llvm-svn: 190931
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