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* Implement Attribute Target MultiVersioningErich Keane2018-01-083-0/+137
| | | | | | | | | | | | | | | | | | | | | | | | | | | | GCC's attribute 'target', in addition to being an optimization hint, also allows function multiversioning. We currently have the former implemented, this is the latter's implementation. This works by enabling functions with the same name/signature to coexist, so that they can all be emitted. Multiversion state is stored in the FunctionDecl itself, and SemaDecl manages the definitions. Note that it ends up having to permit redefinition of functions so that they can all be emitted. Additionally, all versions of the function must be emitted, so this also manages that. Note that this includes some additional rules that GCC does not, since defining something as a MultiVersion function after a usage has been made illegal. The only 'history rewriting' that happens is if a function is emitted before it has been converted to a multiversion'ed function, at which point its name needs to be changed. Function templates and virtual functions are NOT yet supported (not supported in GCC either). Additionally, constructors/destructors are disallowed, but the former is planned. llvm-svn: 322028
* Fix test added in r321992 failing on some buildbots (again), test requires x86.Sean Eveson2018-01-081-0/+2
| | | | llvm-svn: 322000
* [CodeGen] Fix TBAA info for accesses to members of base classesIvan A. Kosarev2018-01-081-0/+53
| | | | | | | | | | | Resolves: Bug 35724 - regression (r315984): fatal error: error in backend: Broken function found (Did not see access type in access path!) https://bugs.llvm.org/show_bug.cgi?id=35724 Differential Revision: https://reviews.llvm.org/D41547 llvm-svn: 321999
* Fix test added in r321992 failing on some buildbots.Sean Eveson2018-01-081-2/+2
| | | | llvm-svn: 321995
* [Driver] Add flag enabling the function stack size section that was added in ↵Sean Eveson2018-01-081-0/+7
| | | | | | | | | | r319430 Adds the -fstack-size-section flag to enable the .stack_sizes section. The flag defaults to on for the PS4 triple. Differential Revision: https://reviews.llvm.org/D40712 llvm-svn: 321992
* Add support for a limited subset of TS 18661-3 math builtins.Benjamin Kramer2018-01-061-6/+14
| | | | | | | | | | | | | | | | | These just overloads for _Float128. They're supported by GCC 7 and used by glibc. APFloat support is already there so just add the overloads. __builtin_copysignf128 __builtin_fabsf128 __builtin_huge_valf128 __builtin_inff128 __builtin_nanf128 __builtin_nansf128 This is the same support that GCC has, according to the documentation, but limited to _Float128. llvm-svn: 321948
* [CGBuiltin] Handle unsigned mul overflow properly (PR35750)Vedant Kumar2018-01-031-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | r320902 fixed the IRGen for some types of checked multiplications. It did not handle unsigned overflow correctly in the case where the signed operand is negative (PR35750). Eli pointed out that on overflow, the result must be equal to the unique value that is equivalent to the mathematically-correct result modulo two raised to the k power, where k is the number of bits in the result type. This patch fixes the specialized IRGen from r320902 accordingly. Testing: Apart from check-clang, I modified the test harness from r320902 to validate the results of all multiplications -- not just the ones which don't overflow: https://gist.github.com/vedantk/3eb9c88f82e5c32f2e590555b4af5081 llvm.org/PR35750, rdar://34963321 Differential Revision: https://reviews.llvm.org/D41717 llvm-svn: 321771
* Revert "ASan+operator new[]: Fix operator new[] cookie poisoning"Filipe Cabecinhas2018-01-021-9/+1
| | | | | | | | This reverts r321645. I missed a compiler-rt test that needs updating. llvm-svn: 321647
* ASan+operator new[]: Fix operator new[] cookie poisoningFilipe Cabecinhas2018-01-021-1/+9
| | | | | | | | | | | | | | | | | | Summary: The C++ Itanium ABI says: No cookie is required if the new operator being used is ::operator new[](size_t, void*). We should only avoid poisoning the cookie if we're calling this operator, not others. This is dealt with before the call to InitializeArrayCookie. Reviewers: rjmccall, kcc, rsmith Subscribers: cfe-commits Differential Revision: https://reviews.llvm.org/D41301 llvm-svn: 321645
* [x86][icelake][vbmi2]Coby Tayree2017-12-273-2/+910
| | | | | | | | | | | | | | | added vbmi2 feature recognition added intrinsics support for vbmi2 instructions _mm[128,256,512]_mask[z]_compress_epi[16,32] _mm[128,256,512]_mask_compressstoreu_epi[16,32] _mm[128,256,512]_mask[z]_expand_epi[16,32] _mm[128,256,512]_mask[z]_expandloadu_epi[16,32] _mm[128,256,512]_mask[z]_sh[l,r]di_epi[16,32,64] _mm[128,256,512]_mask_sh[l,r]dv_epi[16,32,64] matching a similar work on the backend (D40206) Differential Revision: https://reviews.llvm.org/D41557 llvm-svn: 321487
* [x86][icelake][vnni]Coby Tayree2017-12-273-2/+226
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | added vnni feature recognition added intrinsics support for VNNI instructions _mm256_mask_dpbusd_epi32 _mm256_maskz_dpbusd_epi32 _mm256_dpbusd_epi32 _mm256_mask_dpbusds_epi32 _mm256_maskz_dpbusds_epi32 _mm256_dpbusds_epi32 _mm256_mask_dpwssd_epi32 _mm256_maskz_dpwssd_epi32 _mm256_dpwssd_epi32 _mm256_mask_dpwssds_epi32 _mm256_maskz_dpwssds_epi32 _mm256_dpwssds_epi32 _mm128_mask_dpbusd_epi32 _mm128_maskz_dpbusd_epi32 _mm128_dpbusd_epi32 _mm128_mask_dpbusds_epi32 _mm128_maskz_dpbusds_epi32 _mm128_dpbusds_epi32 _mm128_mask_dpwssd_epi32 _mm128_maskz_dpwssd_epi32 _mm128_dpwssd_epi32 _mm128_mask_dpwssds_epi32 _mm128_maskz_dpwssds_epi32 _mm128_dpwssds_epi32 _mm512_mask_dpbusd_epi32 _mm512_maskz_dpbusd_epi32 _mm512_dpbusd_epi32 _mm512_mask_dpbusds_epi32 _mm512_maskz_dpbusds_epi32 _mm512_dpbusds_epi32 _mm512_mask_dpwssd_epi32 _mm512_maskz_dpwssd_epi32 _mm512_dpwssd_epi32 _mm512_mask_dpwssds_epi32 _mm512_maskz_dpwssds_epi32 _mm512_dpwssds_epi32 matching a similar work on the backend (D40208) Differential Revision: https://reviews.llvm.org/D41558 llvm-svn: 321484
* [x86][icelake][bitalg]Coby Tayree2017-12-273-2/+160
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | added bitalg feature recognition added intrinsics support for bitalg instructions _mm512_popcnt_epi16 _mm512_mask_popcnt_epi16 _mm512_maskz_popcnt_epi16 _mm512_popcnt_epi8 _mm512_mask_popcnt_epi8 _mm512_maskz_popcnt_epi8 _mm512_mask_bitshuffle_epi64_mask _mm512_bitshuffle_epi64_mask _mm256_popcnt_epi16 _mm256_mask_popcnt_epi16 _mm256_maskz_popcnt_epi16 _mm128_popcnt_epi16 _mm128_mask_popcnt_epi16 _mm128_maskz_popcnt_epi16 _mm256_popcnt_epi8 _mm256_mask_popcnt_epi8 _mm256_maskz_popcnt_epi8 _mm128_popcnt_epi8 _mm128_mask_popcnt_epi8 _mm128_maskz_popcnt_epi8 _mm256_mask_bitshuffle_epi32_mask _mm256_bitshuffle_epi32_mask _mm128_mask_bitshuffle_epi16_mask _mm128_bitshuffle_epi16_mask matching a similar work on the backend (D40222) Differential Revision: https://reviews.llvm.org/D41564 llvm-svn: 321483
* [x86][icelake][vpclmulqdq]Coby Tayree2017-12-272-2/+19
| | | | | | | | | | | added vpclmulqdq feature recognition added intrinsics support for vpclmulqdq instructions _mm256_clmulepi64_epi128 _mm512_clmulepi64_epi128 matching a similar work on the backend (D40101) Differential Revision: https://reviews.llvm.org/D41573 llvm-svn: 321480
* [x86][icelake][gfni]Coby Tayree2017-12-272-1/+183
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | added gfni feature recognition added intrinsics support for gfni instructions _mm_gf2p8affineinv_epi64_epi8 _mm_mask_gf2p8affineinv_epi64_epi8 _mm_maskz_gf2p8affineinv_epi64_epi8 _mm256_gf2p8affineinv_epi64_epi8 _mm256_mask_gf2p8affineinv_epi64_epi8 _mm256_maskz_gf2p8affineinv_epi64_epi8 _mm512_gf2p8affineinv_epi64_epi8 _mm512_mask_gf2p8affineinv_epi64_epi8 _mm512_maskz_gf2p8affineinv_epi64_epi8 _mm_gf2p8affine_epi64_epi8 _mm_mask_gf2p8affine_epi64_epi8 _mm_maskz_gf2p8affine_epi64_epi8 _mm256_gf2p8affine_epi64_epi8 _mm256_mask_gf2p8affine_epi64_epi8 _mm256_maskz_gf2p8affine_epi64_epi8 _mm512_gf2p8affine_epi64_epi8 _mm512_mask_gf2p8affine_epi64_epi8 _mm512_maskz_gf2p8affine_epi64_epi8 _mm_gf2p8mul_epi8 _mm_mask_gf2p8mul_epi8 _mm_maskz_gf2p8mul_epi8 _mm256_gf2p8mul_epi8 _mm256_mask_gf2p8mul_epi8 _mm256_maskz_gf2p8mul_epi8 _mm512_gf2p8mul_epi8 _mm512_mask_gf2p8mul_epi8 _mm512_maskz_gf2p8mul_epi8 matching a similar work on the backend (D40373) Differential Revision: https://reviews.llvm.org/D41582 llvm-svn: 321477
* [x86][icelake][vaes]Coby Tayree2017-12-272-3/+58
| | | | | | | | | | | | | | | added vaes feature recognition added intrinsics support for vaes instructions, matching a similar work on the backend (D40078) _mm256_aesenc_epi128 _mm512_aesenc_epi128 _mm256_aesenclast_epi128 _mm512_aesenclast_epi128 _mm256_aesdec_epi128 _mm512_aesdec_epi128 _mm256_aesdeclast_epi128 _mm512_aesdeclast_epi128 llvm-svn: 321474
* [CodeGen] Represent array members in new-format TBAA type descriptorsIvan A. Kosarev2017-12-221-0/+34
| | | | | | | | | | | | | Now that in the new TBAA format we allow access types to be of any object types, including aggregate ones, it becomes critical to specify types of all sub-objects such aggregates comprise as their members. In order to meet this requirement, this patch enables generation of field descriptors for members of array types. Differential Revision: https://reviews.llvm.org/D41399 llvm-svn: 321352
* [CodeGen] Support generation of TBAA info in the new formatIvan A. Kosarev2017-12-221-27/+56
| | | | | | | | | | Now that the MDBuilder helpers generating TBAA type and access descriptors in the new format are in place, we can teach clang to use them when requested. Differential Revision: https://reviews.llvm.org/D41394 llvm-svn: 321351
* Revert "[CodeGen] Fix crash when a function taking transparent union is ↵Volodymyr Sapsai2017-12-212-37/+1
| | | | | | | | | | | | redeclared." This reverts commit r321296. It caused performance regressions FAIL: imp.execution_time FAIL: 2007-01-04-KNR-Args.execution_time FAIL: sse_expandfft.execution_time FAIL: sse_stepfft.execution_time llvm-svn: 321306
* [AArch64] Enable fp16 data type for the Builtin for AArch64 only.Abderrazek Zaafrani2017-12-211-117/+123
| | | | | | Differential Revision: https:://reviews.llvm.org/D41360 llvm-svn: 321301
* [CodeGen] Fix crash when a function taking transparent union is redeclared.Volodymyr Sapsai2017-12-212-1/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When a function taking transparent union is declared as taking one of union members earlier in the translation unit, clang would hit an "Invalid cast" assertion during EmitFunctionProlog. This case corresponds to function f1 in test/CodeGen/transparent-union-redecl.c. We decided to cast i32 to union because after merging function declarations function parameter type becomes int, CGFunctionInfo::ArgInfo type matches with ABIArgInfo type, so we decide it is a trivial case. But these types should also be castable to parameter declaration type which is not the case here. The fix is in checking for the trivial case if ABIArgInfo type matches with parameter declaration type. It exposed inconsistency that we check hasScalarEvaluationKind for different types in EmitParmDecl and EmitFunctionProlog, and comment says they should match. Additional tests in Sema/transparent-union.c capture current behavior and make sure there are no regressions. rdar://problem/34949329 Reviewers: rjmccall, rafael Reviewed By: rjmccall Subscribers: aemerson, cfe-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D41311 llvm-svn: 321296
* [AARch64] Add ARMv8.2-A FP16 vector intrinsicsAbderrazek Zaafrani2017-12-214-355/+1976
| | | | | | | | Putting back the code that was reverted few weeks ago. Differential Revision: https://reviews.llvm.org/D34161 llvm-svn: 321294
* [ubsan] Diagnose noreturn functions which returnVedant Kumar2017-12-211-0/+7
| | | | | | | | | | | | | | | | | | Diagnose 'unreachable' UB when a noreturn function returns. 1. Insert a check at the end of functions marked noreturn. 2. A decl may be marked noreturn in the caller TU, but not marked in the TU where it's defined. To diagnose this scenario, strip away the noreturn attribute on the callee and insert check after calls to it. Testing: check-clang, check-ubsan, check-ubsan-minimal, D40700 rdar://33660464 Differential Revision: https://reviews.llvm.org/D40698 llvm-svn: 321231
* [Complex] Don't use __div?c3 when building with fast-math.Florian Hahn2017-12-201-0/+139
| | | | | | | | | | | | Summary: Plant an inline version of "((ac+bd)/(cc+dd)) + i((bc-ad)/(cc+dd))" instead. Patch by Paul Walker. Reviewed By: hfinkel Differential Revision: https://reviews.llvm.org/D40299 llvm-svn: 321183
* [X86] Use {{.*}} instead of hardcoded %1 in knot test.Martin Bohme2017-12-181-1/+1
| | | | | | | This makes the test more resilient and consistent with the other tests introduced in r320919. llvm-svn: 320971
* [Driver, CodeGen] pass through and apply -fassociative-mathSanjay Patel2017-12-161-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are 2 parts to getting the -fassociative-math command-line flag translated to LLVM FMF: 1. In the driver/frontend, we accept the flag and its 'no' inverse and deal with the interactions with other flags like -ffast-math -fno-signed-zeros -fno-trapping-math. This was mostly already done - we just need to translate the flag as a codegen option. The test file is complicated because there are many potential combinations of flags here. Note that we are matching gcc's behavior that requires 'nsz' and no-trapping-math. 2. In codegen, we map the codegen option to FMF in the IR builder. This is simple code and corresponding test. For the motivating example from PR27372: float foo(float a, float x) { return ((a + x) - x); } $ ./clang -O2 27372.c -S -o - -ffast-math -fno-associative-math -emit-llvm | egrep 'fadd|fsub' %add = fadd nnan ninf nsz arcp contract float %0, %1 %sub = fsub nnan ninf nsz arcp contract float %add, %2 So 'reassoc' is off as expected (and so is the new 'afn' but that's a different patch). This case now works as expected end-to-end although the underlying logic is still wrong: $ ./clang -O2 27372.c -S -o - -ffast-math -fno-associative-math | grep xmm addss %xmm1, %xmm0 subss %xmm1, %xmm0 We're not done because the case where 'reassoc' is set is ignored by optimizer passes. Example: $ ./clang -O2 27372.c -S -o - -fassociative-math -fno-signed-zeros -fno-trapping-math -emit-llvm | grep fadd %add = fadd reassoc float %0, %1 $ ./clang -O2 27372.c -S -o - -fassociative-math -fno-signed-zeros -fno-trapping-math | grep xmm addss %xmm1, %xmm0 subss %xmm1, %xmm0 Differential Revision: https://reviews.llvm.org/D39812 llvm-svn: 320920
* [X86] Implement kand/kandn/kor/kxor/kxnor/knot intrinsics using native IR.Craig Topper2017-12-161-16/+45
| | | | llvm-svn: 320919
* [X86] Add the two files I forgot to commit in r320915.Craig Topper2017-12-161-0/+73
| | | | llvm-svn: 320916
* [CodeGen] Specialize mixed-sign mul-with-overflow (fix PR34920)Vedant Kumar2017-12-161-0/+119
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch introduces a specialized way to lower overflow-checked multiplications with mixed-sign operands. This fixes link failures and ICEs on code like this: void mul(int64_t a, uint64_t b) { int64_t res; __builtin_mul_overflow(a, b, &res); } The generic checked-binop irgen would use a 65-bit multiplication intrinsic here, which requires runtime support for _muloti4 (128-bit multiplication), and therefore fails to link on i386. To get an ICE on x86_64, change the example to use __int128_t / __uint128_t. Adding runtime and backend support for 65-bit or 129-bit checked multiplication on all of our supported targets is infeasible. This patch solves the problem by using simpler, specialized irgen for the mixed-sign case. llvm.org/PR34920, rdar://34963321 Testing: Apart from check-clang, I compared the output from this fairly comprehensive test driver using unpatched & patched clangs: https://gist.github.com/vedantk/3eb9c88f82e5c32f2e590555b4af5081 Differential Revision: https://reviews.llvm.org/D41149 llvm-svn: 320902
* [CodeGen][X86] Implement _InterlockedCompareExchange128 intrinsicReid Kleckner2017-12-141-1/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: InterlockedCompareExchange128 is a bit more complicated than the other InterlockedCompareExchange functions, so it requires a bit more work. It doesn't directly refer to 128bit ints, instead it takes pointers to 64bit ints for Destination and ComparandResult, and exchange is taken as two 64bit ints (high & low). The previous value is written to ComparandResult, and success is returned. This implementation does the following in order to produce a cmpxchg instruction: 1. Cast everything to 128bit ints or int pointers, and glues together the Exchange values 2. Reads from CompareandResult to get the comparand 3. Calls cmpxchg volatile (on X86 this will produce a lock cmpxchg16b instruction) 1. Result 0 (previous value) is written back to ComparandResult 2. Result 1 (success bool) is zext'ed to a uchar and returned Resolves bug https://llvm.org/PR35251 Patch by Colden Cullen! Reviewers: rnk, agutowski Reviewed By: rnk Subscribers: majnemer, cfe-commits Differential Revision: https://reviews.llvm.org/D41032 llvm-svn: 320730
* [Hexagon] Intrinsic support for V62 and V65Krzysztof Parzyszek2017-12-131-1866/+2276
| | | | llvm-svn: 320609
* [Driver][CodeGen] Add -mprefer-vector-width driver option and attribute ↵Craig Topper2017-12-111-0/+14
| | | | | | | | | | | | | | | | during CodeGen. This adds a new command line option -mprefer-vector-width to specify a preferred vector width for the vectorizers. Valid values are 'none' and unsigned integers. The driver will check that it meets those constraints. Specific supported integers will be managed by the targets in the backend. Clang will take the value and add it as a new function attribute during CodeGen. This represents the alternate direction proposed by Sanjay in this RFC: http://lists.llvm.org/pipermail/llvm-dev/2017-November/118734.html The syntax here matches gcc, though gcc treats it as an x86 specific command line argument. gcc only allows values of 128, 256, and 512. I'm not having clang check any values. Differential Revision: https://reviews.llvm.org/D40230 llvm-svn: 320419
* [Hexagon] Remove unsupported vlut intrinsicsKrzysztof Parzyszek2017-12-111-16/+0
| | | | llvm-svn: 320410
* Hardware-assisted AddressSanitizer (clang part).Evgeniy Stepanov2017-12-091-0/+53
| | | | | | | | | | | | | | Summary: Driver, frontend and LLVM codegen for HWASan. A clone of ASan, basically. Reviewers: kcc, pcc, alekseyshl Subscribers: srhines, javed.absar, cfe-commits Differential Revision: https://reviews.llvm.org/D40936 llvm-svn: 320232
* [CodeGen][X86] Fix handling of __fp16 vectors.Akira Hatanaka2017-12-092-35/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit fixes a bug in IRGen where it generates completely broken code for __fp16 vectors on X86. For example when the following code is compiled: half4 hv0, hv1, hv2; // these are vectors of __fp16. void foo221() { hv0 = hv1 + hv2; } clang generates the following IR, in which two i16 vectors are added: @hv1 = common global <4 x i16> zeroinitializer, align 8 @hv2 = common global <4 x i16> zeroinitializer, align 8 @hv0 = common global <4 x i16> zeroinitializer, align 8 define void @foo221() { %0 = load <4 x i16>, <4 x i16>* @hv1, align 8 %1 = load <4 x i16>, <4 x i16>* @hv2, align 8 %add = add <4 x i16> %0, %1 store <4 x i16> %add, <4 x i16>* @hv0, align 8 ret void } To fix the bug, this commit uses the code committed in r314056, which modified clang to promote and truncate __fp16 vectors to and from float vectors in the AST. It also fixes another IRGen bug where a short value is assigned to an __fp16 variable without any integer-to-floating-point conversion, as shown in the following example: __fp16 a; short b; void foo1() { a = b; } @b = common global i16 0, align 2 @a = common global i16 0, align 2 define void @foo1() #0 { %0 = load i16, i16* @b, align 2 store i16 %0, i16* @a, align 2 ret void } rdar://problem/20625184 Differential Revision: https://reviews.llvm.org/D40112 llvm-svn: 320215
* [ubsan] array-bounds: Ignore params with constant sizeVedant Kumar2017-12-081-2/+1
| | | | | | | | | | This is a follow-up to r320128. Eli pointed out that there is some gray area in the language standard about whether the constant size is exact, or a lower bound. https://reviews.llvm.org/D40940 llvm-svn: 320185
* [ubsan] Use pass_object_size info in bounds checksVedant Kumar2017-12-081-0/+69
| | | | | | | | | Teach UBSan's bounds check to opportunistically use pass_object_size information to check array accesses. rdar://33272922 llvm-svn: 320128
* [x86][AVX512] Lowering kunpack intrinsics to LLVM IRJina Nahias2017-12-052-9/+26
| | | | | | | | | This patch, together with a matching llvm patch (https://reviews.llvm.org/D39720), implements the lowering of X86 kunpack intrinsics to IR. Differential Revision: https://reviews.llvm.org/D39719 Change-Id: Id5d3cb394ad33b98be79a6783d1d15569e2b798d llvm-svn: 319777
* Revert "[CodeGen] Add initial support for union members in TBAA"Hal Finkel2017-12-032-108/+6
| | | | | | | | This reverts commit r319413. See PR35503. We can't use "union member" as the access type here like this. llvm-svn: 319629
* [CodeGen] fix mapping from fmod calls to frem instructionSanjay Patel2017-12-022-18/+20
| | | | | | Similar to D40044 and discussed in D40594. llvm-svn: 319619
* [CodeGen] convert math libcalls/builtins to equivalent LLVM intrinsicsSanjay Patel2017-12-015-122/+121
| | | | | | | | | | | | | | | | There are 20 LLVM math intrinsics that correspond to mathlib calls according to the LangRef: http://llvm.org/docs/LangRef.html#standard-c-library-intrinsics We were only converting 3 mathlib calls (sqrt, fma, pow) and 12 builtin calls (ceil, copysign, fabs, floor, fma, fmax, fmin, nearbyint, pow, rint, round, trunc) to their intrinsic-equivalents. This patch pulls the transforms together and handles all 20 cases. The switch is guarded by a check for const-ness to make sure we're not doing the transform if errno could possibly be set by the libcall or builtin. Differential Revision: https://reviews.llvm.org/D40044 llvm-svn: 319593
* [CodeGen] Add initial support for union members in TBAAIvan A. Kosarev2017-11-302-6/+108
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The basic idea behind this patch is that since in strict aliasing mode all accesses to union members require their outermost enclosing union objects to be specified explicitly, then for a couple given accesses to union members of the form p->a.b.c... q->x.y.z... it is known they can only alias if both p and q point to the same union type and offset ranges of members a.b.c... and x.y.z... overlap. Note that the actual types of the members do not matter. Specifically, in this patch we do the following: * Make unions to be valid TBAA base access types. This enables generation of TBAA type descriptors for unions. * Encode union types as structures with a single member of a special "union member" type. Currently we do not encode information about sizes of types, but conceptually such union members are considered to be of the size of the whole union. * Encode accesses to direct and indirect union members, including member arrays, as accesses to these special members. All accesses to members of a union thus get the same offset, which is the offset of the union they are part of. This means the existing LLVM TBAA machinery is able to handle such accesses with no changes. While this is already an improvement comparing to the current situation, that is, representing all union accesses as may-alias ones, there are further changes planned to complete the support for unions. One of them is storing information about access sizes so we can distinct accesses to non-overlapping union members, including accesses to different elements of member arrays. Another change is encoding type sizes in order to make it possible to compute offsets within constant-indexed array elements. These enhancements will be addressed with separate patches. Differential Revision: https://reviews.llvm.org/D39455 llvm-svn: 319413
* [XRay][clang] Introduce -fxray-always-emit-customeventsDean Michael Berris2017-11-301-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: The -fxray-always-emit-customevents flag instructs clang to always emit the LLVM IR for calls to the `__xray_customevent(...)` built-in function. The default behaviour currently respects whether the function has an `[[clang::xray_never_instrument]]` attribute, and thus not lower the appropriate IR code for the custom event built-in. This change allows users calling through to the `__xray_customevent(...)` built-in to always see those calls lowered to the corresponding LLVM IR to lay down instrumentation points for these custom event calls. Using this flag enables us to emit even just the user-provided custom events even while never instrumenting the start/end of the function where they appear. This is useful in cases where "phase markers" using __xray_customevent(...) can have very few instructions, must never be instrumented when entered/exited. Reviewers: rnk, dblaikie, kpw Subscribers: cfe-commits Differential Revision: https://reviews.llvm.org/D40601 llvm-svn: 319388
* Reland "Fix vtable not receiving hidden visibility when using push(visibility)"Jake Ehrlich2017-11-291-0/+20
| | | | | | | | | | I had to reland this change in order to make the test work on windows This change should resolve https://bugs.llvm.org/show_bug.cgi?id=35022 https://reviews.llvm.org/D39627 llvm-svn: 319269
* Control-Flow Enforcement Technology - Shadow Stack and Indirect Branch ↵Oren Ben Simhon2017-11-262-2/+99
| | | | | | | | | | | | | | | | | | Tracking support (Clang side) Shadow stack solution introduces a new stack for return addresses only. The stack has a Shadow Stack Pointer (SSP) that points to the last address to which we expect to return. If we return to a different address an exception is triggered. This patch includes shadow stack intrinsics as well as the corresponding CET header. It includes CET clang flags for shadow stack and Indirect Branch Tracking. For more information, please see the following: https://software.intel.com/sites/default/files/managed/4d/2a/control-flow-enforcement-technology-preview.pdf Differential Revision: https://reviews.llvm.org/D40224 Change-Id: I79ad0925a028bbc94c8ecad75f6daa2f214171f1 llvm-svn: 318995
* [X86] Use separate builtins for fma4 scalar intrinsics. Use negations to ↵Craig Topper2017-11-252-14/+30
| | | | | | | | | | remove some of the scalar fma3 builtins. fma4 instructions zero the upper bits of the xmm register. fma3 instructions leave the bits unmodified. This requires separate builtins for the different semantics. While we're cleaning up the scalar builtins this also removes the fma3 fmsub/fnmadd/fnmsub builtins by using negates in the header file. llvm-svn: 318985
* Revert "[CodeGen] Fix vtable not receiving hidden visibility when using ↵Petr Hosek2017-11-221-21/+0
| | | | | | | | push(visibility)" This reverts commit r318853: tests are failing on Windows bots llvm-svn: 318866
* [CodeGen] Fix vtable not receiving hidden visibility when using push(visibility)Petr Hosek2017-11-221-0/+21
| | | | | | | | | | This change should resolve https://bugs.llvm.org/show_bug.cgi?id=35022 Patch by Jake Ehrlich Differential Revision: https://reviews.llvm.org/D39627 llvm-svn: 318853
* Avoid unecessary opsize byte in segment move to memoryNirav Dave2017-11-211-6/+6
| | | | | | | | | | | | | | | | | Segment moves to memory are always 16-bit. Remove invalid 32 and 64 bit variants. Recommiting with missing clang inline assembly test change. Fixes PR34478. Reviewers: rnk, craig.topper Subscribers: llvm-commits, hiraditya Differential Revision: https://reviews.llvm.org/D39847 llvm-svn: 318797
* Add -finstrument-function-entry-bare flagHans Wennborg2017-11-211-0/+13
| | | | | | | | | | | | | | | | | This is an instrumentation flag that's similar to -finstrument-functions, but it only inserts calls on function entry, the calls are inserted post-inlining, and they don't take any arugments. This is intended for users who want to instrument function entry with minimal overhead. (-pg would be another alternative, but forces frame pointer emission and affects link flags, so is probably best left alone to be used for generating gcov data.) Differential revision: https://reviews.llvm.org/D40276 llvm-svn: 318785
* [x86][inline-asm] allow recognition of MPX regs inside ms inline-asm blobCoby Tayree2017-11-211-0/+11
| | | | | | Differential Revision: https://reviews.llvm.org/D38445 llvm-svn: 318739
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