summaryrefslogtreecommitdiffstats
path: root/clang/test/CodeGen
Commit message (Collapse)AuthorAgeFilesLines
* Revert "Make FP_CONTRACT ON the default."Manuel Klimek2015-11-173-189/+13
| | | | | | | | | This reverts commit r253269. This leads to assert / segfault triggering on the following reduced example: float foo(float U, float base, float cell) { return (U = 2 * base) - cell; } llvm-svn: 253337
* Make FP_CONTRACT ON the default.Stephen Canon2015-11-163-13/+189
| | | | | | Differential Revision: D14200 llvm-svn: 253269
* When producing error messages for always_inline functions with theEric Christopher2015-11-161-0/+9
| | | | | | | | | | target attribute, don't include "negative" subtarget features in the list of required features. Builtins are positive by default so don't need this change, but we pull the default list of features from the command line and so need to make sure that we only include features that are turned on for code generation in our error. llvm-svn: 253242
* [ARM,AArch64] Fix __rev16l and __rev16ll intrinsicsOliver Stannard2015-11-161-10/+36
| | | | | | | | | | | | | | | | | | | | These two intrinsics are defined in arm_acle.h. __rev16l needs to rotate by 16 bits, bit it was actually rotating by 2 bits. For AArch64, where long is 64 bits, this would still be wrong. __rev16ll was incorrect, it reversed the bytes in each 32-bit word, rather than each 16-bit halfword. The correct implementation is to apply __rev16 to the top and bottom words of the 64-bit value. For AArch32 targets, these get compiled down to the hardware rev16 instruction at -O1 and above. For AArch64 targets, the 64-bit ones get compiled to two 32-bit rev16 instructions, because there is not currently a pattern for the 64-bit rev16 instruction. Differential Revision: http://reviews.llvm.org/D14609 llvm-svn: 253211
* [X86][MMX] Added MMX IR + assembly codegen builtin tests for some missing ↵Simon Pilgrim2015-11-151-14/+81
| | | | | | cvt intrinsics llvm-svn: 253169
* [X86][MMX] Sorted MMX IR + assembly codegen builtin testsSimon Pilgrim2015-11-141-367/+374
| | | | | | Makes it easier to track what tests are missing.... llvm-svn: 253131
* [X86][MMX] Added MMX IR + assembly codegen builtin testsSimon Pilgrim2015-11-141-196/+358
| | | | | | Improved tests as discussed in PR24580 llvm-svn: 253130
* Add support for the always_inline + target feature diagnostic to printEric Christopher2015-11-142-2/+2
| | | | | | | out the first missing target feature that's required and reword the diagnostic accordingly. llvm-svn: 253121
* Make some tests LLVM-optimization agnostic and remove some others that were ↵David Blaikie2015-11-142-35/+16
| | | | | | | | | | | | | | | | beyond value/repair Several of these tests (the two deleted, and the one removal edit) were relying on the optimizer to collapse things to test some frontend feature. The tests were really old and features seemed amply covered by other parts of the test suite, so I just removed them. If anyone thinks they're valuable enough to keep/fix, we can play around with that, for sure. (inspired by r252872) llvm-svn: 253114
* Add support for function attribute 'disable_tail_calls'.Akira Hatanaka2015-11-131-5/+13
| | | | | | | | | | | | | | | | | | | | | | The ``disable_tail_calls`` attribute instructs the backend to not perform tail call optimization inside the marked function. For example, int callee(int); int foo(int a) __attribute__((disable_tail_calls)) { return callee(a); // This call is not tail-call optimized. } Note that this attribute is different from 'not_tail_called', which prevents tail-call optimization to the marked function. rdar://problem/8973573 Differential Revision: http://reviews.llvm.org/D12547 llvm-svn: 252986
* Correct atomic libcall support for __atomic_*_fetch builtins.James Y Knight2015-11-121-6/+13
| | | | | | | | | | | | | | In r244063, I had caused these builtins to call the same-named library functions, __atomic_*_fetch_SIZE. However, this was incorrect: while those functions are in fact supported by GCC's libatomic, they're not documented by the spec (and gcc doesn't ever call them). Instead, you're /supposed/ to call the __atomic_fetch_* builtins and then redo the operation inline to return the final value. Differential Revision: http://reviews.llvm.org/D14385 llvm-svn: 252920
* Update clang regression tests for 'norecurse'James Molloy2015-11-122-4/+4
| | | | | | FunctionAttrs has just been taught how to infer 'norecurse'. Update clang tests for LLVM r252871. llvm-svn: 252872
* Provide a frontend based error for always_inline functions that requireEric Christopher2015-11-124-98/+17
| | | | | | | | | | | | | | | target features that the caller function doesn't provide. This matches the existing backend failure to inline functions that don't have matching target features - and diagnoses earlier in the case of always_inline. Fix up a few test cases that were, in fact, invalid if you tried to generate code from the backend with the specified target features and add a couple of tests to illustrate what's going on. This should fix PR25246. llvm-svn: 252834
* [Lit Test] Updated 26 Lit tests to be C++11 compatible.Charles Li2015-11-111-1/+1
| | | | | | | Expected diagnostics have been expanded to vary by C++ dialect. RUN line has also been expanded to: default, C++98/03 and C++11. llvm-svn: 252785
* [X86] Add 'pause' builtin that's already in llvm and use it instead of ↵Craig Topper2015-11-111-0/+6
| | | | | | inline assembly to implement _mm_pause. llvm-svn: 252712
* [X86] Use __builtin_ia32_paddq and __builtin_ia32_psubq to implement a ↵Craig Topper2015-11-111-0/+18
| | | | | | couple intrinsics that were supposed to operate on MMX registers. Otherwise we end up operating on GPRs. Throw in a test for _mm_mul_su32 while I was there. llvm-svn: 252711
* Reorder the check strings in test case following r252692.Akira Hatanaka2015-11-111-1/+1
| | | | | | rdar://problem/19836465 llvm-svn: 252693
* [WebAssembly] Change long double to be quadruple-precision floating point.Dan Gohman2015-11-101-2/+2
| | | | llvm-svn: 252646
* Atomics: support __c11_* calls on _Atomic struct types.Tim Northover2015-11-094-24/+236
| | | | | | | | | | | | | When a struct's size is not a power of 2, the corresponding _Atomic() type is promoted to the nearest. We already correctly handled normal C++ expressions of this form, but direct calls to the __c11_atomic_whatever builtins ended up performing dodgy operations on the smaller non-atomic types (e.g. memcpy too much). Later optimisations removed this as undefined behaviour. This patch converts EmitAtomicExpr to allocate its temporaries at the full atomic width, sidestepping the issue. llvm-svn: 252507
* [EABI] Add Clang support for -meabi flagRenato Golin2015-11-091-0/+20
| | | | | | | | | | | | | | The -meabi flag to control LLVM EABI version. Without '-meabi' or with '-meabi default' imply LLVM triple default. With '-meabi gnu' sets EABI GNU. With '-meabi 4' or '-meabi 5' set EABI version 4 and 5 respectively. A similar patch was introduced in LLVM. Patch by Vinicius Tinti. llvm-svn: 252463
* Use regex in test case.Akira Hatanaka2015-11-071-1/+1
| | | | | | This is a follow-up to r252369. llvm-svn: 252376
* Add support for function attribute 'not_tail_called'.Akira Hatanaka2015-11-061-0/+33
| | | | | | | | | | | | | | | | | | | | | | This attribute is used to prevent tail-call optimizations to the marked function. For example, in the following piece of code, foo1 will not be tail-call optimized: int __attribute__((not_tail_called)) foo1(int); int foo2(int a) { return foo1(a); // Tail-call optimization is not performed. } The attribute has effect only on statically bound calls. It has no effect on indirect calls. Also, virtual functions and objective-c methods cannot be marked as 'not_tail_called'. rdar://problem/22667622 Differential Revision: http://reviews.llvm.org/D12922 llvm-svn: 252369
* CodeGen: Update for debug info API change.Peter Collingbourne2015-11-051-1/+1
| | | | | | Differential Revision: http://reviews.llvm.org/D14266 llvm-svn: 252220
* [WebAssembly] Update wasm builtin functions to match spec changes.Dan Gohman2015-11-051-9/+3
| | | | | | | The page_size operator has been removed from the spec, and the resize_memory operator has been changed to grow_memory. llvm-svn: 252201
* [x86] Additional small fix for MCU psABI supportAndrey Bokhanko2015-11-051-1/+1
| | | | | | | | This patch fixes one more thing in MCU psABI support: LongDoubleWidth should be set to 64. Differential Revision: http://reviews.llvm.org/D14285 llvm-svn: 252156
* Fix va_arg on watchOS.Tim Northover2015-11-021-6/+11
| | | | | | As in other contexts, alignments can go up to 16 bytes in a va_list. llvm-svn: 251821
* [x86] Front-end part of MCU psABI supportAndrey Bokhanko2015-11-021-0/+4
| | | | | | | | | | | This patch implements two things in front-end for MCU psABI support: 1) "long double type is the same as double." 2) "New predefined C/C++ pre-processor symbols: iamcu and iamcu__. Differential Revision: http://reviews.llvm.org/D14205 llvm-svn: 251786
* ARMv7k: implement ABI changes for watchOS from standard iOS.Tim Northover2015-10-302-0/+92
| | | | llvm-svn: 251710
* Update debug-info-scope test to remove "FIXME", which is fixed in r251689Dehao Chen2015-10-301-4/+0
| | | | llvm-svn: 251691
* Add support for __builtin_{add,sub,mul}_overflow.John McCall2015-10-291-0/+165
| | | | | | Patch by David Grayson! llvm-svn: 251651
* Fix the calling convention of Mingw64 long double valuesReid Kleckner2015-10-281-9/+38
| | | | | | | | | | GCC uses the x87DoubleExtended model for long doubles, and passes them indirectly by address through function calls. Also replace the existing mingw-long-double assembly emitting test with an IR-level test. llvm-svn: 251567
* Allow linking multiple bitcode files.Artem Belevich2015-10-271-2/+13
| | | | | | | | | | | | | | | | | | Linking options for particular file depend on the option that specifies the file. Currently there are two: * -mlink-bitcode-file links in complete content of the specified file. * -mlink-cuda-bitcode links in only the symbols needed by current TU. Linked symbols are internalized. This bitcode linking mode is used to link device-specific bitcode provided by CUDA. Files are linked in order they are specified on command line. -mlink-cuda-bitcode replaces -fcuda-uses-libdevice flag. Differential Revision: http://reviews.llvm.org/D13913 llvm-svn: 251427
* [ms-inline-asm] Test case for alignment directive change in LLVM r251418Reid Kleckner2015-10-271-0/+30
| | | | llvm-svn: 251419
* Handle target builtin options that are all required rather thanEric Christopher2015-10-271-0/+13
| | | | | | | | | | | | | | | | | only one of a group of possibilities. This changes the syntax in the builtin files to represent: , as the and operator | as the or operator The former syntax matches how the backend tablegen files represent multiple subtarget features being required. Updated the builtin and intrinsic headers accordingly for the new syntax. llvm-svn: 251388
* [X86] Mark inregs correctly for MCU psABIMichael Kuperstein2015-10-251-0/+58
| | | | | | | | | The MCU psABI calling convention is somewhat, but not quite, like -mregparm 3. In particular, the rules involving structs are different. Differential Revision: http://reviews.llvm.org/D13978 llvm-svn: 251224
* [ARM] Renaming +t2dsp feature into +dsp, as discussed on llvm-devArtyom Skrobov2015-10-231-11/+11
| | | | llvm-svn: 251124
* Disable trigraph and escaped newline expansion on all types of raw string ↵Craig Topper2015-10-221-0/+24
| | | | | | literals not just ASCII type. llvm-svn: 251025
* [x86] Fix maskload/store intrinsic definitions in avxintrin.hAndrea Di Biagio2015-10-201-8/+8
| | | | | | | | | | | | | According to the Intel documentation, the mask operand of a maskload and maskstore intrinsics is always a vector of packed integer/long integer values. This patch introduces the following two changes: 1. It fixes the avx maskload/store intrinsic definitions in avxintrin.h. 2. It changes BuiltinsX86.def to match the correct gcc definitions for avx maskload/store (see D13861 for more details). Differential Revision: http://reviews.llvm.org/D13861 llvm-svn: 250816
* [X86] Enable soft float ABI for x86Michael Kuperstein2015-10-191-0/+6
| | | | | | | | | The Intel MCU psABI requires floating-point values to be passed in-reg. This makes the x86-32 ABI code respect "-mfloat-abi soft" and generate float inreg arguments. Differential Revision: http://reviews.llvm.org/D13554 llvm-svn: 250689
* [X86] Add fxsr feature name for fxsave/fxrestore builtins.Craig Topper2015-10-162-8/+8
| | | | llvm-svn: 250498
* Make __builtin_object_size more conservativeGeorge Burgess IV2015-10-162-12/+172
| | | | | | | | | | | | | | | | | | | | | | | | | | | r246877 made __builtin_object_size substantially more aggressive with unknown bases if Type=1 or Type=3, which causes issues when we encounter code like this: struct Foo { int a; char str[1]; }; const char str[] = "Hello, World!"; struct Foo *f = (struct Foo *)malloc(sizeof(*f) + strlen(str)); strcpy(&f->str, str); __builtin_object_size(&f->str, 1) would hand back 1, which is technically correct given the type of Foo, but the type of Foo lies to us about how many bytes are available in this case. This patch adds support for this "writing off the end" idiom -- we now answer conservatively when we're given the address of the very last member in a struct. Differential Revision: http://reviews.llvm.org/D12169 llvm-svn: 250488
* [Sema] Fix address-of + enable_if overloading logicGeorge Burgess IV2015-10-161-0/+31
| | | | | | | | | | | | | | | | | Previously, our logic when taking the address of an overloaded function would not consider enable_if attributes, so long as all of the enable_if conditions on a given candidate were true. So, two functions with identical signatures (one with enable_if attributes, the other without), would be considered equally good overloads. If we were calling the function instead of taking its address, then the function with enable_if attributes would be preferred. This patch makes us prefer the candidate with enable_if regardless of if we're calling or taking the address of an overloaded function. Differential Revision: http://reviews.llvm.org/D13795 llvm-svn: 250486
* Mark this test as requiring and x86 registered target.Eric Christopher2015-10-161-0/+1
| | | | llvm-svn: 250475
* Add an error when calling a builtin that requires features that don'tEric Christopher2015-10-153-0/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | match the feature set of the function that they're being called from. This ensures that we can effectively diagnose some[1] code that would instead ICE in the backend with a failure to select message. Example: __m128d foo(__m128d a, __m128d b) { return __builtin_ia32_addsubps(b, a); } compiled for normal x86_64 via: clang -target x86_64-linux-gnu -c would fail to compile in the back end because the normal subtarget features for x86_64 only include sse2 and the builtin requires sse3. [1] We're still not erroring on: __m128i bar(__m128i const *p) { return _mm_lddqu_si128(p); } where we should fail and error on an always_inline function being inlined into a function that doesn't support the subtarget features required. llvm-svn: 250473
* The target-feature command line option doesn't take a comma delimitedEric Christopher2015-10-152-12/+12
| | | | | | string, so split them into multiple options. llvm-svn: 250449
* Add the minimum target features that these tests depend upon.Eric Christopher2015-10-152-3/+3
| | | | llvm-svn: 250448
* [X86] Add command line switches for xsave/xsaveopt/xsavec/xsaves. Macro ↵Craig Topper2015-10-151-3/+3
| | | | | | defines for the same. And add the flags to correct CPU names. llvm-svn: 250368
* Canonicalize some of the x86 builtin tests and either remove or commentEric Christopher2015-10-1431-56/+90
| | | | | | about optimization options. llvm-svn: 250271
* Remove the optimization option from this test as it is unnecessaryEric Christopher2015-10-141-1/+1
| | | | | | and front end tests should avoid this if possible. llvm-svn: 250270
* Move the adc-builtins test to the pattern of the other builtinsEric Christopher2015-10-131-1/+3
| | | | | | tests by predefining _MM_MALLOC_H rather than use -ffreestanding. llvm-svn: 250203
OpenPOWER on IntegriCloud