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* [CLANG][AVX512][BUILTIN] Add builtin vcomi{ss|sd}Michael Zuckerman2016-03-071-0/+10
| | | | | | Differential Revision: http://reviews.llvm.org/D17919 llvm-svn: 262847
* [ms-inline-asm][AVX512] Add ability to use k registers in MS inline asm + ↵Marina Yatsina2016-03-072-1/+11
| | | | | | | | | | | | | | | | | | | | | | fix bag with curly braces Until now curly braces could only be used in MS inline assembly to mark block start/end. All curly braces were removed completely at a very early stage. This approach caused bugs like: "m{o}v eax, ebx" turned into "mov eax, ebx" without any error. In addition, AVX-512 added special operands (e.g., k registers), which are also surrounded by curly braces that mark them as such. Now, we need to keep the curly braces and identify at a later stage if they are marking block start/end (if so, ignore them), or surrounding special AVX-512 operands (if so, parse them as such). This patch fixes the bug described above and enables the use of AVX-512 special operands. This commit is the the clang part of the patch. The clang part of the review is: http://reviews.llvm.org/D17766 The llvm part of the review is: http://reviews.llvm.org/D17767 Differential Revision: http://reviews.llvm.org/D17766 llvm-svn: 262842
* Implement __builtin_eh_return_data_regno for SPARC and SPARC64.Joerg Sonnenberger2016-03-071-0/+10
| | | | llvm-svn: 262838
* [CLANG][AVX512][BUILTIN] Adding new feature flag headed files and new ↵Michael Zuckerman2016-03-072-0/+86
| | | | | | | | BUILTIN vpermi2varq{i|t}{128|256|512}{mask|maskz} Differential Revision: http://reviews.llvm.org/D17917 llvm-svn: 262834
* Resolved Bug 26414.Amjad Aboud2016-03-071-0/+8
| | | | | | | | | https://llvm.org/bugs/show_bug.cgi?id=26414 Since interrupt handler must be returned with iret, tail call can't be used. Differential Revision: http://reviews.llvm.org/D17853 llvm-svn: 262830
* [CLANG][AVX512][BUILTIN] Adding new feature flag header file and new builtin ↵Michael Zuckerman2016-03-072-0/+119
| | | | | | | | vpmadd52{h|l}uq{128|256|512}{mask|maskz} Differential Revision: http://reviews.llvm.org/D17915 llvm-svn: 262820
* [CLANG][AVX512][BUILTIN] Adding vpmultishiftqb{128|256|512}Michael Zuckerman2016-03-072-1/+62
| | | | | | Differential Revision: http://reviews.llvm.org/D17914 llvm-svn: 262817
* [X86] Pass __m64 types via SSE registers for GCC compatibilityDavid Majnemer2016-03-042-28/+54
| | | | | | | | | | For compatibility with GCC, classify __m64 as SSE. However, clang is a platform compiler for certain targets; retain our old behavior on those targets: classify __m64 as integer. This fixes PR26832. llvm-svn: 262688
* [CLANG][AVX512][BUILTIN] movddup{128|256|512}Michael Zuckerman2016-03-032-0/+42
| | | | | | Differential Revision: http://reviews.llvm.org/D17826 llvm-svn: 262617
* [OpenCL] Apply missing restrictions for Blocks in OpenCL v2.0Anastasia Stulova2016-03-031-3/+4
| | | | | | | | | | | | | | Applying the following restrictions for block types in OpenCL (v2.0 s6.12.5): - __block storage class is disallowed - every block declaration must be const qualified and initialized - a block can't be used as a return type of a function - a blocks can't be used to declare a structure or union field - extern speficier is disallowed Corrected image and sampler types diagnostics with struct and unions. Review: http://reviews.llvm.org/D16928 llvm-svn: 262616
* Fixing a checkfile error in avx512vlbw-builtins.cMichael Zuckerman2016-03-031-8/+8
| | | | | | Differential Revision: http://reviews.llvm.org/D17814 llvm-svn: 262611
* [CLANG][AVX512][BUILTIN] movdqu{qi|hi} {128|256|512}Michael Zuckerman2016-03-032-0/+70
| | | | | | Differential Revision: http://reviews.llvm.org/D17814 llvm-svn: 262609
* [CLANG][AVX512][BUILTIN] movdqa{32|64}{load|store|}{128|256|512}Michael Zuckerman2016-03-032-0/+120
| | | | | | Differential Revision: http://reviews.llvm.org/D17812 llvm-svn: 262598
* [Clang][AVX512][BUILTIN] Adding PSRL{W|WI}{128|256|512}Michael Zuckerman2016-03-031-0/+37
| | | | | | Differential Revision: http://reviews.llvm.org/D17754 llvm-svn: 262593
* [PGO] Change profile use cc1 option to handle IR level profilesRong Xu2016-03-023-0/+13
| | | | | | | | | | | | | | | | | | This patch changes cc1 option for PGO profile use from -fprofile-instr-use=<path> to -fprofile-instrument-use-path=<path>. -fprofile-instr-use=<path> is now a driver only option. In addition to decouple the cc1 option from the driver level option, this patch also enables IR level profile use. cc1 option handling now reads the profile header and sets CodeGenOpt ProfileUse (valid values are {None, Clang, LLVM} -- this is a common enum for -fprofile-instrument={}, for the profile instrumentation), and invoke the pipeline to enable the respective PGO use pass. Reviewers: silvas, davidxl Differential Revision: http://reviews.llvm.org/D17737 llvm-svn: 262515
* [CLANG] [AVX512] [BUILTIN] Adding PSRA{W|WI}{128|256|512}.Michael Zuckerman2016-03-021-0/+37
| | | | | | Differential Revision: http://reviews.llvm.org/D17706 llvm-svn: 262481
* [CLANG] [AVX512] [BUILTIN] Adding PSRAVMichael Zuckerman2016-03-022-0/+78
| | | | | | Differential Revision: http://reviews.llvm.org/D17699 llvm-svn: 262471
* Updated SSE41 builtin tests to more closely match the llvm fast-isel ↵Simon Pilgrim2016-03-011-40/+50
| | | | | | equivalent tests llvm-svn: 262418
* [MSVC Compat] Correctly handle finallys nested within finallysDavid Majnemer2016-03-011-0/+25
| | | | | | | | | We'd lose track of the parent CodeGenFunction, leading us to get confused with regard to which function a nested finally belonged to. Differential Revision: http://reviews.llvm.org/D17752 llvm-svn: 262379
* [PPC64][VSX] Add short, char, and bool data type for vec_vsx_ld and ↵Kit Barton2016-03-011-0/+118
| | | | | | | | | | | | | | | | | | | | vec_vsx_st intrinsics Issue: https://llvm.org/bugs/show_bug.cgi?id=26720 Fix compile error when building ffmpeg for PowerPC64LE because of some vec_vsx_ld/vec_vsx_st intrinsics are not supported by current clang. New added intrinsics: (vector) {signed|unsigned} {short|char} vec_vsx_ld: (total: 8) bool vec_vsx_ld: (total: 1) (vector) {signed|unsigned} {short|char} vec_vsx_st: (total: 8) bool vec_vsx_st: (total: 1) Total: 18 intrinsics Phabricator: http://reviews.llvm.org/D17637 llvm-svn: 262359
* [CLANG][AVX512][BUILTIN] Adding PSRL{DI|QI}{128|256|512} builtinMichael Zuckerman2016-03-012-0/+131
| | | | | | Differential Revision: http://reviews.llvm.org/D17714 llvm-svn: 262355
* [CLANG][AVX512][BUILTIN] Adding PSRLV builtin Michael Zuckerman2016-03-012-0/+66
| | | | | | Differential Revision: http://reviews.llvm.org/D17718 llvm-svn: 262326
* [CLANG] [AVX512] [BUILTIN] Adding PSRA{Q|D|QI|DI}{128|256|512} builtinMichael Zuckerman2016-03-011-0/+37
| | | | | | Differential Revision: http://reviews.llvm.org/D17693 llvm-svn: 262321
* [PGO] clang cc1 option change to enable IR level instrumentationRong Xu2016-02-291-0/+9
| | | | | | | | | | | This patch expands cc1 option -fprofile-instrument= with a new value: -fprofile-instrument=llvm which enables IR level PGO instrumentation. Reviewers: davidxl, silvas Differential Revision: http://reviews.llvm.org/D17622 llvm-svn: 262239
* [X86] Disabling avx512f should also disable avx512vbmi and avx512ifma. ↵Craig Topper2016-02-291-1/+1
| | | | | | Enabling avx512vbmi or avx512ifma should enable avx512f. Add command line switches and header defines for avx512ifma and avx512vbmi. llvm-svn: 262201
* [CLANG] [AVX512] [BUILTIN] Adding PSLL{V|W|Wi}{128|256|512} builtinMichael Zuckerman2016-02-283-1/+189
| | | | | | Differential Revision: http://reviews.llvm.org/D17685 llvm-svn: 262177
* Add __builtin_canonicalizeMatt Arsenault2016-02-271-0/+7
| | | | llvm-svn: 262122
* Fix Clang tests that used CHECK-NEXT-NOT and CHECK-DAG-NOT.Paul Robinson2016-02-262-4/+4
| | | | | | | | FileCheck actually doesn't support combo suffixes. Differential Revision: http://reviews.llvm.org/D17589 llvm-svn: 262052
* Fix typo in test/CodeGen/object-size.c CHECK line.Bob Wilson2016-02-241-1/+1
| | | | llvm-svn: 261762
* [CLANG] [AVX512] [BUILTIN] Adding PSHUF{L|H}W{128|256|512} builtin to clang .Michael Zuckerman2016-02-241-0/+38
| | | | | | Differential Revision: http://reviews.llvm.org/D17539 llvm-svn: 261755
* Default vaarg lowering should support indirect struct types.James Y Knight2016-02-242-2/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fixes PR11517 for SPARC. On most targets, clang lowers va_arg itself, eschewing the use of the llvm vaarg instruction. This is necessary (at least for now) as the type argument to the vaarg instruction cannot represent all the ABI information that is needed to support complex calling conventions. However, on targets with a simpler varrags ABIs, the LLVM instruction can work just fine, and clang can simply lower to it. Unfortunately, even on such targets, vaarg with a struct argument would fail, because the default lowering to vaarg was naive: it didn't take into account the ABI attribute computed by classifyArgumentType. In particular, for the DefaultABIInfo, structs are supposed to be passed indirectly and so llvm's vaarg instruction should be emitted with a pointer argument. Now, vaarg instruction emission is able to use computed ABIArgInfo for the provided argument type, which allows the default ABI support to work for structs too. I haven't touched the EmitVAArg implementation for PPC32_SVR4 or XCore, although I believe both are now redundant, and could be switched over to use the default implementation as well. Differential Revision: http://reviews.llvm.org/D16154 llvm-svn: 261717
* [CLANG] [AVX512] [BUILTIN] Adding prorv{d|q}{128|256|512} builtin to clang Michael Zuckerman2016-02-232-0/+108
| | | | | | Differential Revision: http://reviews.llvm.org/D17512 llvm-svn: 261641
* [CLANG] [AVX512] [BUILTIN] Adding pro{lv|r}{d|q}{128|256|512} builtin to clangMichael Zuckerman2016-02-232-0/+219
| | | | | | Differential Revision: http://reviews.llvm.org/D17506 llvm-svn: 261635
* [ms-inline-asm] Fixing bug in single asm statement supportMarina Yatsina2016-02-231-2/+11
| | | | | | | | | | | | | | Fixing a crash caused by trying to merge a single-line asm statement with an asm block that follows it, e.g: asm int 4 asm { int 5 } Now, only adjacent single-line asm statements that are not surrounded by braces will be merged into one asm call. Differential Revision: http://reviews.llvm.org/D17496 llvm-svn: 261618
* [WebAssembly] Lower va_arg in clang.Dan Gohman2016-02-221-0/+103
| | | | | | | This uses the general emitVoidPtrVAArg lowering logic for everything, since this supports all types, and we don't have any special requirements. llvm-svn: 261557
* Add support for Android Vector calling convention for AArch64Nirav Dave2016-02-221-0/+22
| | | | | | | | | | | | | | | | | | | | | | | This modification applies the following Android commit when we have an Android environment. This is the sole non-renderscript in the Android repo commit 9212d4fb30a3ca2f4ee966dd2748c35573d9682c Author: Tim Murray <timmurray@google.com> Date: Fri Aug 15 16:00:15 2014 -0700 Update vector calling convention for AArch64. bug 16846318 Change-Id: I3cfd167758b4bd634d8480ee6ba6bb55d61f82a7 Reviewers: srhines, jyknight Subscribers: mcrosier, aemerson, rengolin, tberghammer, danalbert, srhines Differential Revision: http://reviews.llvm.org/D17448 llvm-svn: 261533
* [CLANG] [AVX512] [BUILTIN] Adding prol{d|q|w}{128|256|512} builtin to clang .Michael Zuckerman2016-02-222-2/+111
| | | | | | Differential Revision: http://reviews.llvm.org/D16985 llvm-svn: 261516
* [CLANG] [AVX512] [BUILTIN] Adding pmovzx{b|d|w}{w|d|q}{128|256|512} builtin ↵Michael Zuckerman2016-02-214-0/+370
| | | | | | | | to clang Differential Revision: http://reviews.llvm.org/D16961 llvm-svn: 261471
* Remove -fnew-ms-ehDavid Majnemer2016-02-202-5/+5
| | | | | | This flag no longer controls any behavior inside of clang. llvm-svn: 261423
* Fix handling of vaargs on PPC32 when going from regsave to overflow.Roman Divacky2016-02-201-0/+2
| | | | | | | | | | | | It can happen that when we only have 1 more register left in the regsave area we need to store a value bigger than 1 register and therefore we go to the overflow area. In this case we have to leave the last slot in the regsave area unused and keep using overflow area. Do this by storing a limit value to the used register counter in the overflow block. Issue diagnosed by and solution tested by Mark Millard! llvm-svn: 261422
* Add test.JF Bastien2016-02-191-0/+36
| | | | llvm-svn: 261310
* Missed a spot in r261251, also ignore attributes on all pointer parametersKrzysztof Parzyszek2016-02-181-2/+2
| | | | llvm-svn: 261253
* Make test less prone to attribute changesKrzysztof Parzyszek2016-02-181-3/+3
| | | | llvm-svn: 261251
* [CLANG] [AVX512] [BUILTIN] Adding pmovsx{b|d|w}{w|d|q}{128|256|512} builtin ↵Michael Zuckerman2016-02-184-0/+252
| | | | | | | | to clang Differential Revision: http://reviews.llvm.org/D16955 llvm-svn: 261196
* [Hexagon] Specify vector alignment in DataLayout stringKrzysztof Parzyszek2016-02-121-1/+1
| | | | | | | | | | | The DataLayout can calculate alignment of vectors based on the alignment of the element type and the number of elements. In fact, it is the product of these two values. The problem is that for vectors of N x i1, this will return the alignment of N bytes, since the alignment of i1 is 8 bits. The vector types of vNi1 should be aligned to N bits instead. Provide explicit alignment for HVX vectors to avoid such complications. llvm-svn: 260680
* [PR26550] Use a different TBAA root for C++ vs C.Manman Ren2016-02-113-3/+3
| | | | | | | | | | | | | | | | | | | This commit changes the root from "Simple C/C++ TBAA" to "Simple C++ TBAA" for C++. The problem is that the type name in the TBAA nodes is generated differently for C vs C++. If we link an IR file for C with an IR file for C++, since they have the same root and the type names are different, accesses to the two type nodes will be considered no-alias, even though the two type nodes are from the same type in a header file. The fix is to use different roots for C and C++. Types from C will be treated conservatively in respect to types from C++. Follow-up commits will change the C root to "Simple C TBAA" plus some mangling change for C types to make it a little more aggresive. llvm-svn: 260567
* [MCU] Fix assertion failure on function returning empty union.Denis Zobnin2016-02-111-0/+70
| | | | | | | | Treat empty struct/union in return type as void for MCU ABI. PR26438. Differential Revision: http://reviews.llvm.org/D16808 llvm-svn: 260510
* [X86] Fix stack alignment for MCU target (Clang part), by Anton Nadolskiy.Andrey Turetskiy2016-02-101-0/+38
| | | | | | | | This patch fixes stack alignments for MCU (should be aligned to 4 bytes). Differential Revision: http://reviews.llvm.org/D15647 llvm-svn: 260376
* Fix assertion "Chunk.Kind == DeclaratorChunk::Function" with attributed type.Denis Zobnin2016-02-101-0/+11
| | | | | | | | | | This patch is to upgrade FunctionTypeUnwrapper for correct processing of AttributedType. Fixes PR25786. Patch by Alexander Makarov. Differential Revision: http://reviews.llvm.org/D15373 llvm-svn: 260373
* Basic: mark TLS as supported on Windows on ARMSaleem Abdulrasool2016-02-041-0/+5
| | | | | | | LLVM can now lower TLS access as per the MS ABI on ARM. This enables the generation of TLS access for Windows on ARM. llvm-svn: 259751
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