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* Implement the no_split_stack attribute.Peter Collingbourne2014-05-191-3/+11
| | | | | | | | | This is a GNU attribute that allows split stacks to be turned off on a per-function basis. Differential Revision: http://reviews.llvm.org/D3817 llvm-svn: 209167
* Non-allocatable Global Named RegisterRenato Golin2014-05-191-0/+26
| | | | | | | | | | | | | This patch implements global named registers in Clang, lowering to the just created intrinsics in LLVM (@llvm.read/write_register). A new type of LValue had to be created (Register), which just adds support to carry the metadata node containing the name of the register. Two new methods to emit loads and stores interoperate with another to emit the named metadata node. No guarantees are being made and only non-allocatable global variable named registers are being supported. Local named register support is unchanged. llvm-svn: 209149
* ARM: PCS non-compliance when struct is padded to avoid register/stack split, ↵Oliver Stannard2014-05-191-3/+8
| | | | | | | | | | and requires internal padding When we were padding a struct to avoid splitting it between registers and the stack, we were throwing away the type which the argument should be coerced to. llvm-svn: 209122
* Update for llvm api change.Rafael Espindola2014-05-162-3/+3
| | | | | | | | | | Now that llvm cannot represent alias cycles, we have to diagnose erros just before trying to close the cycle. This degrades the errors a bit. The real solution is what it was before: if we want to provide good errors for these cases, we have to be able to find a clang level decl given a mangled name and produce the error from Sema. llvm-svn: 209008
* Allow dllimport/dllexport on inline functions and adjust the linkage.Hans Wennborg2014-05-151-0/+8
| | | | | | | | This is a step towards handling these attributes on classes (PR11170). Differential Revision: http://reviews.llvm.org/D3772 llvm-svn: 208925
* ARM64: update tests now that we print "mov" & "mvn".Tim Northover2014-05-153-29/+29
| | | | llvm-svn: 208875
* AArch64: update test after LLVM CodeGen changeTim Northover2014-05-151-1/+1
| | | | llvm-svn: 208868
* [ARM64]Fix the bug right shift uint64_t by 64 generates incorrect result.Hao Liu2014-05-141-2/+24
| | | | llvm-svn: 208761
* DebugInfo: Avoid creating DILexicalScopeFiles when the filename in the ↵David Blaikie2014-05-141-0/+20
| | | | | | | | | | | | | | | | | | | current scope has not changed. This looks like the right way for this check to work, but there is another semi-obvious bug, I would think: why is CurLoc not zero'd out between functions? The possibility for it to bleed between them seems problematic. (& indeed I caused tests to fail when I fixed this a different way, by setting CurLoc to SourceLocation() and the end of EmitFunctionEnd... ) The changes to debug-info-blocks.m are due to a mismatch between the source manager's file naming and CGDebugInfo's default handling when no -main-file-name is specified. This actually reveals somewhat of a bug in the debug info when using source files from standard in, too. See the comment in CGDebugInfo::CreateCompileUnit for more details. llvm-svn: 208742
* Fixed a few tests and moved a comment to its proper placeFilipe Cabecinhas2014-05-131-5/+8
| | | | llvm-svn: 208665
* Patched clang to emit x86 blends as shufflevectors.Filipe Cabecinhas2014-05-133-5/+41
| | | | | | | | | | | | | | | | | Summary: Most of the clang header patch by Simon Pilgrim @ SCEE. Also fixed (or added) clang tests for these intrinsics. LLVM tests to make sure we get the blend instruction out of these shufflevectors are at http://reviews.llvm.org/D3600 Reviewers: eli.friedman, craig.topper, rafael Subscribers: cfe-commits Differential Revision: http://reviews.llvm.org/D3601 llvm-svn: 208664
* CodeGen: support dll{ex,im}port on WoASaleem Abdulrasool2014-05-111-0/+25
| | | | | | | | | | Add ARM support for dllexport and dllimport attributes. This is a relatively conservative change. The alternative is to entirely drop the architecture requirement. The dllimport and dllexport attributes are not restricted to any architecture, simply to platforms that support this attribute (currently Windows). llvm-svn: 208486
* Reapply r208417 (olista01 'ARM: HFAs must be passed in consecutive ↵James Molloy2014-05-092-26/+26
| | | | | | registers'). Bots are now pacified. llvm-svn: 208425
* Revert r208417 (olista01 'ARM: HFAs must be passed in consecutive ↵James Molloy2014-05-092-26/+26
| | | | | | registers'). This is a followon commit from r208413 which broke the LLVM bots. llvm-svn: 208422
* ARM: HFAs must be passed in consecutive registersOliver Stannard2014-05-092-26/+26
| | | | | | | This is the clang counterpart to 208413, which ensures that Homogeneous Floating-point Aggregates are passed in consecutive registers on ARM. llvm-svn: 208417
* When doing int<->ptr coercion for big-endian, calculate the shift amount ↵James Molloy2014-05-071-0/+9
| | | | | | | | | | | | | | | correctly. Previously we calculated the shift amount based upon DataLayout::getTypeAllocSizeInBits. This will only work for legal types - types such as i24 that are created as part of structs for bitfields will return "32" from that function. Change to using getTypeSizeInBits. It turns out that AArch64 didn't run across this problem because it always returned [1 x i64] as the type for a bitfield, whereas ARM64 returns i64 so goes down this (better, but wrong) codepath. llvm-svn: 208231
* Re-satisfy the bots. Due to a de-sync between my clang and LLVM trees, I ↵James Molloy2014-05-071-1/+1
| | | | | | didn't notice that the generated BE alignment register is now unnamed and is not called '%align_be'. llvm-svn: 208217
* [ARM64-BE] Correctly deal with single element HFAs in varargs.James Molloy2014-05-071-0/+13
| | | | | | | Just because the first "if" didn't fire, doesn't mean we can not have an HFA in the "else" clause. llvm-svn: 208216
* ARM: Fix assertion caused by passing bitfield struct using ↵Oliver Stannard2014-05-071-2/+6
| | | | | | | | | | | | ABIArgInfo::getExpandWithPadding In cases where a struct must, according to the AAPCS, not be split between general purpose and floating point registers, we use ABIArgInfo::getExpandWithPadding to add the padding arguments. However, ExpandWithPadding does not work if the struct contains bitfields, so we instead must use ABIArgInfo::getDirect. llvm-svn: 208185
* Reapply: DebugInfo: Emit the definition of enums when the definition ↵David Blaikie2014-05-061-0/+10
| | | | | | | | | | | | | | | | | | | preceeds the declaration and initial use. Reverting r208106 to reapply r208065 with a fix for the regression. The issue was that the enum tried to be built even if the declaration hadn't been constructed for debug info - presenting problems for enum templates and typedefs of enums with names for linkage purposes. Original commit message: This regressed a little further 208055 though it was already a little broken. While the requiresCompleteType optimization should be implemented here. Future (possibly near future) work. llvm-svn: 208114
* Revert "DebugInfo: Emit the definition of enums when the definition preceeds ↵David Blaikie2014-05-061-10/+0
| | | | | | | | | | | the declaration and initial use." This is breaking the compiler-rt build. Reverting while I investigate/fix. This reverts commit r208065. llvm-svn: 208106
* DebugInfo: Emit the definition of enums when the definition preceeds the ↵David Blaikie2014-05-061-0/+10
| | | | | | | | | | | | declaration and initial use. This regressed a little further 208055 though it was already a little broken. While the requiresCompleteType optimization should be implemented here. Future (possibly near future) work. llvm-svn: 208065
* Support field references to struct names and c++11 aliases from inline asm.Nico Weber2014-05-061-1/+31
| | | | | | This is in addition to the existing support for typedefs. llvm-svn: 208053
* Fix pr19653.Rafael Espindola2014-05-051-0/+5
| | | | | | Warn if an alias requests a section other than the aliasee section. llvm-svn: 207997
* Fix some typosAlp Toker2014-05-051-2/+2
| | | | llvm-svn: 207994
* CodeGen: complete ARM ACLE hint 8.4 supportSaleem Abdulrasool2014-05-041-0/+24
| | | | | | | Add support for the remaining hints from the ACLE. Although __dbg is listed as a hint, it is handled different, so it is not covered by this change. llvm-svn: 207930
* XCore target: fix bug in dereferencing null pointer.Robert Lytton2014-05-021-0/+27
| | | | | | Also add basic cpp ABI tests where they differ from C ABI output. llvm-svn: 207834
* XCore target: Add TypeString meta data to IR output.Robert Lytton2014-05-021-0/+169
| | | | | | | This includes the addition of the virtual function: TargetCodeGenInfo::EmitTargetMD() llvm-svn: 207832
* CodeGen: rename __builtin_arm_sevl to __sevlSaleem Abdulrasool2014-05-021-1/+1
| | | | | | | ACLE adds the __sevl() extension. Rename the hint from a custom name to the ACLE specified name. llvm-svn: 207829
* [ARM64] Port remaining relevant AArch64 clang tests over to ARM64Bradley Smith2014-04-301-0/+2
| | | | llvm-svn: 207632
* [ARM64]Fix a bug cannot select UQSHL/SQSHL with constant i64 shift amount.Hao Liu2014-04-281-0/+12
| | | | llvm-svn: 207401
* CodeGen: add __yield intrinsic for ARMSaleem Abdulrasool2014-04-251-0/+10
| | | | | | | | | The __yield intrinsic generates a hint instruction to indicate that the thread is not performing any useful operations at the moment. This is for compatibility with MSVC, although, the intrinsic is also part of the ACLE, and is enabled globally as a result. llvm-svn: 207275
* Print detailed vector type information on diagnostics.Benjamin Kramer2014-04-251-3/+3
| | | | | | | | | | | | | | | | | | | | | | We never aka vector types because our attributed syntax for it is less comprehensible than the typedefs. This leaves the user in the dark when the typedef isn't named that well. Example: v2s v; v4f w; w = v; The naming in this cases isn't even that bad, but the error we give is useless without looking up the actual typedefs. t.c:6:5: error: assigning to 'v4f' from incompatible type 'v2s' Now: t.c:6:5: error: assigning to 'v4f' (vector of 4 'float' values) from incompatible type 'v2s' (vector of 2 'int' values) We do this for all diagnostics that print a vector type. llvm-svn: 207267
* CodeGen: replace use of @llvm.arm.sevl with @llvm.arm.hintSaleem Abdulrasool2014-04-251-1/+1
| | | | | | | Use the new generic @llvm.arm.hint hint intrinsic rather than the specialised @llvm.arm.sevl hint instruction. llvm-svn: 207243
* [X86] Add Clang support for intrinsics __rdtsc and __rdtscp.Andrea Di Biagio2014-04-241-0/+3
| | | | | | | | | | | | | | This patch: 1. Adds a definition for two new GCCBuiltins in BuiltinsX86.def: __builtin_ia32_rdtsc; __builtin_ia32_rdtscp; 2. Replaces the already existing definition of intrinsic __rdtsc in ia32intrin.h with a simple call to the new GCC builtin __builtin_ia32_rdtsc. 3. Adds a definition for the new intrinsic __rdtscp in ia32intrin.h llvm-svn: 207132
* [mips] Support 128-bit int in N32 ABI by overriding TargetInfo::hasInt128Type()Daniel Sanders2014-04-242-0/+105
| | | | | | | | | | | | | | Summary: The condition in the base class is rather strange. It says a target has the 128-bit integer type if the size of a pointer is >= 64-bits. N32 has 32-bit pointers but 64-bit integers. I'm a bit reluctant to change this for all targets so this patch makes the method virtual and overrides it for MIPS64. Reviewers: atanasyan Reviewed By: atanasyan Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D3472 llvm-svn: 207121
* AArch64: update tests to new way of printing NEON lists.Tim Northover2014-04-243-65/+65
| | | | llvm-svn: 207117
* Fix test to not depend on llvm optimizations.Michael J. Spencer2014-04-241-4/+4
| | | | llvm-svn: 207062
* [ARM64] Enable more CodeGen tests for ARM64. The crypto and neon intrinsics ↵James Molloy2014-04-232-15/+20
| | | | | | tests needed changing slightly due to the naming differences between AArch64 and ARM64. llvm-svn: 206964
* [ARM64] Change inline assembly constraints to be more lax, to match the ↵James Molloy2014-04-231-0/+1
| | | | | | | | behaviour of Clang/AArch64 and GCC. GCC allows sub-64bit values to use the 'r' register constraint. llvm-svn: 206963
* [ARM64] Enable the test aarch64-type-sizes.c for ARM64 BE.James Molloy2014-04-231-0/+1
| | | | | | This completes the port of r203918 (cpirker "AArch64_be specific clang target settings") to ARM64. llvm-svn: 206962
* [ARM64] Add a missed case label for arm64_be, and enable the aarch64-varargs ↵James Molloy2014-04-231-0/+1
| | | | | | | | test for arm64_be. This ensures that r203917 (cpirker "AArch64_be varargs processing for ARM ABI") is ported to ARM64. llvm-svn: 206961
* ARM64: update NEON test to improved backend codegenTim Northover2014-04-221-2/+2
| | | | llvm-svn: 206890
* ARM64: Do not expand variadic HFA/HVA arguments with the Darwin ABI.Bob Wilson2014-04-211-0/+6
| | | | | | | | | | | Unlike the standard AAPCS64 ABI, variadic arguments are always passed on the stack with the Darwin ABI, and this was not being considered when deciding whether to expand HFA/HVA arguments in a call. An HFA argument with a "float" base type was being expanded into separate "float" arguments, each of which was then extended to a double, resulting in a serious mismatch from what is expected by the va_arg implementation. <rdar://problem/15777067> llvm-svn: 206729
* ARM64: make sure the caller is expected to extend in AAPCS.Tim Northover2014-04-181-0/+7
| | | | | | | This is one of those DarwinPCS differences. It'd been caught in arguments, but not return values. llvm-svn: 206594
* ARM64: make sure HFAs on the stack get properly aligned.Tim Northover2014-04-182-3/+15
| | | | | | Another AAPCS bug, part of PR19432. llvm-svn: 206580
* BackendUtil: Pass through -mdisable-tail-callsDuncan P. N. Exon Smith2014-04-181-0/+16
| | | | | | | | | | | | | | | The frontend option -fno-optimize-sibling-calls resolves to -cc1's -mdisable-tail-calls, which is passed to the TargetMachine in the backend. PassManagerBuilder was adding the -tailcallelim pass anyway. Use a new DisableTailCalls option in PassManagerBuilder to disable tail calls harder. Requires the matching commit in LLVM that adds DisableTailCalls. <rdar://problem/16050591> llvm-svn: 206543
* ARM64: remove holes from *all* HFAs on the stack.Tim Northover2014-04-171-0/+9
| | | | | | | | | | My first attempt to make sure HFAs were contiguous was in the block dealing with padding registers, which meant it only triggered on the first stack-based HFA. This should extend it to the rest as well. Another part of PR19432. llvm-svn: 206456
* [ARM64] Allow the disabling of NEON and crypto instructions. Update tests to ↵James Molloy2014-04-1648-52/+52
| | | | | | pass -target-feature +neon. llvm-svn: 206394
* Re-enable several builtins in non-gnu modes.Evgeniy Stepanov2014-04-161-0/+11
| | | | | | | | | This is a partial revert of 183015. By not recognizing things like _setjmp we lose (returns_twice) attribute on them, which leads to incorrect code generation. Fixes PR16138. llvm-svn: 206362
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