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* Fix a tranche of comment, test and doc typosAlp Toker2013-12-051-2/+2
| | | | llvm-svn: 196510
* Correct hyphenations in comments and assert messagesAlp Toker2013-12-051-1/+1
| | | | | | | This patch tries to avoid unrelated changes other than fixing a few hyphen-related ambiguities in nearby lines. llvm-svn: 196466
* [ms-cxxabi] Construct and destroy call arguments in the correct orderReid Kleckner2013-12-041-2/+2
| | | | | | | | | | | | | | | | | | | Summary: MSVC destroys arguments in the callee from left to right. Because C++ objects have to be destroyed in the reverse order of construction, Clang has to construct arguments from right to left and destroy arguments from left to right. This patch fixes the ordering by reversing the order of evaluation of all call arguments under the MS C++ ABI. Fixes PR18035. Reviewers: rsmith Differential Revision: http://llvm-reviews.chandlerc.com/D2275 llvm-svn: 196402
* [SystemZ] Fix handling of pass-by-pointer argumentsRichard Sandiford2013-12-041-1/+1
| | | | | | | | | | | | | | | | I'd misunderstood getIndirect() to mean that the argument should be passed as a pointer at the ABI level, with the ByVal argument choosing caller-copy semantics over no-caller-copy (callee-copy-on-write) semantics. But getIndirect(x) actually means that x is passed by pointer at the IR level but (at least on all other targets I looked at) directly at the ABI level. getIndirect(x, false) selects a pointer to a caller-made copy, which is what SystemZ was aiming for. This fixes a miscompilation of c-index-test. Structure arguments were being passed by pointer, but no copy was being made, so a write in the callee stomped over a caller's local variable. llvm-svn: 196370
* [AArch64 NEON] Add ACLE intrinsic vceqz_f64.Kevin Qin2013-12-041-0/+6
| | | | llvm-svn: 196361
* [AArch64 NEON] Add missing compare intrinsics.Kevin Qin2013-12-042-1/+163
| | | | llvm-svn: 196359
* clang/test: REQUIRES: s/x86-64-registered-target/x86-registered-target/NAKAMURA Takumi2013-12-045-5/+5
| | | | llvm-svn: 196350
* clang/test: REQUIRES: s/ppc{32|64}-registered-target/powerpc-registered-target/NAKAMURA Takumi2013-12-0415-15/+15
| | | | llvm-svn: 196349
* clang/test/CodeGen/builtins-nvptx.c: Prune "REQUIRES: ↵NAKAMURA Takumi2013-12-041-1/+0
| | | | | | nvptx64-registered-target". "nvptx" should imply it. llvm-svn: 196348
* [AArch64]Add missing floating point convert, round and misc intrinsics.Hao Liu2013-12-031-0/+168
| | | | | | E.g. int64x1_t vcvt_s64_f64(float64x1_t a) -> FCVTZS Dd, Dn llvm-svn: 196211
* AArch64: add missing ACLE intrinsics mapping to general arithmetic operation ↵Hao Liu2013-12-031-0/+90
| | | | | | | | from VFP instructions. E.g. float64x1_t vadd_f64(float64x1_t a, float64x1_t b) -> FADD Dd, Dn, Dm. llvm-svn: 196209
* Patch by Ana Pazos.Jiangning Liu2013-12-031-4/+3
| | | | | | Fixed vcopy_laneq_f64 intrinsic implementation. llvm-svn: 196206
* revert r196152. Hao Liu2013-12-032-80/+2
| | | | | | | | | | | | | | This is a duplicate implementation. E.g. this patch defines: float64_t vabd_f64(float64_t a, float64_t b) But there is already a similar intrinsic "vabdd_f64" with the same types. Also, this intrinsic will be conflicted to the vector type intrinsic as following(Which is implemented by me and will be committed to trunk): float64x1_t vabd_f64(float64x1_t a, float64x1_t b). Two functions shouldn't have a same name in arm_neon.h. According to ARM ACLE document, such vabd_f64 with float64_t is not existing. So I revert this commit. llvm-svn: 196205
* AArch64: Add missing scalar pair intrinsics.Hao Liu2013-12-031-0/+97
| | | | | | E.g. "float32_t vaddv_f32(float32x2_t a)" to be matched into "faddp s0, v1.2s". llvm-svn: 196199
* Add some missing AArch64 Neon intrinsics like vuqadd_s64 and friends.Jiangning Liu2013-12-031-0/+36
| | | | llvm-svn: 196191
* Add some missing AArch64 Neon intrinsics like vmull_high_n_s16 and friends.Jiangning Liu2013-12-031-0/+149
| | | | llvm-svn: 196189
* [AArch64] Implemented vcopy_lane patterns using scalar DUP instruction.Chad Rosier2013-12-021-0/+53
| | | | | | Patch by Ana Pazos! llvm-svn: 196153
* [AArch64] Add missing NEON scalar floating-point to integer convert ACLEs.Chad Rosier2013-12-022-2/+80
| | | | llvm-svn: 196152
* Fix the problem that the range check for scalar narrow shift is too wide.Hao Liu2013-11-291-36/+36
| | | | | | E.g. the immediate value of vshrns_n_s16 is [1,16], which should be [1,8]. llvm-svn: 195942
* Add missing intrinsic function vbsl_f64 for AArch64 NEON.Jiangning Liu2013-11-291-0/+6
| | | | llvm-svn: 195940
* Add missing intrinsic function vcombine_f64 for AArch64 NEON.Jiangning Liu2013-11-291-0/+91
| | | | llvm-svn: 195937
* Fix the AArch64 NEON bug exposed by checking constant integer argument range ↵Jiangning Liu2013-11-271-192/+924
| | | | | | of ACLE intrinsics. llvm-svn: 195844
* [AArch64] Add support for NEON scalar floating-point absolute difference.Chad Rosier2013-11-271-0/+12
| | | | llvm-svn: 195804
* [AArch64] Add support for NEON scalar floating-point to integer convertChad Rosier2013-11-261-0/+133
| | | | | | instructions. llvm-svn: 195789
* Debug Info: add a "Debug Info Version" module flag to output the current debugManman Ren2013-11-221-0/+8
| | | | | | | | info version number. Will error out when modules have different version numbers. llvm-svn: 195495
* Revert r193994 and part of r193995Justin Bogner2013-11-221-8/+0
| | | | | | | | | | | | | Not long ago I made the CodeGen of for loops simplify the condition at -O0 in the same way we do for if and conditionals. Unfortunately this ties how loops and simple conditions work together too tightly, which makes features such as instrumentation based PGO awkward. Ultimately, we should find a more general way to simplify the logic in a given condition, but for now we'll just avoid using EmitBranchOnBool for loops, like we already do for while and do loops. llvm-svn: 195438
* Deleting three tests that are redundant with ↵Artyom Skrobov2013-11-223-15/+0
| | | | | | test/Preprocessor/arm-target-features.c and test/Driver/arm-cortex-cpus.c llvm-svn: 195430
* For AArch64, intrinsic vget_low_xxx can be optimized away.Jiangning Liu2013-11-221-42/+42
| | | | llvm-svn: 195409
* Implemented Neon scalar vdup_lane intrinsics.Ana Pazos2013-11-211-0/+173
| | | | | | Fixed scalar dup alias and added test case. llvm-svn: 195329
* Implemented Neon scalar by element intrinsics.Ana Pazos2013-11-211-11/+135
| | | | | | | Intrinsics implemented: vqdmull_lane, vqdmulh_lane, vqrdmulh_lane, vqdmlal_lane, vqdmlsl_lane scalar Neon intrinsics. llvm-svn: 195326
* [NVPTX] Update ABI handlingJustin Holewinski2013-11-201-0/+17
| | | | | | For PTX, we want the target to handle struct returns directly. llvm-svn: 195268
* Add a mangler entry point for TBAA rather than using RTTI directlyReid Kleckner2013-11-191-0/+22
| | | | | | | | | | | | | | | | | | | | Summary: RTTI is not yet implemented for the Microsoft C++ ABI and isn't expected soon. We could easily add the mangling, but the error is what prevents us from silently miscompiling code that expects RTTI. Instead, add a new mangleTypeName entry point that simply forwards to mangleName or mangleType to produce a string that isn't part of the ABI. Itanium can continue to use RTTI names to avoid unecessary test breakage. This also seems like the right design. The fact that TBAA names happen to be RTTI names is now an implementation detail of the mangler, rather than part of TBAA. Differential Revision: http://llvm-reviews.chandlerc.com/D2153 llvm-svn: 195168
* Implement AArch64 neon instructions class SIMD lsone and SIMD lone-post.Hao Liu2013-11-191-0/+2047
| | | | llvm-svn: 195079
* Implement AArch64 SISD intrinsics for vget_high and vget_low.Jiangning Liu2013-11-191-0/+176
| | | | llvm-svn: 195073
* Add predicate for AArch64 crypto instructions.Jiangning Liu2013-11-191-1/+4
| | | | llvm-svn: 195069
* Implement the newly added AArch64 ACLE functions for ld1/st1 with 2/3/4 vectors.Hao Liu2013-11-181-0/+1120
| | | | | | The functions are like: vst1_s8_x2 ... llvm-svn: 194991
* Implement vreinterpret ACLE functions in Clang.Hao Liu2013-11-171-0/+2184
| | | | llvm-svn: 194954
* Implemented aarch64 Neon scalar vmulx_lane intrinsicsAna Pazos2013-11-152-0/+146
| | | | | | | | | | | | | | Implemented aarch64 Neon scalar vfma_lane intrinsics Implemented aarch64 Neon scalar vfms_lane intrinsics Implemented legacy vmul_n_f64, vmul_lane_f64, vmul_laneq_f64 intrinsics (v1f64 parameter type) using Neon scalar instructions. Implemented legacy vfma_lane_f64, vfms_lane_f64, vfma_laneq_f64, vfms_laneq_f64 intrinsics (v1f64 parameter type) using Neon scalar instructions. llvm-svn: 194889
* These ACLE tests no longer need to cast the return value.Chad Rosier2013-11-151-8/+8
| | | | llvm-svn: 194854
* [AArch64] Add support for legacy AArch32 NEON scalar shift right by immediateChad Rosier2013-11-141-0/+24
| | | | | | and accumulate instructions. llvm-svn: 194732
* Remove a test failure.Kevin Qin2013-11-141-4/+0
| | | | llvm-svn: 194678
* Add test case for AArch64 NEON poly64 intrinsic.Kevin Qin2013-11-141-0/+287
| | | | llvm-svn: 194674
* Add test cases for AArch64 NEON instruction set misc.Kevin Qin2013-11-141-0/+1951
| | | | llvm-svn: 194672
* Implement AArch64 NEON instruction set AdvSIMD (table).Jiangning Liu2013-11-141-0/+463
| | | | llvm-svn: 194649
* -fms-extensions: Recognize _alloca as an alias for the alloca builtinReid Kleckner2013-11-131-0/+9
| | | | | | Differential Revision: http://llvm-reviews.chandlerc.com/D1989 llvm-svn: 194617
* Only provide MS builtins when -fms-extensions is onReid Kleckner2013-11-131-1/+1
| | | | | | | | | | | We already have builtins that are only available in GNU mode, so this mirrors that. Reviewers: rsmith Differential Revision: http://llvm-reviews.chandlerc.com/D2128 llvm-svn: 194615
* [AArch64] Tests for legacy AArch32 NEON scalar shift by immediate instructions.Chad Rosier2013-11-131-0/+77
| | | | | | | A number of non-overloaded intrinsics have been replaced by thier overloaded counterparts. llvm-svn: 194599
* add intrinsics: __builtin_arm_{dmb,dsb} for ARMWeiming Zhao2013-11-121-1/+5
| | | | llvm-svn: 194513
* [mips][msa] Enable inlinse assembly for MSA.Daniel Sanders2013-11-122-0/+41
| | | | | | | | | | | | | | Like GCC, this re-uses the 'f' constraint and a new 'w' print-modifier: asm ("ldi.w %w0, 1", "=f"(result)); Unlike GCC, the 'w' print-modifer is not _required_ to produce the intended output. This is a consequence of differences in the internal handling of the registers in each compiler. To be source-compatible between the compilers, users must use the 'w' print-modifier. MSA registers (including control registers) are supported in clobber lists. llvm-svn: 194476
* [mips] Added fpu register tests to tests/CodeGen/mips-clobber-reg.cDaniel Sanders2013-11-121-0/+34
| | | | llvm-svn: 194474
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