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* [WebAssembly] Update wasm builtin functions to match spec changes.Dan Gohman2015-11-051-9/+3
| | | | | | | The page_size operator has been removed from the spec, and the resize_memory operator has been changed to grow_memory. llvm-svn: 252201
* [x86] Additional small fix for MCU psABI supportAndrey Bokhanko2015-11-051-1/+1
| | | | | | | | This patch fixes one more thing in MCU psABI support: LongDoubleWidth should be set to 64. Differential Revision: http://reviews.llvm.org/D14285 llvm-svn: 252156
* Fix va_arg on watchOS.Tim Northover2015-11-021-6/+11
| | | | | | As in other contexts, alignments can go up to 16 bytes in a va_list. llvm-svn: 251821
* [x86] Front-end part of MCU psABI supportAndrey Bokhanko2015-11-021-0/+4
| | | | | | | | | | | This patch implements two things in front-end for MCU psABI support: 1) "long double type is the same as double." 2) "New predefined C/C++ pre-processor symbols: iamcu and iamcu__. Differential Revision: http://reviews.llvm.org/D14205 llvm-svn: 251786
* ARMv7k: implement ABI changes for watchOS from standard iOS.Tim Northover2015-10-302-0/+92
| | | | llvm-svn: 251710
* Update debug-info-scope test to remove "FIXME", which is fixed in r251689Dehao Chen2015-10-301-4/+0
| | | | llvm-svn: 251691
* Add support for __builtin_{add,sub,mul}_overflow.John McCall2015-10-291-0/+165
| | | | | | Patch by David Grayson! llvm-svn: 251651
* Fix the calling convention of Mingw64 long double valuesReid Kleckner2015-10-281-9/+38
| | | | | | | | | | GCC uses the x87DoubleExtended model for long doubles, and passes them indirectly by address through function calls. Also replace the existing mingw-long-double assembly emitting test with an IR-level test. llvm-svn: 251567
* Allow linking multiple bitcode files.Artem Belevich2015-10-271-2/+13
| | | | | | | | | | | | | | | | | | Linking options for particular file depend on the option that specifies the file. Currently there are two: * -mlink-bitcode-file links in complete content of the specified file. * -mlink-cuda-bitcode links in only the symbols needed by current TU. Linked symbols are internalized. This bitcode linking mode is used to link device-specific bitcode provided by CUDA. Files are linked in order they are specified on command line. -mlink-cuda-bitcode replaces -fcuda-uses-libdevice flag. Differential Revision: http://reviews.llvm.org/D13913 llvm-svn: 251427
* [ms-inline-asm] Test case for alignment directive change in LLVM r251418Reid Kleckner2015-10-271-0/+30
| | | | llvm-svn: 251419
* Handle target builtin options that are all required rather thanEric Christopher2015-10-271-0/+13
| | | | | | | | | | | | | | | | | only one of a group of possibilities. This changes the syntax in the builtin files to represent: , as the and operator | as the or operator The former syntax matches how the backend tablegen files represent multiple subtarget features being required. Updated the builtin and intrinsic headers accordingly for the new syntax. llvm-svn: 251388
* [X86] Mark inregs correctly for MCU psABIMichael Kuperstein2015-10-251-0/+58
| | | | | | | | | The MCU psABI calling convention is somewhat, but not quite, like -mregparm 3. In particular, the rules involving structs are different. Differential Revision: http://reviews.llvm.org/D13978 llvm-svn: 251224
* [ARM] Renaming +t2dsp feature into +dsp, as discussed on llvm-devArtyom Skrobov2015-10-231-11/+11
| | | | llvm-svn: 251124
* Disable trigraph and escaped newline expansion on all types of raw string ↵Craig Topper2015-10-221-0/+24
| | | | | | literals not just ASCII type. llvm-svn: 251025
* [x86] Fix maskload/store intrinsic definitions in avxintrin.hAndrea Di Biagio2015-10-201-8/+8
| | | | | | | | | | | | | According to the Intel documentation, the mask operand of a maskload and maskstore intrinsics is always a vector of packed integer/long integer values. This patch introduces the following two changes: 1. It fixes the avx maskload/store intrinsic definitions in avxintrin.h. 2. It changes BuiltinsX86.def to match the correct gcc definitions for avx maskload/store (see D13861 for more details). Differential Revision: http://reviews.llvm.org/D13861 llvm-svn: 250816
* [X86] Enable soft float ABI for x86Michael Kuperstein2015-10-191-0/+6
| | | | | | | | | The Intel MCU psABI requires floating-point values to be passed in-reg. This makes the x86-32 ABI code respect "-mfloat-abi soft" and generate float inreg arguments. Differential Revision: http://reviews.llvm.org/D13554 llvm-svn: 250689
* [X86] Add fxsr feature name for fxsave/fxrestore builtins.Craig Topper2015-10-162-8/+8
| | | | llvm-svn: 250498
* Make __builtin_object_size more conservativeGeorge Burgess IV2015-10-162-12/+172
| | | | | | | | | | | | | | | | | | | | | | | | | | | r246877 made __builtin_object_size substantially more aggressive with unknown bases if Type=1 or Type=3, which causes issues when we encounter code like this: struct Foo { int a; char str[1]; }; const char str[] = "Hello, World!"; struct Foo *f = (struct Foo *)malloc(sizeof(*f) + strlen(str)); strcpy(&f->str, str); __builtin_object_size(&f->str, 1) would hand back 1, which is technically correct given the type of Foo, but the type of Foo lies to us about how many bytes are available in this case. This patch adds support for this "writing off the end" idiom -- we now answer conservatively when we're given the address of the very last member in a struct. Differential Revision: http://reviews.llvm.org/D12169 llvm-svn: 250488
* [Sema] Fix address-of + enable_if overloading logicGeorge Burgess IV2015-10-161-0/+31
| | | | | | | | | | | | | | | | | Previously, our logic when taking the address of an overloaded function would not consider enable_if attributes, so long as all of the enable_if conditions on a given candidate were true. So, two functions with identical signatures (one with enable_if attributes, the other without), would be considered equally good overloads. If we were calling the function instead of taking its address, then the function with enable_if attributes would be preferred. This patch makes us prefer the candidate with enable_if regardless of if we're calling or taking the address of an overloaded function. Differential Revision: http://reviews.llvm.org/D13795 llvm-svn: 250486
* Mark this test as requiring and x86 registered target.Eric Christopher2015-10-161-0/+1
| | | | llvm-svn: 250475
* Add an error when calling a builtin that requires features that don'tEric Christopher2015-10-153-0/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | match the feature set of the function that they're being called from. This ensures that we can effectively diagnose some[1] code that would instead ICE in the backend with a failure to select message. Example: __m128d foo(__m128d a, __m128d b) { return __builtin_ia32_addsubps(b, a); } compiled for normal x86_64 via: clang -target x86_64-linux-gnu -c would fail to compile in the back end because the normal subtarget features for x86_64 only include sse2 and the builtin requires sse3. [1] We're still not erroring on: __m128i bar(__m128i const *p) { return _mm_lddqu_si128(p); } where we should fail and error on an always_inline function being inlined into a function that doesn't support the subtarget features required. llvm-svn: 250473
* The target-feature command line option doesn't take a comma delimitedEric Christopher2015-10-152-12/+12
| | | | | | string, so split them into multiple options. llvm-svn: 250449
* Add the minimum target features that these tests depend upon.Eric Christopher2015-10-152-3/+3
| | | | llvm-svn: 250448
* [X86] Add command line switches for xsave/xsaveopt/xsavec/xsaves. Macro ↵Craig Topper2015-10-151-3/+3
| | | | | | defines for the same. And add the flags to correct CPU names. llvm-svn: 250368
* Canonicalize some of the x86 builtin tests and either remove or commentEric Christopher2015-10-1431-56/+90
| | | | | | about optimization options. llvm-svn: 250271
* Remove the optimization option from this test as it is unnecessaryEric Christopher2015-10-141-1/+1
| | | | | | and front end tests should avoid this if possible. llvm-svn: 250270
* Move the adc-builtins test to the pattern of the other builtinsEric Christopher2015-10-131-1/+3
| | | | | | tests by predefining _MM_MALLOC_H rather than use -ffreestanding. llvm-svn: 250203
* [X86] Add XSAVE intrinsic familyAmjad Aboud2015-10-133-1/+207
| | | | | | | | | | | | Add intrinsics for the XSAVE instructions (XSAVE/XSAVE64/XRSTOR/XRSTOR64) XSAVEOPT instructions (XSAVEOPT/XSAVEOPT64) XSAVEC instructions (XSAVEC/XSAVEC64) XSAVES instructions (XSAVES/XSAVES64/XRSTORS/XRSTORS64) Differential Revision: http://reviews.llvm.org/D13014 llvm-svn: 250158
* [X86] LLVM now prints XOP immediates as unsigned after r250147. Fix expected ↵Craig Topper2015-10-131-1/+1
| | | | | | check string accordingly. llvm-svn: 250149
* Tweak clang/test/CodeGen/debug-prefix-map.c to appease win32 hosts.NAKAMURA Takumi2015-10-131-1/+1
| | | | | | !1 = !DIFile(filename: "/var/empty\5C<stdin>", directory: "E:\5Cllvm\5Cbuild\5Ccmake-ninja\5Ctools\5Cclang\5Ctest\5CCodeGen") llvm-svn: 250136
* test: change argumentSaleem Abdulrasool2015-10-121-1/+1
| | | | | | | This failed on AArch64 due to the type mismatch using int instead of __builtin_va_list. llvm-svn: 250112
* test: relax path matching for windowsSaleem Abdulrasool2015-10-121-9/+9
| | | | | | The test failed on Windows due to use of \ as a path separator rather than /. llvm-svn: 250111
* Support Debug Info path remappingSaleem Abdulrasool2015-10-121-0/+34
| | | | | | | | | | | | | | | | Add support for the `-fdebug-prefix-map=` option as in GCC. The syntax is `-fdebug-prefix-map=OLD=NEW`. When compiling files from a path beginning with OLD, change the debug info to indicate the path as start with NEW. This is particularly helpful if you are preprocessing in one path and compiling in another (e.g. for a build cluster with distcc). Note that the linearity of the implementation is not as terrible as it may seem. This is normally done once per file with an expectation that the map will be small (1-2) entries, making this roughly linear in the number of input paths. Addresses PR24619. llvm-svn: 250094
* [Sema] Make `&function_with_enable_if_attrs` an errorGeorge Burgess IV2015-10-121-0/+51
| | | | | | | | | | | | | | | | | | This fixes a bug where one can take the address of a conditionally enabled function to drop its enable_if guards. For example: int foo(int a) __attribute__((enable_if(a > 0, ""))); int (*p)(int) = &foo; int result = p(-1); // compilation succeeds; calls foo(-1) Overloading logic has been updated to reflect this change, as well. Functions with enable_if attributes that are always true are still allowed to have their address taken. Differential Revision: http://reviews.llvm.org/D13607 llvm-svn: 250090
* Handle sse turning on mmx, but no -mmx not turning off SSE.Eric Christopher2015-10-082-5/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rationale : // sse3 __m128d test_mm_addsub_pd(__m128d A, __m128d B) { return _mm_addsub_pd(A, B); } // mmx void shift(__m64 a, __m64 b, int c) { _mm_slli_pi16(a, c); _mm_slli_pi32(a, c); _mm_slli_si64(a, c); _mm_srli_pi16(a, c); _mm_srli_pi32(a, c); _mm_srli_si64(a, c); _mm_srai_pi16(a, c); _mm_srai_pi32(a, c); } clang -msse3 -mno-mmx file.c -c For this code we should be able to explicitly turn off MMX without affecting the compilation of the SSE3 function and then diagnose and error on compiling the MMX function. This is a preparatory patch to the actual diagnosis code which is coming in a future patch. This sets us up to have the correct information where we need it and verifies that it's being emitted for the backend to handle. llvm-svn: 249733
* Migrate most feature map inclusion to initFeatureMap for the x86 target soEric Christopher2015-10-081-3/+3
| | | | | | | | that we can build up an accurate set of features rather than relying on TargetInfo initialization via handleTargetFeatures to munge the list of features. llvm-svn: 249732
* [Sema] Tweak incomplete enum types on MSVC ABI targetsDavid Majnemer2015-10-081-1/+1
| | | | | | | | | Enums without an explicit, fixed, underlying type are implicitly given a fixed 'int' type for ABI compatibility with MSVC. However, we can enforce the standard-mandated rules on these types as-if we didn't know this fact if the tag is not part of a definition. llvm-svn: 249667
* Update tests touched by r249656David Majnemer2015-10-082-2/+3
| | | | | | | | | These test updates almost exclusively around the change in behavior around enum: enums without a definition are considered incomplete except when targeting MSVC ABIs. Since these tests are interested in the 'incomplete-enum' behavior, restrict them to %itanium_abi_triple. llvm-svn: 249660
* [MSVC Compat] Enable ABI impacting non-conforming behavior independently of ↵David Majnemer2015-10-081-1/+1
| | | | | | | | | | -fms-compatibility No ABI for C++ currently makes it possible to implement the standard 100% perfectly. We wrongly hid some of our compatible behavior behind -fms-compatibility instead of tying it to the compiler ABI. llvm-svn: 249656
* Stop messing with the 'g' group of options in CompilerInvocation.Douglas Katzman2015-10-0849-53/+53
| | | | | | | | | | | | | | | | With this change, most 'g' options are rejected by CompilerInvocation. They remain only as Driver options. The new way to request debug info from cc1 is with "-debug-info-kind={line-tables-only|limited|standalone}" and "-dwarf-version={2|3|4}". In the absence of a command-line option to specify Dwarf version, the Toolchain decides it, rather than placing Toolchain-specific logic in CompilerInvocation. Also fix a bug in the Windows compatibility argument parsing in which the "rightmost argument wins" principle failed. Differential Revision: http://reviews.llvm.org/D13221 llvm-svn: 249655
* [WinEH] Remove NewMSEH and enable its behavior by defaultReid Kleckner2015-10-085-767/+180
| | | | | | | Testing has shown that it is at least as reliable as the old landingpad pattern matching code. llvm-svn: 249647
* clang/test/CodeGen/exceptions-seh-leave-new.c: Use "opt -instnamer" for ↵NAKAMURA Takumi2015-10-071-1/+1
| | | | | | branch-sensitive checks. llvm-svn: 249499
* [SEH] Fix x64 __exception_code in __except blocksReid Kleckner2015-10-071-0/+21
| | | | | | | Use llvm.eh.exceptioncode to get the code out of EAX for x64. For 32-bit, the filter is responsible for storing it to memory for us. llvm-svn: 249497
* [Headers][X86] Fix stream_load (movntdqa) to accept const*.Ahmed Bougacha2015-10-022-2/+2
| | | | | | | | | | Per Intel intrinsics guide: - _mm256_stream_load_si256 takes `__m256i const *' - _mm_stream_load_si128 takes `__m128i *', for no good reason. Let's accept const* for both. llvm-svn: 249213
* [WebAssembly] Add a __builtin_wasm_resize_memory() intrinsic.Dan Gohman2015-10-021-0/+6
| | | | llvm-svn: 249179
* [WebAssembly] Add a __builtin_wasm_memory_size() intrinsic.Dan Gohman2015-10-021-0/+6
| | | | llvm-svn: 249176
* Make test more resilient to FastIsel changes. NFC.Andrea Di Biagio2015-10-021-6/+6
| | | | | | | | | | | | | | | | | | | | | | Currently FastISel doesn't know how to select vector bitcasts. During instruction selection, fast-isel always falls back to SelectionDAG every time it encounters a vector bitcast. As a consequence of this, all the 'packed vector shift by immedate count' test cases in avx2-builtins.c are optimized by the DAGCombiner. In particular, the DAGCombiner would always fold trivial stack loads of constant shift counts into the operands of packed shift builtins. This behavior would start changing as soon as I reapply revision 249121. That revision would teach x86 fast-isel how to select bitcasts between vector types of the same size. As a consequence of that change, fast-isel would less often fall back to SelectionDAG. More importantly, DAGCombiner would no longer be able to simplify the code by folding the stack reload of a constant. No functional change. llvm-svn: 249142
* Fix the SSE4 byte sign extension in a cleaner way, and more thoroughlyChandler Carruth2015-10-015-0/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | test that our intrinsics behave the same under -fsigned-char and -funsigned-char. This further testing uncovered that AVX-2 has a broken cmpgt for 8-bit elements, and has for a long time. This is fixed in the same way as SSE4 handles the case. The other ISA extensions currently work correctly because they use specific instruction intrinsics. As soon as they are rewritten in terms of generic IR, they will need to add these special casts. I've added the necessary testing to catch this however, so we shouldn't have to chase it down again. I considered changing the core typedef to be signed, but that seems like a bad idea. Notably, it would be an ABI break if anyone is reaching into the innards of the intrinsic headers and passing __v16qi on an API boundary. I can't be completely confident that this wouldn't happen due to a macro expanding in a lambda, etc., so it seems much better to leave it alone. It also matches GCC's behavior exactly. A fun side note is that for both GCC and Clang, -funsigned-char really does change the semantics of __v16qi. To observe this, consider: % cat x.cc #include <smmintrin.h> #include <iostream> int main() { __v16qi a = { 1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; __v16qi b = _mm_set1_epi8(-1); std::cout << (int)(a / b)[0] << ", " << (int)(a / b)[1] << '\n'; } % clang++ -o x x.cc && ./x -1, 1 % clang++ -funsigned-char -o x x.cc && ./x 0, 1 However, while this may be surprising, both Clang and GCC agree. Differential Revision: http://reviews.llvm.org/D13324 llvm-svn: 249097
* Patch over a really horrible bug in our vector builtins that showed upChandler Carruth2015-10-011-0/+2
| | | | | | | | | | | | | | | | | | | | | | | recently when we started using direct conversion to model sign extension. The __v16qi type we use for SSE v16i8 vectors is defined in terms of 'char' which may or may not be signed! This causes us to generate pmovsx and pmovzx depending on the setting of -funsigned-char. This patch just forms an explicitly signed type and uses that to formulate the sign extension. While this gets the correct behavior (which we now verify with the enhanced test) this is just the tip of the ice berg. Now that I know what to look for, I have found errors of this sort *throughout* our vector code. Fortunately, this is the only specific place where I know of users actively having their code miscompiled by Clang due to this, so I'm keeping the fix for those users minimal and targeted. I'll be sending a proper email for discussion of how to fix these systematically, what the implications are, and just how widely broken this is... From what I can tell, we have never shipped a correct set of builtin headers for x86 when users rely on -funsigned-char. Oops. llvm-svn: 248980
* [CUDA] fix codegen for __nvvm_atom_cas_*Jingyue Wu2015-09-301-0/+3
| | | | | | | | | | | | Summary: __nvvm_atom_cas_* returns the old value instead of whether the swap succeeds. Reviewers: eliben, tra Subscribers: jholewinski, llvm-commits Differential Revision: http://reviews.llvm.org/D13306 llvm-svn: 248951
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