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* Generating assumption loads of vptr after ctor call (fixed)Piotr Padlewski2015-09-091-1/+1
| | | | | | | | | | | | | | | | | Generating call assume(icmp %vtable, %global_vtable) after constructor call for devirtualization purposes. For more info go to: http://lists.llvm.org/pipermail/cfe-dev/2015-July/044227.html Edit: Fixed version because of PR24479. After this patch got reverted because of ScalarEvolution bug (D12719) Merged after John McCall big patch (Added Address). http://reviews.llvm.org/D11859 llvm-svn: 247199
* [ARM] "cortex-r5f" and "cortex-m4f" are unknown names for clang.Alexandros Lamprineas2015-09-091-7/+2
| | | | | | | | | | | | The tests in test/CodeGen/arm-target-features.c are currently passing but warning messages are suppressed. These tests are now synchronized with the corresponding changes in Target Parser. This patch will fix the regressions in clang caused by r247136 Differential Revision: http://reviews.llvm.org/D12722 llvm-svn: 247138
* Introduce __builtin_nontemporal_store and __builtin_nontemporal_load.Michael Zolotukhin2015-09-081-0/+48
| | | | | | | | | | | | | Summary: Currently clang provides no general way to generate nontemporal loads/stores. There are some architecture specific builtins for doing so (e.g. in x86), but there is no way to generate non-temporal store on, e.g. AArch64. This patch adds generic builtins which are expanded to a simple store with '!nontemporal' attribute in IR. Differential Revision: http://reviews.llvm.org/D12313 llvm-svn: 247104
* Collect SEH captures in a set instead of a vector to avoidJohn McCall2015-09-081-0/+30
| | | | | | | | doing redundant work if a variable is used multiple times. Fixes PR24751. llvm-svn: 247075
* clang/test/CodeGen/complex-convert.c: Appease for targeting powerpc64-*.NAKAMURA Takumi2015-09-081-0/+2
| | | | llvm-svn: 247015
* findDominatingStoreToReturn in CGCall.cpp didn't check if a candidate storeJakub Kuderski2015-09-081-0/+17
| | | | | | | | | | | | | | instruction used the ReturnValue as pointer operand or value operand. This led to wrong code gen - in later stages (load-store elision code) the found store and its operand would be erased, causing ReturnValue to become a <badref>. The patch adds a check that makes sure that ReturnValue is a pointer operand of store instruction. Regression test is also added. This fixes PR24386. Differential Revision: http://reviews.llvm.org/D12400 llvm-svn: 247003
* Fix clang/test/CodeGen/mips-varargs.c for -Asserts, possibly typo.NAKAMURA Takumi2015-09-081-1/+1
| | | | llvm-svn: 246994
* Compute and preserve alignment more faithfully in IR-generation.John McCall2015-09-0828-623/+551
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Introduce an Address type to bundle a pointer value with an alignment. Introduce APIs on CGBuilderTy to work with Address values. Change core APIs on CGF/CGM to traffic in Address where appropriate. Require alignments to be non-zero. Update a ton of code to compute and propagate alignment information. As part of this, I've promoted CGBuiltin's EmitPointerWithAlignment helper function to CGF and made use of it in a number of places in the expression emitter. The end result is that we should now be significantly more correct when performing operations on objects that are locally known to be under-aligned. Since alignment is not reliably tracked in the type system, there are inherent limits to this, but at least we are no longer confused by standard operations like derived-to-base conversions and array-to-pointer decay. I've also fixed a large number of bugs where we were applying the complete-object alignment to a pointer instead of the non-virtual alignment, although most of these were hidden by the very conservative approach we took with member alignment. Also, because IRGen now reliably asserts on zero alignments, we should no longer be subject to an absurd but frustrating recurring bug where an incomplete type would report a zero alignment and then we'd naively do a alignmentAtOffset on it and emit code using an alignment equal to the largest power-of-two factor of the offset. We should also now be emitting much more aggressive alignment attributes in the presence of over-alignment. In particular, field access now uses alignmentAtOffset instead of min. Several times in this patch, I had to change the existing code-generation pattern in order to more effectively use the Address APIs. For the most part, this seems to be a strict improvement, like doing pointer arithmetic with GEPs instead of ptrtoint. That said, I've tried very hard to not change semantics, but it is likely that I've failed in a few places, for which I apologize. ABIArgInfo now always carries the assumed alignment of indirect and indirect byval arguments. In order to cut down on what was already a dauntingly large patch, I changed the code to never set align attributes in the IR on non-byval indirect arguments. That is, we still generate code which assumes that indirect arguments have the given alignment, but we don't express this information to the backend except where it's semantically required (i.e. on byvals). This is likely a minor regression for those targets that did provide this information, but it'll be trivial to add it back in a later patch. I partially punted on applying this work to CGBuiltin. Please do not add more uses of the CreateDefaultAligned{Load,Store} APIs; they will be going away eventually. llvm-svn: 246985
* [X86][SSE4A] Added SSE4A IR + assembly codegen builtin testsSimon Pilgrim2015-09-071-14/+25
| | | | llvm-svn: 246974
* [X86][SSSE3] Added SSSE3 IR + assembly codegen builtin testsSimon Pilgrim2015-09-062-10/+127
| | | | | | Transferred SSSE3 instructions from sse-builtins.c llvm-svn: 246948
* [X86]][SSE3] Added SSE41 IR + assembly codegen builtin testsSimon Pilgrim2015-09-062-162/+433
| | | | | | Transferred SSE41 instructions from sse-builtins.c llvm-svn: 246947
* Refactoring of how ARMTargetInfo handles default target features.Alexandros Lamprineas2015-09-061-2/+25
| | | | | | Differential Revision: http://reviews.llvm.org/D11299 llvm-svn: 246946
* [X86]][SSE3] Added SSE3 IR + assembly codegen builtin testsSimon Pilgrim2015-09-061-0/+85
| | | | llvm-svn: 246945
* [X86]][SSE42] Added SSE42 IR + assembly codegen builtin testsSimon Pilgrim2015-09-061-0/+141
| | | | llvm-svn: 246944
* Fix a bug in __builtin_object_size cast removalGeorge Burgess IV2015-09-041-0/+30
| | | | | | | | | | | Apparently there are many cast kinds that may cause implicit pointer arithmetic to happen. In light of this, the cast ignoring logic introduced in r246877 has been changed to only ignore a small set of cast kinds, and a test for this behavior has been added. Thanks to Richard for catching this before it became a bug report. :) llvm-svn: 246890
* Increase accuracy of __builtin_object_size.George Burgess IV2015-09-041-4/+115
| | | | | | | | | | | | | | | | | | | Improvements: - For all types, we would give up in a case such as: __builtin_object_size((char*)&foo, N); even if we could provide an answer to __builtin_object_size(&foo, N); We now provide the same answer for both of the above examples in all cases. - For type=1|3, we now support subobjects with unknown bases, as long as the designator is valid. Thanks to Richard Smith for the review + design planning. Review: http://reviews.llvm.org/D12169 llvm-svn: 246877
* [X86-64] Allow additional register names in inline assembler.Alexey Bataev2015-09-041-0/+53
| | | | | | | Patch allows to recognize additional registers x8d, x8b, x8w - x15d, x15b, x15w in inline assembler, already recognized by backend Differential Revision: http://reviews.llvm.org/D12594 llvm-svn: 246835
* [WebAssembly] Initial WebAssembly support in clangDan Gohman2015-09-035-0/+128
| | | | | | | | | | This implements basic support for compiling (though not yet assembling or linking) for a WebAssembly target. Note that ABI details are not yet finalized, and may change. Differential Revision: http://reviews.llvm.org/D12002 llvm-svn: 246814
* [ARM] Allow passing/returning of __fp16 argumentsOliver Stannard2015-09-031-0/+21
| | | | | | | | | | | | | | | | | | | | | The ACLE (ARM C Language Extensions) 2.0 allows the __fp16 type to be used as a functon argument or return type (ACLE 1.1 did not). The current public release of the AAPCS (2.09) states that __fp16 values should be converted to single-precision before being passed or returned, but AAPCS 2.10 (to be released shortly) changes this, so that they are passed in the least-significant 16 bits of either a GPR (for base AAPCS) or a single-precision register (for AAPCS-VFP). This does not change how arguments are passed if they get passed on the stack. This patch brings clang up to compliance with the latest versions of both of these specs. We can now set the __ARM_FP16_ARGS ACLE predefine, and we have always been able to set the __ARM_FP16_FORMAT_IEEE predefine (we do not support the alternative format). llvm-svn: 246764
* Revert 246755 as it breaks buildbotsOliver Stannard2015-09-031-21/+0
| | | | | | | | | | | | | | | | | | | | | | | | Original commit message: [ARM] Allow passing/returning of __fp16 arguments The ACLE (ARM C Language Extensions) 2.0 allows the __fp16 type to be used as a functon argument or return type (ACLE 1.1 did not). The current public release of the AAPCS (2.09) states that __fp16 values should be converted to single-precision before being passed or returned, but AAPCS 2.10 (to be released shortly) changes this, so that they are passed in the least-significant 16 bits of either a GPR (for base AAPCS) or a single-precision register (for AAPCS-VFP). This does not change how arguments are passed if they get passed on the stack. This patch brings clang up to compliance with the latest versions of both of these specs. We can now set the __ARM_FP16_ARGS ACLE predefine, and we have always been able to set the __ARM_FP16_FORMAT_IEEE predefine (we do not support the alternative format). llvm-svn: 246760
* [ARM] Allow passing/returning of __fp16 argumentsOliver Stannard2015-09-031-0/+21
| | | | | | | | | | | | | | | | | | | | | The ACLE (ARM C Language Extensions) 2.0 allows the __fp16 type to be used as a functon argument or return type (ACLE 1.1 did not). The current public release of the AAPCS (2.09) states that __fp16 values should be converted to single-precision before being passed or returned, but AAPCS 2.10 (to be released shortly) changes this, so that they are passed in the least-significant 16 bits of either a GPR (for base AAPCS) or a single-precision register (for AAPCS-VFP). This does not change how arguments are passed if they get passed on the stack. This patch brings clang up to compliance with the latest versions of both of these specs. We can now set the __ARM_FP16_ARGS ACLE predefine, and we have always been able to set the __ARM_FP16_FORMAT_IEEE predefine (we do not support the alternative format). llvm-svn: 246755
* add __builtin_unpredictable and convert to metadataSanjay Patel2015-09-021-0/+38
| | | | | | | | | | | | | | | | | | | | | | | This patch depends on r246688 (D12341). The goal is to make LLVM generate different code for these functions for a target that has cheap branches (see PR23827 for more details): int foo(); int normal(int x, int y, int z) { if (x != 0 && y != 0) return foo(); return 1; } int crazy(int x, int y) { if (__builtin_unpredictable(x != 0 && y != 0)) return foo(); return 1; } Differential Revision: http://reviews.llvm.org/D12458 llvm-svn: 246699
* [PowerPC] Support __builtin_ppc_get_timebaseHal Finkel2015-08-311-0/+7
| | | | | | | | | | GCC 4.8+ has a PowerPC-specific intrinsic, __builtin_ppc_get_timebase, to do what Clang's __builtin_readcyclecounter does. For compatibility with code that uses GCC's spelling (including glibc), support it as well. Partially fixes PR23681. llvm-svn: 246510
* Fix CHECK directives that weren't checking.Hans Wennborg2015-08-314-16/+17
| | | | llvm-svn: 246492
* [CUDA] fix codegen for __nvvm_atom_min/max_gen_u*Jingyue Wu2015-08-311-10/+10
| | | | | | | | | | | | Summary: Clang should emit "atomicrmw umin/umax" instead of "atomicrmw min/max". Reviewers: eliben, tra Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D12487 llvm-svn: 246455
* Fix test for Release builds, the label form is <label>:14, not <label>14.Yaron Keren2015-08-301-6/+6
| | | | llvm-svn: 246391
* Make test resistant to false matches of numbered (unnamed) labels inside ↵Yaron Keren2015-08-301-4/+9
| | | | | | | | | | | other numbers. In release builds labels are numbers. Matching just the number may result in false matches where the label is contained in other numbers, such as 14 inside [114 x i8]. A stricter match requiring start of line or > character before the label avoids these false matches. llvm-svn: 246385
* [X86] Reapplied r246204, r246206, r246211, r246223Simon Pilgrim2015-08-294-4/+136
| | | | | | | | (Re)added debug codegen test for F16C, FMA4, XOP + 3DNow! intrinsics Part of PR24590 llvm-svn: 246363
* Add a check for a function we're not testing.Eric Christopher2015-08-291-0/+1
| | | | llvm-svn: 246355
* Revert "[X86][3DNow] Added debug codegen test for 3DNow! intrinsics"Renato Golin2015-08-281-26/+1
| | | | | | This reverts commit r246223, as it broke all ARM/AArch64 bots. llvm-svn: 246323
* Revert "[X86][XOP] Added debug codegen test for XOP intrinsics"Renato Golin2015-08-281-66/+1
| | | | | | This reverts commit r246211, as it broke all ARM/AArch64 bots. llvm-svn: 246321
* Revert "[X86][FMA4] Added debug codegen test for FMA4 intrinsics"Renato Golin2015-08-281-34/+1
| | | | | | This reverts commit r246206, as it broke all ARM/AArch64 bots. llvm-svn: 246320
* Revert "[X86][F16C] Added debug codegen test for F16C intrinsics"Renato Golin2015-08-281-6/+1
| | | | | | This reverts commit r246204, as it was breaking all ARM/AArch64 bots. llvm-svn: 246319
* Revert r246214 and r246213Steven Wu2015-08-281-1/+1
| | | | | | These two commits causes llvm LTO bootstrap to hang in ScalarEvolution. llvm-svn: 246282
* [X86] Bump Darwin MaxVectorAlign to 64 when AVX512 is enabled.Ahmed Bougacha2015-08-271-0/+10
| | | | | | | | | | | Without this, 64-byte vector types (__m512), specified to be 64-byte aligned in the AVX512 draft SysV ABI, will only be 32-byte aligned. This is analoguous to AVX, for which we accept 32-byte max alignment. Differential Revision: http://reviews.llvm.org/D10724 llvm-svn: 246230
* [X86] Conditionalize Darwin MaxVectorAlign on the presence of AVX.Ahmed Bougacha2015-08-271-13/+26
| | | | | | | | | There's no point in using a larger alignment if we have no instructions that would benefit from it. Differential Revision: http://reviews.llvm.org/D12389 llvm-svn: 246229
* [X86][3DNow] Added debug codegen test for 3DNow! intrinsicsSimon Pilgrim2015-08-271-1/+26
| | | | | | Part of PR24590 llvm-svn: 246223
* Generating assumption loads of vptr after ctor call (fixed)Piotr Padlewski2015-08-271-1/+1
| | | | | | | | | | | | | | | Generating call assume(icmp %vtable, %global_vtable) after constructor call for devirtualization purposes. For more info go to: http://lists.llvm.org/pipermail/cfe-dev/2015-July/044227.html Edit: Fixed version because of PR24479. http://reviews.llvm.org/D11859 llvm-svn: 246213
* [X86][XOP] Added debug codegen test for XOP intrinsicsSimon Pilgrim2015-08-271-1/+66
| | | | | | Part of PR24590 llvm-svn: 246211
* [X86][FMA4] Added debug codegen test for FMA4 intrinsicsSimon Pilgrim2015-08-271-1/+34
| | | | | | Part of PR24590 llvm-svn: 246206
* [X86][F16C] Added debug codegen test for F16C intrinsicsSimon Pilgrim2015-08-271-1/+6
| | | | | | Part of PR24590 llvm-svn: 246204
* [X86] Add __builtin_ia32_undef* intrinsics to testSimon Pilgrim2015-08-271-0/+3
| | | | | | Minor tweak to rL246083 llvm-svn: 246200
* Target attribute syntax compatibility fix - gcc uses no- rather than mno-.Eric Christopher2015-08-272-3/+3
| | | | llvm-svn: 246197
* Rename this file to have a processor suffix to help identify.Eric Christopher2015-08-271-0/+0
| | | | llvm-svn: 246196
* Rewrite the code generation handling for function feature and cpu attributes.Eric Christopher2015-08-272-1/+8
| | | | | | | | | | | | | | | | | | | | A couple of changes here: a) Do less work in the case where we don't have a target attribute on the function. We've already canonicalized the attributes for the function - no need to do more work. b) Use the newer canonicalized feature adding functions from TargetInfo to do the work when we do have a target attribute. This enables us to diagnose some warnings in the case of conflicting written attributes (only ppc does this today) and also make sure to get all of the features for a cpu that's listed rather than just change the cpu. Updated all testcases accordingly and added a new testcase to verify that we'll error out on ppc if we have some incompatible options using the existing diagnosis framework there. llvm-svn: 246195
* DI: Update DISubprogram testcases after LLVM r246098Duncan P. N. Exon Smith2015-08-261-2/+2
| | | | llvm-svn: 246099
* [ARM] Mark mcr/mrc builtin operands as required-immediate.Ahmed Bougacha2015-08-261-0/+38
| | | | | | An early error message is better than the "cannot select" alternative. llvm-svn: 246094
* [ms-inline-asm] Add field access to MS inline asm identifier lookupReid Kleckner2015-08-261-0/+18
| | | | | | | | | | | | | | Now we can parse code like this: struct A { int field; }; int f(A o) { __asm mov eax, o.field } Fixes PR19117. llvm-svn: 246088
* [X86][SSE] Add _mm_undefined_* intrinsicsSimon Pilgrim2015-08-263-0/+60
| | | | | | | | | | | | | | | | Added missing SSE/AVX 'undefined' intrinsics (PR24040): _mm_undefined_pd, _mm_undefined_ps + _mm_undefined_si128 _mm256_undefined_pd, _mm256_undefined_ps + _mm256_undefined_si256 _mm512_undefined, _mm512_undefined_ps, _mm512_undefined_pd + _mm512_undefined_epi32 Added builtin intrinsicss: __builtin_ia32_undef128, __builtin_ia32_undef256 + __builtin_ia32_undef512 Differential Revision: http://reviews.llvm.org/D12052 llvm-svn: 246083
* [Headers] Require x86-registered for r245987 codegen tests.Ahmed Bougacha2015-08-251-0/+2
| | | | llvm-svn: 245992
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