bcm5719-llvm - Project Ortega BCM5719 LLVM

	Commit message (Collapse)	Author	Age	Files	Lines
*	[mips][msa] Correct sld and sldi builtins.	Daniel Sanders	2013-12-10	1	-9/+9
\| \| \| \| \| \| \| \| \| \| \| \| \|	Summary: The result register of these instructions is also the first operand. Reviewers: jacksprat, dsanders Reviewed By: dsanders Differential Revision: http://llvm-reviews.chandlerc.com/D2362 Differential Revision: http://llvm-reviews.chandlerc.com/D2363 llvm-svn: 196910
*	[mips][msa] Correct definition of bins[lr] and CHECK-DAG-ize related tests	Daniel Sanders	2013-10-30	1	-8/+8
\| \| \| \|	llvm-svn: 193695
*	[mips][msa] Added support for matching bmnz, bmnzi, bmz, and bmzi from ↵	Daniel Sanders	2013-10-30	1	-10/+17
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	normal IR (i.e. not intrinsics) Also corrected the definition of the intrinsics for these instructions (the result register is also the first operand), and added intrinsics for bsel and bseli to clang (they already existed in the backend). These four operations are mostly equivalent to bsel, and bseli (the difference is which operand is tied to the result). As a result some of the tests changed as described below. bitwise.ll: - bsel.v test adapted so that the mask is unknown at compile-time. This stops it emitting bmnzi.b instead of the intended bsel.v. - The bseli.b test now tests the right thing. Namely the case when one of the values is an uimm8, rather than when the condition is a uimm8 (which is covered by bmnzi.b) compare.ll: - bsel.v tests now (correctly) emits bmnz.v instead of bsel.v because this is the same operation (see MSA.txt). i8.ll - CHECK-DAG-ized test. - bmzi.b test now (correctly) emits equivalent bmnzi.b with swapped operands because this is the same operation (see MSA.txt). - bseli.b still emits bseli.b though because the immediate makes it distinguishable from bmnzi.b. vec.ll: - CHECK-DAG-ized test. - bmz.v tests now (correctly) emits bmnz.v with swapped operands (see MSA.txt). - bsel.v tests now (correctly) emits bmnz.v with swapped operands (see MSA.txt). llvm-svn: 193693
*	[mips][msa] Added support for matching bins[lr]i.[bhwd] from normal IR (i.e. ↵	Daniel Sanders	2013-10-30	1	-8/+8
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	not intrinsics) This required correcting the definition of the bins[lr]i intrinsics because the result is also the first operand. It also required removing the (arbitrary) check for 32-bit immediates in MipsSEDAGToDAGISel::selectVSplat(). Currently using binsli.d with 2 bits set in the mask doesn't select binsli.d because the constant is legalized into a ConstantPool. Similar things can happen with binsri.d with more than 10 bits set in the mask. The resulting code when this happens is correct but not optimal. llvm-svn: 193687
*	[mips][msa] Add intrinsics that map to pseudo-instructions.	Daniel Sanders	2013-10-23	1	-0/+6
\| \| \| \| \| \| \| \| \| \| \|	Unlike the previously added intrinsics, these do not map to a single instruction on MIPS32. They are provided for regularity (to round out the .[bhw] variants of the same operation) and compatibility with GCC. Includes: copy_[us].d, fill.d, insert.d, insve.d llvm-svn: 193237
*	[mips][msa] Fix definition of SLD instruction.	Matheus Almeida	2013-10-21	1	-4/+4
\| \| \| \| \| \| \|	The second parameter of the SLD intrinsic is the number of columns (GPR) to slide left the source array. llvm-svn: 193076
*	[mips][msa] Added most of the remaining builtins	Daniel Sanders	2013-10-17	1	-0/+167
\| \| \| \| \| \| \| \| \| \| \|	Includes: and.v, bmnz.v, bmz.v, bnz.[bhwdv], bz.[bhwdv], cfcmsa, ctcmsa, fcaf, fcor, fcueq, fcul[et], fcun, fcune, fsaf, fsueq, fsul[et], fsun, fsune, ftrunc hadd_[su].[hwd], hsub_[su].[hwd], insert.[bhw], insve.[bhw], ld.[bhwd], move.v, nor.v, or.v, srar.[bhwd], srari.[bhwd], srlr.[bhwd], srlri.[bhwd], st.[bhwd], subsus_u.[bhwd], subsuu_s.[bhwd], vshf.[bhwd], xor.v llvm-svn: 192896
*	[mips][msa] Corrected the definition of the dotp_[su].[hwd] intrinsics	Daniel Sanders	2013-09-11	1	-6/+6
\| \| \| \| \| \| \|	The elements of the operands should be half the width of the elements of the result. llvm-svn: 190505
*	[mips][msa] Removed unsupported dot product instructions (dotp_[su].b).	Daniel Sanders	2013-09-10	1	-2/+0
\| \| \| \| \| \|	The dotp_[su].b instructions never existed in any revision of the MSA spec. llvm-svn: 190399
*	[mips][msa] Added fexdo, fexup[lr] builtins	Daniel Sanders	2013-08-20	1	-0/+9
\| \| \| \|	llvm-svn: 188784
*	[Mips][msa] Added most builtins from add.a to xori	Jack Carter	2013-08-15	1	-0/+642
	Includes: add.a, adds_a, adds_s, adds_u, addv, addvi, andi.b, asub_[su], ave_[su], aver_[su], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bset, bseti, c(eq\|ne), c(eq\|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], fadd, fceq, fclass, fcl[et], fcne, fdiv, fexp2, ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin, fmin_a, fmsub, fmul, frint, fseq, fsle, fslt, fsne, fsqr, fsub, ftint_[su], ftq, ilvev, ilvl, ilvod, ilvr, ldi, frcp, frsqrt, madd_q, maddr_q, maddv, max_[asu], maxi_[su], min_[asu], mini_[su], mod_[su], msub_q, msubr_q, msubv, mul_q, mulr_q, mulv, nloc, nlzc, nori, ori, pckev, pckod, pcnt, sat_[su], shf, sld, sldi, sll, slli, splat, splati, sr[al], sr[al]i, subs_[su], subv, subvi, xori Patch by Daniel Sanders llvm-svn: 188461