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* [AVX-512] Replace masked dword and qword variable shift builtins with ↵Craig Topper2016-11-131-6/+10
| | | | | | | | unmasked builtins and a select. This is part of a set of changes to allow InstCombine in the backend to optimize variable shifts without having to know about masking. llvm-svn: 286757
* [AVX-512] Convert the rest of the masked shift by immediate and by single ↵Craig Topper2016-11-121-12/+20
| | | | | | | | element builtins over to the newly added unmasked builtins and a select. This should also fix PR30691 since the new builtins are handled like the legacy builtins in the backend. llvm-svn: 286714
* [AVX-512] Remove masked vector insert builtins and replace with native ↵Craig Topper2016-11-011-6/+10
| | | | | | | | shufflevectors and selects. Unfortunately, the backend currently doesn't fold masks into the instructions correctly when they come from these shufflevectors. I'll work on that in a future commit. llvm-svn: 285667
* [AVX-512] Use selectd instead of selectps for _mm256_mask_extracti32x4_epi32.Craig Topper2016-10-311-2/+2
| | | | llvm-svn: 285545
* [AVX-512] Remove masked vector extract builtins and replace with native ↵Craig Topper2016-10-311-6/+10
| | | | | | | | shufflevectors and selects. Unfortunately, the backend currently doesn't fold masks into the instructions correctly when they come from these shufflevectors. I'll work on that in a future commit. llvm-svn: 285540
* [AVX-512] Remove many of the masked 128/256-bit shift builtins and replace ↵Craig Topper2016-10-311-44/+200
| | | | | | them with unmasked builtins and selects. llvm-svn: 285539
* [AVX-512] Remove masked 128/256-bit sqrt builtins and replace them with ↵Craig Topper2016-10-291-8/+16
| | | | | | unmasked builtins and a select. llvm-svn: 285504
* [AVX-512] Remove masked 128/256-bit pmuludq/pmuldq builtins and replace them ↵Craig Topper2016-10-291-8/+16
| | | | | | with unmasked builtins and a select. llvm-svn: 285503
* [AVX-512] Remove masked 128/256-bit floating point max/min builtins. Use ↵Craig Topper2016-10-291-16/+32
| | | | | | unmasked builtins with select instead. llvm-svn: 285502
* [AVX-512] Replace 64-bit element and 512-bit vector pmin/pmax builtins with ↵Craig Topper2016-10-241-24/+64
| | | | | | native IR like we do for 128/256-bit, but with the addition of masking. llvm-svn: 284956
* [AVX-512] Replace masked 128/256-bit byte, word, and dword min/max builtins ↵Craig Topper2016-10-231-16/+48
| | | | | | with selects and the older unmasked builtins. llvm-svn: 284954
* [AVX-512] Replace masked 128/256-bit vpmovzx/vpmovsx builtins with native IR.Craig Topper2016-10-221-40/+80
| | | | llvm-svn: 284927
* [AVX-512] Remove builtins for 128/256-bit pabsb/pabsw. We can use a select ↵Craig Topper2016-10-221-4/+8
| | | | | | and the older non-masked versions instead. llvm-svn: 284924
* [X86] Remove the mm_malloc.h include guard hack from the X86 builtins testsElad Cohen2016-09-281-3/+1
| | | | | | | | | | | | The X86 clang/test/CodeGen/*builtins.c tests define the mm_malloc.h include guard as a hack for avoiding its inclusion (mm_malloc.h requires a hosted environment since it expects stdlib.h to be available - which is not the case in these internal clang codegen tests). This patch removes this hack and instead passes -ffreestanding to clang cc1. Differential Revision: https://reviews.llvm.org/D24825 llvm-svn: 282581
* [AVX-512] Remove 128-bit and 256-bit masked floating point add/sub/mul/div ↵Craig Topper2016-09-041-40/+72
| | | | | | | | builtins and replace with native operations. We can't do the 512-bit ones because they take a rounding mode argument that we can't represent. llvm-svn: 280635
* [AVX-512] Remove masked integer mullo builtins and replace with native IR.Craig Topper2016-09-031-4/+8
| | | | llvm-svn: 280597
* [AVX-512] Remove masked integer add/sub builtins and replace with native IR.Craig Topper2016-09-031-17/+33
| | | | llvm-svn: 280596
* [AVX512] integer comparisions enumeration.Asaf Badouh2016-08-071-27/+27
| | | | | | | | | | fix Bug 28842 https://llvm.org/bugs/show_bug.cgi?id=28842 Differential Revision: https://reviews.llvm.org/D22212 llvm-svn: 277955
* After PR28761 use -Wall with -Werror in builtins tests to identifyEric Christopher2016-08-041-1/+1
| | | | | | possible problems in headers. llvm-svn: 277696
* [X86] Add missing __x86_64__ qualifiers on a bunch of intrinsics that assume ↵Craig Topper2016-07-211-0/+2
| | | | | | | | 64-bit GPRs are available. Usages of these intrinsics in a 32-bit build results in assertions in the backend. llvm-svn: 276249
* [AVX512] Replace masked AND/OR/XOR intrinsics with native code and remove ↵Craig Topper2016-07-111-33/+61
| | | | | | the builtins. llvm-svn: 275049
* [X86][AVX512] Converted the VBROADCAST intrinsics to generic IRSimon Pilgrim2016-07-051-28/+42
| | | | llvm-svn: 274544
* [X86] Use undefined instead of setzero in shufflevector based intrinsics ↵Craig Topper2016-07-041-8/+8
| | | | | | when the second source is unused. Rewrite immediate extractions in shuffle intrinsics to be in ((c >> x) & y) form instead of ((c & z) >> x). This way only x varies between each use instead of having to vary x and z. llvm-svn: 274525
* [X86][AVX512] Converted the VSHUFPD intrinsics to generic IRSimon Pilgrim2016-07-041-8/+16
| | | | llvm-svn: 274523
* [X86][AVX512] Converted the VPERMPD/VPERMQ intrinsics to generic IRSimon Pilgrim2016-07-041-73/+76
| | | | llvm-svn: 274502
* [AVX512] Modify what indices we emit for the zero vector we use for zero ↵Craig Topper2016-07-041-1/+2
| | | | | | extension of the result of a v2i1 or v4i1 masked compare. This way we emit something that the backend easily interprets as a concatenation rather than a true shuffle. This delivers slightly better codegen with the current backend capabilities. llvm-svn: 274484
* [X86][AVX512] Converted the MOVDDUP/MOVSLDUP/MOVSHDUP masked intrinsics to ↵Simon Pilgrim2016-07-021-14/+26
| | | | | | | | generic IR llvm companion patch imminent llvm-svn: 274442
* [X86] Replace 128-bit and 256 masked vpermilps/vpermilpd builtins with ↵Craig Topper2016-07-021-16/+24
| | | | | | native IR. llvm-svn: 274425
* [AVX512] Zero extend cmp intrinsic return value.Igor Breger2016-06-291-0/+1
| | | | | | Differential Revision: http://reviews.llvm.org/D21746 llvm-svn: 274110
* Update the expected masked load/store intrinsics names in testsArtur Pilipenko2016-06-281-48/+48
| | | | | | The mangling of their names was changed in order to support arbitrary addrspace pointers as arguments in rL274043. llvm-svn: 274044
* [AVX512] Replace masked unpack builtins with shufflevector and selects.Craig Topper2016-06-231-32/+64
| | | | llvm-svn: 273533
* [AVX512] Replace masked integer cmp and ucmp builtins with native IR.Craig Topper2016-06-221-108/+154
| | | | llvm-svn: 273378
* [AVX512] Move the 128-bit and 256-bit lzcnt intrinsics to avx512vlcdintrin.h ↵Craig Topper2016-06-211-73/+0
| | | | | | where they belong. llvm-svn: 273249
* [AVX512] Use native IR for mask pcmpeq/pcmpgt intrinsics.Craig Topper2016-06-151-16/+24
| | | | llvm-svn: 272787
* [AVX512] Masked pcmpeqd, pcmpeqq, pcmpgtd, and pcmpgtq don't require ↵Craig Topper2016-06-131-0/+96
| | | | | | avx512bw, just avx512vl. llvm-svn: 272532
* [AVX512] Use a regular expression instead of checking for a specific name in ↵Craig Topper2016-06-111-1/+1
| | | | | | a CHECK line in test. llvm-svn: 272470
* [AVX512] Implement masked and 512-bit pshufd intrinsics directly with ↵Craig Topper2016-06-111-4/+8
| | | | | | __builtin_shufflevector and __builtin_ia32_select. llvm-svn: 272467
* [AVX512] Emit select instruction instead of using x86 specific instrinsics.Igor Breger2016-06-081-24/+24
| | | | | | | | This will allow us to remove the x86 instrinics from the backend. Differential Revision: http://reviews.llvm.org/D21060 llvm-svn: 272141
* [AVX512] Remove 512-bit andnot tests from the avx512vl test file.Craig Topper2016-06-041-36/+0
| | | | llvm-svn: 271795
* [Clang][AVX512][INTRINSICS] adding round cvt and fix regular cvtps_phMichael Zuckerman2016-06-021-4/+27
| | | | | | Differential Revision: http://reviews.llvm.org/D20870 llvm-svn: 271498
* [AVX512] Convert masked load builtins to generic masked load intrinsics ↵Craig Topper2016-05-311-32/+32
| | | | | | | | instead of the x86 specific ones. This will allow the x86 intrinsics to be removed from the backend. llvm-svn: 271253
* [AVX512] Emit generic masked store instrinsics instead of using x86 specific ↵Craig Topper2016-05-311-16/+16
| | | | | | | | intrinsics. This will allow us to remove the x86 instrinics from the backend. llvm-svn: 271246
* Fix instrinsics names: Michael Zuckerman2016-05-261-15/+12
| | | | | | | | | _mm128_cmp_ps_mask-->_mm_cmp_ps_mask _mm128_mask_cmp_ps_mask-->_mm_mask_cmp_ps_mask _mm128_cmp_pd_mask-->_mm_cmp_pd_mask _mm128_mask_cmp_pd_mask-->_mm_mask_cmp_pd_mask llvm-svn: 270830
* [Clang][AVX512][BUILTIN]adding missing intrinsics for movdaq instruction setMichael Zuckerman2016-05-231-0/+48
| | | | | | Differential Revision: http://reviews.llvm.org/D20514 llvm-svn: 270401
* [X86] Add immediate range checks for many of the builtins.Craig Topper2016-05-181-16/+16
| | | | | | This time allow -128 to 255 for builtins that use a char type immediate." llvm-svn: 269878
* Revert "[X86] Add immediate range checks for many of the builtins."Filipe Cabecinhas2016-05-171-16/+16
| | | | | | This reverts commit r269619. llvm-svn: 269765
* [X86] Add immediate range checks for many of the builtins.Craig Topper2016-05-151-16/+16
| | | | llvm-svn: 269619
* [Clang][AVX512][Builtin] Adding intrinsics for vcvt{ph|ps}2{ps|ph} ↵Michael Zuckerman2016-05-031-0/+48
| | | | | | | | instruction set Differential Revision: http://reviews.llvm.org/D19767 llvm-svn: 268376
* [CLANG][AVX512][BUILTIN]movap{d|s}{128|256|512}Michael Zuckerman2016-05-021-0/+48
| | | | | | Differential Revision: http://reviews.llvm.org/D17818 llvm-svn: 268230
* [Clang][BuiltIn][avx512] Adding intrinsics for vpshufd instruction setMichael Zuckerman2016-05-021-0/+25
| | | | | | Differential Revision: http://reviews.llvm.org/D19580 llvm-svn: 268213
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