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* [NVPTX] added match.{any,all}.sync instructions, intrinsics & builtins.Artem Belevich2017-09-251-3/+29
| | | | | | Differential Revision: https://reviews.llvm.org/D38191 llvm-svn: 314135
* [CUDA] Fix names of __nvvm_vote* intrinsics.Artem Belevich2017-09-251-5/+5
| | | | | | | | Also fixed a syntax error in activemask(). Differential Revision: https://reviews.llvm.org/D38188 llvm-svn: 314129
* fixing a bug in mask[z]_set1 intrinsicJina Nahias2017-09-251-2/+2
| | | | | | | Differential Revision: https://reviews.llvm.org/D38231 Change-Id: I80bbff9cbe93e4be54d8a761ef9723edf3f57c57 llvm-svn: 314102
* [CUDA] Fixed order of words in the names of shfl builtins.Artem Belevich2017-09-211-4/+3
| | | | | | Differential Revision: https://reviews.llvm.org/D38147 llvm-svn: 313899
* [NVPTX] Implemented bar.warp.sync, barrier.sync, and vote{.sync} ↵Artem Belevich2017-09-211-0/+31
| | | | | | | | instructions/intrinsics/builtins. Differential Revision: https://reviews.llvm.org/D38148 llvm-svn: 313898
* [NVPTX] Implemented shfl.sync instruction and supporting intrinsics/builtins.Artem Belevich2017-09-201-0/+68
| | | | | | Differential Revision: https://reviews.llvm.org/D38090 llvm-svn: 313820
* Lowering Mask Set1 intrinsics to LLVM IRJina Nahias2017-09-194-90/+101
| | | | | | | | This patch, together with a matching llvm patch (https://reviews.llvm.org/D37669), implements the lowering of X86 mask set1 intrinsics to IR. Differential Revision: https://reviews.llvm.org/D37668 llvm-svn: 313624
* [X86] Disable _mm512_maskz_set1_epi64 intrinsic on 32-bit targets to prevent ↵Craig Topper2017-09-151-7/+2
| | | | | | | | | | | | a backend isel failure. The __builtin_ia32_pbroadcastq512_mem_mask we were previously trying to use in 32-bit mode is not implemented in the x86 backend and causes isel to fail in release builds. In debug builds it fails even earlier during legalization with an llvm_unreachable. While there add the missing test case for this intrinsic for this for 64-bit mode. This fixes PR34631. D37668 should be able to recover this for 32-bit mode soon. But I wanted to fix the crash ahead of that. llvm-svn: 313392
* [CUDA] Work around a new quirk in CUDA9 headers.Artem Belevich2017-09-151-0/+10
| | | | | | | | | | In CUDA-9 some of device-side math functions that we need are conditionally defined within '#if _GLIBCXX_MATH_H'. We need to temporarily undo the guard around inclusion of math_functions.hpp. Differential Revision: https://reviews.llvm.org/D37906 llvm-svn: 313369
* [Headers] Fix the return type of _InterlockedCompareExchange_relMartin Storsjo2017-09-141-1/+1
| | | | | | This was a typo in SVN r282447, where it was added. llvm-svn: 313232
* This adds the _Float16 preprocessor macro definitions.Sjoerd Meijer2017-09-131-0/+14
| | | | | | Differential Revision: https://reviews.llvm.org/D34695 llvm-svn: 313152
* [X86] Lower _mm[256|512]_[mask[z]]_avg_epu[8|16] intrinsics to native llvm IRYael Tsafrir2017-09-123-28/+42
| | | | | | Differential Revision: https://reviews.llvm.org/D37562 llvm-svn: 313011
* [CUDA] Added rudimentary support for CUDA-9 and sm_70.Artem Belevich2017-09-071-1/+8
| | | | | | | | | | | | | For now CUDA-9 is not included in the list of CUDA versions clang searches for, so the path to CUDA-9 must be explicitly passed via --cuda-path=. On LLVM side NVPTX added sm_70 GPU type which bumps required PTX version to 6.0, but otherwise is equivalent to sm_62 at the moment. Differential Revision: https://reviews.llvm.org/D37576 llvm-svn: 312734
* [CUDA] Add device overloads for non-placement new/delete.Justin Lebar2017-09-071-1/+50
| | | | | | | | | | | | | | | | Summary: Tests have to live in the test-suite, and so will come in a separate patch. Fixes PR34360. Reviewers: tra Subscribers: llvm-commits, sanjoy Differential Revision: https://reviews.llvm.org/D37539 llvm-svn: 312681
* [X86][AVX512] _mm512_stream_load_si512 should take a void const* argument ↵Simon Pilgrim2017-09-051-1/+1
| | | | | | | | | | | | (PR33977) Based off the Intel Intrinsics guide, we should expect a void const* argument. Prevents 'passing 'const void *' to parameter of type 'void *' discards qualifiers' warnings. Differential Revision: https://reviews.llvm.org/D37449 llvm-svn: 312523
* [X86] Implement broadcastf32x2 and broadcasti32x2 intrinsics using ↵Craig Topper2017-08-302-45/+47
| | | | | | | | | | __builtin_shufflevector instead builtins This patch implements the broadcastf32x2/broadcasti32x2 intrinsics using __builtin_shufflevector. Differential Revision: https://reviews.llvm.org/D37287 llvm-svn: 312135
* Headers: explicitly specify double-word alignmentSaleem Abdulrasool2017-08-231-1/+1
| | | | | | | | GCC will interpret `__attribute__((__aligned__))` as 8-byte alignment on ARM, but clang will not. Explicitly specify the alignment. This mirrors the declaration in libunwind. llvm-svn: 311576
* Headers: give _Unwind_Control_Block double-word alignmentSaleem Abdulrasool2017-08-231-1/+1
| | | | | | | | | | The C++ ABI requires that the exception object (which under AEABI is the `_Unwind_Control_Block`) is double-word aligned. The attribute was applied to the `_Unwind_Exception` type, but not the `_Unwind_Control_Block`. This should fix the libunwind test for the alignment of the exception type. llvm-svn: 311563
* [OpenCL] Remove extra select functions from opencl-c.hYaxun Liu2017-08-051-324/+10
| | | | | | | | | | | | | | | | | | | OpenCL spec v2.0 s6.13.6: gentype select (gentype a, gentype b, igentype c) gentype select (gentype a, gentype b, ugentype c) igentype and ugentype must have the same number of elements and bits as gentype. Differential Revision: https://reviews.llvm.org/D36259 llvm-svn: 310160
* Add OpenCL 2.0 atomic builtin functions as Clang builtinYaxun Liu2017-08-041-12/+13
| | | | | | | | | | | | | | | | | | | | | OpenCL 2.0 atomic builtin functions have a scope argument which is ideally represented as synchronization scope argument in LLVM atomic instructions. Clang supports translating Clang atomic builtin functions to LLVM atomic instructions. However it currently does not support synchronization scope of LLVM atomic instructions. Without this, users have to use LLVM assembly code to implement OpenCL atomic builtin functions. This patch adds OpenCL 2.0 atomic builtin functions as Clang builtin functions, which supports generating LLVM atomic instructions with synchronization scope operand. Currently only constant memory scope argument is supported. Support of non-constant memory scope argument will be added later. Differential Revision: https://reviews.llvm.org/D28691 llvm-svn: 310082
* [Headers][Darwin] Allow #include_next<float.h> to work on Darwin prior to 10.7Bruno Cardoso Lopes2017-08-011-0/+9
| | | | | | | | | This fixes PR31504 and it's a follow up from adding #include_next<float.h> for Darwin in r289018. rdar://problem/29856682 llvm-svn: 309752
* [X86][AVX] Ensure vector non-temporal load/store intrinsics force pointer ↵Simon Pilgrim2017-07-293-8/+16
| | | | | | | | | | | | alignment (PR33830) Clang specifies a max type alignment of 16 bytes on darwin targets (annoyingly in the driver not via cc1), meaning that the builtin nontemporal stores don't correctly align the loads/stores to 32 or 64 bytes when required, resulting in lowering to temporal unaligned loads/stores. This patch casts the vectors to explicitly aligned types prior to the load/store to ensure that the require alignment is respected. Differential Revision: https://reviews.llvm.org/D35996 llvm-svn: 309488
* Strip trailing whitespace. NFCI.Simon Pilgrim2017-07-281-30/+30
| | | | llvm-svn: 309383
* Headers: fix _Unwind_{G,S}etGR for non-EHABI targetsSaleem Abdulrasool2017-07-271-4/+1
| | | | | | | | The EHABI definition was being inlined into the users even when EHABI was not in use. Adjust the condition to ensure that the right version is defined. llvm-svn: 309327
* Headers: improve ARM EHABI coverage of unwind.hSaleem Abdulrasool2017-07-261-17/+58
| | | | | | | | | | | | | | | | Ensure that we define the `_Unwind_Control_Block` structure used on ARM EHABI targets. This is needed for building libc++abi with the unwind.h from the resource dir. A minor fallout of this is that we needed to create a typedef for _Unwind_Exception to work across ARM EHABI and non-EHABI targets. The structure definitions here are based originally on the documentation from ARM under the "Exception Handling ABI for the ARM® Architecture" Section 7.2. They are then adjusted to more closely reflect the definition in libunwind from LLVM. Those changes are compatible in layout but permit easier use in libc++abi and help maintain compatibility between libunwind and the compiler provided definition. llvm-svn: 309226
* [clang] Add ARM64 support to armintr.h for MSVC compatibilityMandeep Singh Grang2017-07-263-0/+54
| | | | | | | | | | | | | | Summary: This fixes compiling with headers from the Windows SDK for ARM64. Reviewers: compnerd, ruiu, mstorsjo Reviewed By: compnerd, mstorsjo Subscribers: mgorny, aemerson, javed.absar, kristof.beyls, llvm-commits, cfe-commits Differential Revision: https://reviews.llvm.org/D35862 llvm-svn: 309081
* [SystemZ] Add support for IBM z14 processor (3/3)Ulrich Weigand2017-07-171-24/+1548
| | | | | | | | | | | | | This patch updates the vecintrin.h header file to provide the new set of high-level vector built-in functions. This matches the updated definition implemented by other compilers for the platform, indicated by the pre-defined macro __VEC__ == 10302. Note that some of the new functions (notably those involving the vector float data type) are only available with -march=z14 (indicated by __ARCH__ == 12). llvm-svn: 308199
* [DOXYGEN] Corrected typos and incorrect parameters description.Ekaterina Romanova2017-07-122-2/+2
| | | | | | | | | | Corrected several typos and incorrect parameters description that Sony 's techinical writer found during review. I got an OK from Eric Christopher to commit doxygen comments without prior code review upstream. llvm-svn: 307838
* X86 Intrinsics: _bit_scan_forward should not be under #ifdef __RDRND__Zvi Rackover2017-07-101-9/+9
| | | | | | | | | | | | | | | | | | | | Summary: The _bit_scan_forward and _bit_scan_reverse intrinsics were accidentally masked under the preprocessor checks that prune intrinsics definitions for the benefit of faster compile-time on Windows. This patch moves the definitons out of that region. Fixes pr33722 Reviewers: craig.topper, aaboud, thakis Reviewed By: craig.topper Subscribers: cfe-commits Differential Revision: https://reviews.llvm.org/D35184 llvm-svn: 307524
* [X86] Add more feature flag bit defines to cpuid.h for gcc compatibility.Craig Topper2017-07-091-3/+61
| | | | llvm-svn: 307507
* [X86] Add __get_cpuid_count to cpuid.h. Update __get_cpuid to check the ↵Craig Topper2017-07-091-17/+37
| | | | | | | | maximum level support before accessing the leaf. Rename level to leaf everywhere. This matches gcc behavior. llvm-svn: 307506
* [DOXYGEN] Corrected several typos and incorrect parameters description that ↵Ekaterina Romanova2017-06-064-9/+35
| | | | | | | | | Sony's techinical writer found during review. I got an OK from Eric Christopher to commit doxygen comments without prior code review upstream. llvm-svn: 304840
* [PPC] Make altivec conversion function macros.Benjamin Kramer2017-05-301-57/+49
| | | | | | | | | | The second argument must be a constant, otherwise instruction selection will fail. always_inline is not enough for isel to always fold everything away at -O0. Sadly the overloading turned this into a big macro mess. Fixes PR33212. llvm-svn: 304205
* [X86] Adding avx512_vpopcntdq feature set and its intrinsicsOren Ben Simhon2017-05-253-0/+75
| | | | | | | | | | AVX512_VPOPCNTDQ is a new feature set that was published by Intel. The patch represents the Clang side of the addition of six intrinsics for two new machine instructions (vpopcntd and vpopcntq). It also includes the addition of the new feature set. Differential Revision: https://reviews.llvm.org/D33170 llvm-svn: 303857
* [PowerPC] Implement vec_xxsldwi builtin.Tony Jiang2017-05-241-0/+1
| | | | | | | | | | The vec_xxsldwi builtin is missing from altivec.h. This has been requested by developers working on libvpx for VP9 support for Google. The patch fixes PR: https://bugs.llvm.org/show_bug.cgi?id=32653 Differential Revision: https://reviews.llvm.org/D33236 llvm-svn: 303766
* [PowerPC] Implement vec_xxpermdi builtin.Tony Jiang2017-05-241-0/+4
| | | | | | | | | | The vec_xxpermdi builtin is missing from altivec.h. This has been requested by developers working on libvpx for VP9 support for Google. The patch fixes PR: https://bugs.llvm.org/show_bug.cgi?id=32653 Differential Revision: https://reviews.llvm.org/D33053 llvm-svn: 303760
* (1) Fixed mismatch in intrinsics names in declarations and in doxygen comments.Ekaterina Romanova2017-05-171-16/+9
| | | | | | | | | (2) Removed uncessary anymore \c commands, since the same effect will be achived by <c> ... </c> sequence. I got an OK from Eric Christopher to commit doxygen comments without prior code review upstream. llvm-svn: 303228
* [DOXYGEN] Minor improvements in doxygen comments.Ekaterina Romanova2017-05-158-274/+432
| | | | | | | | | Separated very long brief sections into two sections. I got an OK from Eric Christopher to commit doxygen comments without prior code review upstream. llvm-svn: 303031
* [OpenCL] Added checking OpenCL version for cl_khr_mipmap_image built-insEgor Churaev2017-05-101-4/+10
| | | | | | | | | | | | Reviewers: Anastasia, cfe-commits Reviewed By: Anastasia Subscribers: bader, yaxunl Differential Revision: https://reviews.llvm.org/D32897 llvm-svn: 302630
* [X86][LWP] Remove MSVC LWP intrinsics stubs.Simon Pilgrim2017-05-091-6/+0
| | | | | | Now provided in lwpintrin.h llvm-svn: 302559
* [X86][LWP] Removing LWP todo comment. NFCI.Simon Pilgrim2017-05-091-2/+0
| | | | | | LWP / lwpintrin.h is now supported llvm-svn: 302557
* [X86][LWP] Add clang support for LWP instructions.Simon Pilgrim2017-05-083-0/+155
| | | | | | | | This patch adds support for the the LightWeight Profiling (LWP) instructions which are available on all AMD Bulldozer class CPUs (bdver1 to bdver4). Differential Revision: https://reviews.llvm.org/D32770 llvm-svn: 302418
* [ARM] ACLE Chapter 9 intrinsicsSam Parker2017-05-041-2/+316
| | | | | | | | | | Implemented the remaining integer data processing intrinsics from the ARM ACLE v2.1 spec, such as parallel arithemtic and DSP style multiplications. Differential Revision: https://reviews.llvm.org/D32282 llvm-svn: 302131
* [X86][AVX] Added support for _mm256_zext* helper intrinsics (PR32839)Simon Pilgrim2017-04-292-0/+165
| | | | llvm-svn: 301749
* [DOXYGEN] Minor improvements in doxygen comments.Ekaterina Romanova2017-04-281-166/+0
| | | | | | | | | | | | - I removed doxygen comments for the intrinsics that "alias" the other existing documented intrinsics and that only sligtly differ in spelling (single underscores vs. double underscores). #define _tzcnt_u16(a) (__tzcnt_u16((a))) It will be very hard to keep the documentation for these "aliases" in sync with the documentation for the intrinsics they alias to. Out of sync documentation will be more confusing than no documentation. I got an OK from Eric Christopher to commit doxygen comments without prior code review upstream. llvm-svn: 301652
* [X86][SSE] Add _mm_set_pd1 (PR32827)Simon Pilgrim2017-04-281-0/+18
| | | | | | Matches _mm_set_ps1 implementation llvm-svn: 301637
* Headers: Make the type of SIZE_MAX the same as size_tDuncan P. N. Exon Smith2017-04-271-16/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | size_t is usually defined as unsigned long, but on 64-bit platforms, stdint.h currently defines SIZE_MAX using "ull" (unsigned long long). Although this is the same width, it doesn't necessarily have the same alignment or calling convention. It also triggers printf warnings when using the format flag "%zu" to print SIZE_MAX. This changes SIZE_MAX to reuse the compiler-provided __SIZE_MAX__, and provides similar fixes for the other integers: - INTPTR_MIN - INTPTR_MAX - UINTPTR_MAX - PTRDIFF_MIN - PTRDIFF_MAX - INTMAX_MIN - INTMAX_MAX - UINTMAX_MAX - INTMAX_C() - UINTMAX_C() ... and fixes the typedefs for intptr_t and uintptr_t to use __INTPTR_TYPE__ and __UINTPTR_TYPE__ instead of int32_t, effectively reverting r89224, r89226, and r89237 (r89221 already having been effectively reverted). We can probably also kill __INTPTR_WIDTH__, __INTMAX_WIDTH__, and __UINTMAX_WIDTH__ in a follow-up, but I was hesitant to delete all the per-target CHECK lines in this commit since those might serve their own purpose. rdar://problem/11811377 llvm-svn: 301593
* Use __CLANG_ATOMIC_TYPE_LOCK_FREE macros in `stdatomic.h`Eric Fiselier2017-04-201-10/+10
| | | | | | | | | | | | | | Summary: This patch makes the header `stdatomic.h` work when `-fms-compatibility` is specified. Reviewers: rsmith Reviewed By: rsmith Subscribers: cfe-commits Differential Revision: https://reviews.llvm.org/D32322 llvm-svn: 300919
* [DOXYGEN] Minor improvements in doxygen comments.Ekaterina Romanova2017-04-182-149/+92
| | | | | | | | | | | - To be consistent with the rest of the intrinsics headers, I removed the tags <i> .. </i> for marking instruction names in italics in in smmintrin.h. - Formatting changes to fit into 80 characters. I got an OK from Eric Christopher to commit doxygen comments without prior code review upstream. llvm-svn: 300578
* [X86][SSE] Update MOVNTDQA non-temporal loads to generic implementation (clang)Simon Pilgrim2017-04-143-3/+3
| | | | | | | | | | MOVNTDQA non-temporal aligned vector loads can be correctly represented using generic builtin loads, allowing us to remove the existing x86 intrinsics. LLVM companion patch: D31767. Differential Revision: https://reviews.llvm.org/D31766 llvm-svn: 300326
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