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* OpenCL: Use length modifier for warning on vector printf argumentsMatt Arsenault2019-01-291-1/+1
| | | | | | | | | | | | Re-enable format string warnings on printf. The warnings are still incomplete. Apparently it is undefined to use a vector specifier without a length modifier, which is not currently warned on. Additionally, type warnings appear to not be working with the hh modifier, and aren't warning on all of the special restrictions from c99 printf. llvm-svn: 352540
* Revert "OpenCL: Extend argument promotion rules to vector types"Matt Arsenault2019-01-291-1/+1
| | | | | | | | | | | | This reverts r348083. This was based on a misreading of the spec for printf specifiers. Also revert r343653, as without a subsequent patch, a correctly specified format for a vector will incorrectly warn. Fixes bug 40491. llvm-svn: 352539
* [X86] Remove mask and passthru arguments from vpconflict builtins. Use ↵Craig Topper2019-01-252-56/+42
| | | | | | select in IR instead. llvm-svn: 352173
* [X86] Remove the cvtuqq2ps256/cvtqq2ps256 mask builtins. Replace with ↵Craig Topper2019-01-201-18/+14
| | | | | | | | | | | | | | uitofp/sitofp and select. Reviewers: RKSimon, spatel Reviewed By: RKSimon Subscribers: kristina, cfe-commits Differential Revision: https://reviews.llvm.org/D56965 llvm-svn: 351694
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
| | | | | | | | | | | | | | | | | to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
* [X86] Only define _XCR_XFEATURE_ENABLED_MASK in xsaveintrin.h when _MSC_VER ↵Craig Topper2019-01-182-2/+1
| | | | | | | | is defined. Remove from intrin.h. I think this was my intention when I added it xsaveintrin.h llvm-svn: 351568
* Recommit r351160 "[X86] Make _xgetbv/_xsetbv on non-windows platforms"Craig Topper2019-01-163-11/+20
| | | | | | V8 has been fixed now. llvm-svn: 351391
* Revert "[X86] Make _xgetbv/_xsetbv on non-windows platforms"Benjamin Kramer2019-01-153-20/+11
| | | | | | This reverts commit r351160. Breaks building v8. llvm-svn: 351210
* [OpenCL] opencl-c.h: read_image*(): sampler-less, and image{1,2}d_array_t ↵Roman Lebedev2019-01-151-2/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | variants are OpenCL-1.2+, mark them as such Summary: Refer to [[ https://www.khronos.org/registry/OpenCL/specs/opencl-1.1.pdf#page=242 | `6.11.13.2 Built-in Image Functions` ]], and [[ https://www.khronos.org/registry/OpenCL/specs/opencl-1.1.pdf#page=306 | `9.6.8 Image Read and Write Functions` ]] of the OpenCL 1.1 spec. * There is no mention of `image1d_array_t` and `image2d_array_t` anywhere in the OpenCL 1.1 spec. * All the `read_image{f,i,ui,h}()` functions, as of OpenCL 1.1 spec, have a second required parameter `sampler_t sampler` Should have prevented the following regression: https://redmine.darktable.org/issues/12493 Reviewers: yaxunl, Anastasia, echuraev, asavonic Reviewed By: Anastasia Subscribers: cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D56646 llvm-svn: 351188
* [X86] Make _xgetbv/_xsetbv on non-windows platformsCraig Topper2019-01-153-11/+20
| | | | | | | | | | | | | | | | | | | | | | | Summary: This patch attempts to redo what was tried in r278783, but was reverted. These intrinsics should be available on non-windows platforms with "xsave" feature check. But on Windows platforms they shouldn't have feature check since that's how MSVC behaves. To accomplish this I've added a MS builtin with no feature check. And a normal gcc builtin with a feature check. When _MSC_VER is not defined _xgetbv/_xsetbv will be macros pointing to the gcc builtin name. I've moved the forward declarations from intrin.h to immintrin.h to match the MSDN documentation and used that as the header file for the MS builtin. I'm not super happy with this implementation, and I'm open to suggestions for better ways to do it. Reviewers: rnk, RKSimon, spatel Reviewed By: rnk Subscribers: cfe-commits Differential Revision: https://reviews.llvm.org/D56686 llvm-svn: 351160
* [COFF, ARM64] Add __byteswap intrinsicsMandeep Singh Grang2019-01-151-0/+10
| | | | | | | | | | | | Reviewers: rnk, efriedma, ssijaric, TomTan, haripul Reviewed By: efriedma Subscribers: javed.absar, cfe-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D56685 llvm-svn: 351147
* [COFF, ARM64] Add __nop intrinsicMandeep Singh Grang2019-01-141-0/+3
| | | | | | | | | | | | Reviewers: rnk, efriedma, TomTan, haripul, ssijaric Reviewed By: rnk, efriedma Subscribers: javed.absar, kristof.beyls, cfe-commits Differential Revision: https://reviews.llvm.org/D56671 llvm-svn: 351135
* [X86] Remove mask parameter from avx512 pmultishiftqb intrinsics. Use select ↵Craig Topper2019-01-142-49/+33
| | | | | | | | in IR instead. Fixes PR40259 llvm-svn: 351036
* [X86] Make the pointer arguments to avx512 gather/scatter intrinsics 'void*' ↵Craig Topper2019-01-093-96/+96
| | | | | | | | to match gcc and Intel's documentation. The avx2 gather intrinsics are documented to use 'int', 'long long', 'float', or 'double' *. So I'm leaving those. This matches gcc. llvm-svn: 350696
* Recommit r350555 "[X86] Use funnel shift intrinsics for the VBMI2 ↵Craig Topper2019-01-072-272/+198
| | | | | | | | vshld/vshrd builtins." The MSVC limit hit in AutoUpgrade.cpp has been worked around for now. llvm-svn: 350568
* Revert r350555 "[X86] Use funnel shift intrinsics for the VBMI2 vshld/vshrd ↵Craig Topper2019-01-072-198/+272
| | | | | | | | builtins." Had to revert the LLVM patch this depends on to fix a MSVC compiler limit in AutoUpgrade.cpp llvm-svn: 350563
* [X86] Use funnel shift intrinsics for the VBMI2 vshld/vshrd builtins.Craig Topper2019-01-072-272/+198
| | | | | | Differential Revision: https://reviews.llvm.org/D56365 llvm-svn: 350555
* [SystemZ] Fix wrong codegen caused by typos in vecintrin.hUlrich Weigand2018-12-201-3/+3
| | | | | | | | | | | | | | | The following two bugs in SystemZ high-level vector intrinsics are fixes by this patch: - The float case of vec_insert_and_zero should generate a VLLEZF pattern, but currently erroneously generates VLLEZLF. - The float and double versions of vec_orc erroneously generate and-with-complement instead of or-with-complement. The patch also fixes a couple of typos in the associated test. llvm-svn: 349751
* [Builltins][X86] Provide implementations of __lzcnt16, __lzcnt, __lzcnt64 ↵Craig Topper2018-12-142-13/+6
| | | | | | | | | | | | | | | | | | for MS compatibility. Remove declarations from intrin.h and implementations from lzcntintrin.h intrin.h had forward declarations for these and lzcntintrin.h had implementations that were only available with -mlzcnt or a -march that supported the lzcnt feature. For MS compatibility we should always have these builtins available regardless of X86 being the target or the CPU support the lzcnt instruction. The backends should be able to gracefully fallback to something support even if its just shifts and bit ops. Unfortunately, gcc also implements 2 of the 3 function names here on X86 when lzcnt feature is enabled. This patch adds builtins for these for MSVC compatibility and drops the forward declarations from intrin.h. To keep the gcc compatibility the two intrinsics that collided have been turned into macros that use the X86 specific builtins with the lzcnt feature check. These macros are only defined when _MSC_VER is not defined. Without them being macros we can get a redefinition error because -ms-extensions doesn't seem to set _MSC_VER but does make the MS builtins available. Should fix PR40014 Differential Revision: https://reviews.llvm.org/D55677 llvm-svn: 349098
* [X86] Remove the addcarry builtins. Leaving only the addcarryx builtins ↵Craig Topper2018-12-101-2/+2
| | | | | | | | | | since that matches gcc. The addcarry and addcarryx builtins do the same thing. The only difference is that addcarryx previously required adx feature. This commit removes the adx feature check from addcarryx and removes the addcarry builtin. This matches the builtins that gcc has. We don't guarantee compatibility in builtins, but we generally try to be consistent if its not a burden. llvm-svn: 348738
* [CUDA] Added missing 'inline' for functions defined in a header.Artem Belevich2018-12-071-2/+4
| | | | llvm-svn: 348662
* [CMake] Store path to vendor-specific headers in clang-headers target propertyStefan Granitz2018-12-031-2/+4
| | | | | | | | | | | | | | | | | | | | | Summary: LLDB.framework wants a copy these headers. With this change LLDB can easily glob for the list of files: ``` get_target_property(clang_include_dir clang-headers RUNTIME_OUTPUT_DIRECTORY) file(GLOB_RECURSE clang_vendor_headers RELATIVE ${clang_include_dir} "${clang_include_dir}/*") ``` By default `RUNTIME_OUTPUT_DIRECTORY` is unset for custom targets like `clang-headers`. Reviewers: aprantl, JDevlieghere, davide, friss, dexonsmith Reviewed By: JDevlieghere Subscribers: mgorny, #lldb, cfe-commits, llvm-commits Differential Revision: https://reviews.llvm.org/D55128 llvm-svn: 348116
* [PowerPC] Vector load/store builtins overstate alignment of pointersNemanja Ivanovic2018-11-261-24/+39
| | | | | | | | | | | | | A number of builtins in altivec.h load/store vectors from pointers to scalar types. Currently they just cast the pointer to a vector pointer, but expressions like that have the alignment of the target type. Of course, the input pointer did not have that alignment so this triggers UBSan (and rightly so). This resolves https://bugs.llvm.org/show_bug.cgi?id=39704 Differential revision: https://reviews.llvm.org/D54787 llvm-svn: 347556
* [PowerPC] [Clang] [AltiVec] The second parameter of vec_sr function should ↵Zi Xuan Wu2018-11-091-29/+31
| | | | | | | | | | | | | | | | be modulo the number of bits in the element The second parameter of vec_sr function is representing shift bits and it should be modulo the number of bits in the element like what vec_sl does now. This is actually required by the ABI: Each element of the result vector is the result of logically right shifting the corresponding element of ARG1 by the number of bits specified by the value of the corresponding element of ARG2, modulo the number of bits in the element. The bits that are shifted out are replaced by zeros. Differential Revision: https://reviews.llvm.org/D54087 llvm-svn: 346471
* [OpenCL] Add support of cl_intel_device_side_avc_motion_estimation extensionAndrew Savonichev2018-11-081-0/+631
| | | | | | | | | | | | | | | | | | Summary: Documentation can be found at https://www.khronos.org/registry/OpenCL/extensions/intel/cl_intel_device_side_avc_motion_estimation.txt Patch by Kristina Bessonova Reviewers: Anastasia, yaxunl, shafik Reviewed By: Anastasia Subscribers: arphaman, sidorovd, AlexeySotkin, krisb, bader, asavonic, cfe-commits Differential Revision: https://reviews.llvm.org/D51484 llvm-svn: 346392
* Revert r346326 [OpenCL] Add support of ↵Andrew Savonichev2018-11-071-631/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | cl_intel_device_side_avc_motion_estimation This patch breaks Index/opencl-types.cl LIT test: Script: -- : 'RUN: at line 1'; stage1/bin/c-index-test -test-print-type llvm/tools/clang/test/Index/opencl-types.cl -cl-std=CL2.0 | stage1/bin/FileCheck llvm/tools/clang/test/Index/opencl-types.cl -- Command Output (stderr): -- llvm/tools/clang/test/Index/opencl-types.cl:3:26: warning: unsupported OpenCL extension 'cl_khr_fp16' - ignoring [-Wignored-pragmas] llvm/tools/clang/test/Index/opencl-types.cl:4:26: warning: unsupported OpenCL extension 'cl_khr_fp64' - ignoring [-Wignored-pragmas] llvm/tools/clang/test/Index/opencl-types.cl:8:9: error: use of type 'double' requires cl_khr_fp64 extension to be enabled llvm/tools/clang/test/Index/opencl-types.cl:11:8: error: declaring variable of type 'half' is not allowed llvm/tools/clang/test/Index/opencl-types.cl:15:3: error: use of type 'double' requires cl_khr_fp64 extension to be enabled llvm/tools/clang/test/Index/opencl-types.cl:16:3: error: use of type 'double4' (vector of 4 'double' values) requires cl_khr_fp64 extension to be enabled llvm/tools/clang/test/Index/opencl-types.cl:26:26: warning: unsupported OpenCL extension 'cl_khr_gl_msaa_sharing' - ignoring [-Wignored-pragmas] llvm/tools/clang/test/Index/opencl-types.cl:35:44: error: use of type '__read_only image2d_msaa_t' requires cl_khr_gl_msaa_sharing extension to be enabled llvm/tools/clang/test/Index/opencl-types.cl:36:49: error: use of type '__read_only image2d_array_msaa_t' requires cl_khr_gl_msaa_sharing extension to be enabled llvm/tools/clang/test/Index/opencl-types.cl:37:49: error: use of type '__read_only image2d_msaa_depth_t' requires cl_khr_gl_msaa_sharing extension to be enabled llvm/tools/clang/test/Index/opencl-types.cl:38:54: error: use of type '__read_only image2d_array_msaa_depth_t' requires cl_khr_gl_msaa_sharing extension to be enabled llvm-svn: 346338
* [OpenCL] Add support of cl_intel_device_side_avc_motion_estimation extensionAndrew Savonichev2018-11-071-0/+631
| | | | | | | | | | | | | | | | | | Summary: Documentation can be found at https://www.khronos.org/registry/OpenCL/extensions/intel/cl_intel_device_side_avc_motion_estimation.txt Patch by Kristina Bessonova Reviewers: Anastasia, yaxunl, shafik Reviewed By: Anastasia Subscribers: arphaman, sidorovd, AlexeySotkin, krisb, bader, asavonic, cfe-commits Differential Revision: https://reviews.llvm.org/D51484 llvm-svn: 346326
* [MS] Zero out ECX in __cpuid in intrin.hReid Kleckner2018-11-061-1/+1
| | | | | | | | | | | | | | | | Summary: Some CPUID leafs depend on the value of ECX as well as EAX, but we left it uninitialized. Originally reported as https://crbug.com/901547 Reviewers: craig.topper, hans Subscribers: cfe-commits Differential Revision: https://reviews.llvm.org/D54171 llvm-svn: 346265
* [COFF, ARM64] Implement InterlockedDecrement*_* builtinsMandeep Singh Grang2018-11-061-36/+9
| | | | | | | This is eight in a series of patches to move intrinsic definitions out of intrin.h. Differential: https://reviews.llvm.org/D54068 llvm-svn: 346208
* [COFF, ARM64] Implement InterlockedIncrement*_* builtinsMandeep Singh Grang2018-11-061-36/+9
| | | | | | | This is seventh in a series of patches to move intrinsic definitions out of intrin.h. Differential: https://reviews.llvm.org/D54067 llvm-svn: 346207
* [COFF, ARM64] Implement InterlockedAnd*_* builtinsMandeep Singh Grang2018-11-061-48/+12
| | | | | | | This is sixth in a series of patches to move intrinsic definitions out of intrin.h. Differential: https://reviews.llvm.org/D54066 llvm-svn: 346206
* [COFF, ARM64] Implement InterlockedXor*_* builtinsMandeep Singh Grang2018-11-061-48/+12
| | | | | | | | | This is fifth in a series of patches to move intrinsic definitions out of intrin.h. Note: This was reviewed and approved in D54065 but somehow that diff was messed up. Committing this again with the proper diff. llvm-svn: 346205
* Revert "[COFF, ARM64] Implement InterlockedXor*_* builtins"Mandeep Singh Grang2018-11-061-0/+735
| | | | | | This reverts commit cc3d3cd0fbeb88412d332354c261ff139c4ede6b. llvm-svn: 346192
* [COFF, ARM64] Implement InterlockedXor*_* builtinsMandeep Singh Grang2018-11-061-735/+0
| | | | | | | | | | | | | | Summary: This is fifth in a series of patches to move intrinsic definitions out of intrin.h. Reviewers: rnk, efriedma, mstorsjo, TomTan Reviewed By: efriedma Subscribers: javed.absar, kristof.beyls, chrib, jfb, kristina, cfe-commits Differential Revision: https://reviews.llvm.org/D54065 llvm-svn: 346191
* [COFF, ARM64] Implement InterlockedOr*_* builtinsMandeep Singh Grang2018-11-061-48/+12
| | | | | | This is fourth in a series of patches to move intrinsic definitions out of intrin.h. llvm-svn: 346190
* [COFF, ARM64] Implement InterlockedCompareExchange*_* builtinsMandeep Singh Grang2018-11-061-84/+24
| | | | | | | | | | | | | | Summary: This is third in a series of patches to move intrinsic definitions out of intrin.h. Reviewers: rnk, efriedma, mstorsjo, TomTan Reviewed By: efriedma Subscribers: javed.absar, kristof.beyls, chrib, jfb, kristina, cfe-commits Differential Revision: https://reviews.llvm.org/D54062 llvm-svn: 346189
* [COFF, ARM64] Implement InterlockedExchange*_* builtinsMandeep Singh Grang2018-11-021-60/+12
| | | | | | | | | | | | | | Summary: Windows SDK needs these intrinsics to be proper builtins. This is second in a series of patches to move intrinsic defintions out of intrin.h. Reviewers: rnk, mstorsjo, efriedma, TomTan Reviewed By: rnk, efriedma Subscribers: javed.absar, kristof.beyls, chrib, jfb, kristina, cfe-commits Differential Revision: https://reviews.llvm.org/D54046 llvm-svn: 346044
* [ARM64] [Windows] Implement _InterlockedExchangeAdd*_* builtins.Eli Friedman2018-10-311-48/+12
| | | | | | | | | These apparently need to be proper builtins to handle the Windows SDK. Differential Revision: https://reviews.llvm.org/D53916 llvm-svn: 345779
* [OpenCL] Remove PIPE_RESERVE_ID_VALID_BIT from opencl-c.hAndrew Savonichev2018-10-231-1/+0
| | | | | | | | | | | | | | | | | Summary: PIPE_RESERVE_ID_VALID_BIT is implementation defined, so lets not keep it in the header. Previously the topic was discussed here: https://reviews.llvm.org/D32896 Reviewers: Anastasia, yaxunl Reviewed By: Anastasia Subscribers: cfe-commits, asavonic, bader Differential Revision: https://reviews.llvm.org/D52658 llvm-svn: 345051
* [OpenCL] Add cl_intel_planar_yuv extensionAndrew Savonichev2018-10-231-0/+8
| | | | | | | | | | Just adding a preprocessor #define for the extension. Patch by Alexey Sotkin and Dmitry Sidorov Phabricator review: https://reviews.llvm.org/D51402 llvm-svn: 345044
* [X86] Add more intrinsics to match icc.Craig Topper2018-10-202-1/+111
| | | | | | | | | | This adds _mm_loadu_epi8, _mm256_loadu_epi8, _mm512_loadu_epi8 _mm_loadu_epi16, _mm256_loadu_epi16, _mm512_loadu_epi16 _mm_storeu_epi8, _mm256_storeu_epi8, _mm512_storeu_epi8 _mm_storeu_epi16, _mm256_storeu_epi16, _mm512_storeu_epi16 llvm-svn: 344862
* [X86] Add missing intrinsics to match icc.Craig Topper2018-10-202-19/+270
| | | | | | | | | | | | | | | | | | | | | | | | | | This adds _mm_and_epi32, _mm_and_epi64 _mm_andnot_epi32, _mm_andnot_epi64 _mm_or_epi32, _mm_or_epi64 _mm_xor_epi32, _mm_xor_epi64 _mm256_and_epi32, _mm256_and_epi64 _mm256_andnot_epi32, _mm256_andnot_epi64 _mm256_or_epi32, _mm256_or_epi64 _mm256_xor_epi32, _mm256_xor_epi64 _mm_loadu_epi32, _mm_loadu_epi64 _mm_load_epi32, _mm_load_epi64 _mm256_loadu_epi32, _mm256_loadu_epi64 _mm256_load_epi32, _mm256_load_epi64 _mm512_loadu_epi32, _mm512_loadu_epi64 _mm512_load_epi32, _mm512_load_epi64 _mm_storeu_epi32, _mm_storeu_epi64 _mm_store_epi32, _mm_load_epi64 _mm256_storeu_epi32, _mm256_storeu_epi64 _mm256_store_epi32, _mm256_load_epi64 _mm512_storeu_epi32, _mm512_storeu_epi64 _mm512_store_epi32,V _mm512_load_epi64 llvm-svn: 344861
* [COFF, ARM64] Add _ReadStatusReg and_WriteStatusReg intrinsicsMandeep Singh Grang2018-10-181-0/+2
| | | | | | | | | | | | Reviewers: rnk, compnerd, mstorsjo, efriedma, TomTan, haripul, javed.absar Reviewed By: efriedma Subscribers: dmajor, kristof.beyls, chrib, cfe-commits Differential Revision: https://reviews.llvm.org/D53115 llvm-svn: 344765
* [COFF, ARM64] Add _InterlockedAdd intrinsicMandeep Singh Grang2018-10-051-0/+1
| | | | | | | | | | | | Reviewers: rnk, mstorsjo, compnerd, TomTan, haripul, javed.absar, efriedma Reviewed By: efriedma Subscribers: efriedma, kristof.beyls, chrib, jfb, cfe-commits Differential Revision: https://reviews.llvm.org/D52811 llvm-svn: 343894
* [COFF, ARM64] Add __getReg intrinsicMandeep Singh Grang2018-10-041-0/+7
| | | | | | | | | | | | Reviewers: rnk, mstorsjo, compnerd, TomTan, haripul, javed.absar, efriedma Reviewed By: efriedma Subscribers: peter.smith, efriedma, kristof.beyls, chrib, cfe-commits Differential Revision: https://reviews.llvm.org/D52838 llvm-svn: 343824
* OpenCL: Mark printf format string argumentMatt Arsenault2018-10-031-1/+1
| | | | | | Fixes not warning on format string errors. llvm-svn: 343653
* [X86] Add more of the icc unaligned load/store to/from 128 bit vector intrinsicsCraig Topper2018-09-291-1/+106
| | | | | | | | | | | | | | | | | | | | | | Summary: This patch adds _mm_loadu_si32 _mm_loadu_si16 _mm_storeu_si64 _mm_storeu_si32 _mm_storeu_si16 We already had _mm_load_si64. Reviewers: spatel, RKSimon Reviewed By: RKSimon Subscribers: cfe-commits Differential Revision: https://reviews.llvm.org/D52665 llvm-svn: 343388
* [X86] Add the movbe instruction intrinsics from icc.Craig Topper2018-09-281-0/+59
| | | | | | | | | | These intrinsics exist in icc. They can be found on the Intel Intrinsics Guide website. All the backend support is in place to pattern match a load+bswap or a bswap+store pattern to the MOVBE instructions. So we just need to get the frontend to emit the correct IR. The pointer arguments in icc are declared as void so I had to jump through a packed struct to forcing a specific alignment on the load/store. Same trick we use in the unaligned vector load/store intrinsics Differential Revision: https://reviews.llvm.org/D52586 llvm-svn: 343343
* [X86] For lzcnt/tzcnt intrinsics use cttz/ctlz intrinsics with zero_undef ↵Craig Topper2018-09-262-10/+10
| | | | | | | | | | | | flag set to false. Previously we used a select and the zero_undef=true intrinsic. In -O2 this pattern will get optimized to zero_undef=false. But in -O0 this optimization won't happen. This results in a compare and cmov being wrapped around a tzcnt/lzcnt instruction. By using the zero_undef=false intrinsic directly without the select, we can improve the -O0 codegen to just an lzcnt/tzcnt instruction. Differential Revision: https://reviews.llvm.org/D52392 llvm-svn: 343126
* [CUDA] Added basic support for compiling with CUDA-10.0Artem Belevich2018-09-241-1/+7
| | | | llvm-svn: 342924
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