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* Implement MS _rot intrinsicsAlbert Gutowski2016-09-081-55/+0
| | | | | | | | | | Reviewers: thakis, Prazek, compnerd, rnk Subscribers: majnemer, cfe-commits Differential Revision: https://reviews.llvm.org/D24311 llvm-svn: 280997
* Add MS __nop intrinsic to intrin.hReid Kleckner2016-09-071-0/+5
| | | | | | | | | | | | | | | Summary: There was no definition for __nop function - added inline assembly. Patch by Albert Gutowski! Reviewers: rnk, thakis Subscribers: cfe-commits Differential Revision: https://reviews.llvm.org/D24286 llvm-svn: 280826
* [AVX-512] Remove 128-bit and 256-bit masked floating point add/sub/mul/div ↵Craig Topper2016-09-041-179/+128
| | | | | | | | builtins and replace with native operations. We can't do the 512-bit ones because they take a rounding mode argument that we can't represent. llvm-svn: 280635
* [Modules] Add 'freestanding' to the 'requires-declaration' feature-list.Elad Cohen2016-09-041-0/+1
| | | | | | | | | This adds support for modules that require (non-)freestanding environment, such as the compiler builtin mm_malloc submodule. Differential Revision: https://reviews.llvm.org/D23871 llvm-svn: 280613
* Trailing dot that shouldn't have been committed.Joerg Sonnenberger2016-09-041-1/+1
| | | | llvm-svn: 280609
* PR 27200: Fix names of the atomic lock-free macros.Joerg Sonnenberger2016-09-041-6/+6
| | | | llvm-svn: 280607
* [AVX-512] Remove masked integer mullo builtins and replace with native IR.Craig Topper2016-09-036-97/+72
| | | | llvm-svn: 280597
* [AVX-512] Remove masked integer add/sub builtins and replace with native IR.Craig Topper2016-09-034-267/+192
| | | | llvm-svn: 280596
* [AVX-512] Implement masked floating point logical operations with native IR ↵Craig Topper2016-08-312-277/+204
| | | | | | and remove the builtins. llvm-svn: 280197
* [X86] Use v2i64 vectors to implement _mm_and/andn/or/xor_pd.Craig Topper2016-08-311-4/+4
| | | | | | These will be reused when removing some builtins from avx512vldqintrin.h and this will make the tests for that change show a better number of vector elements. llvm-svn: 280196
* [Modules] Add 'gnuinlineasm' to the 'requires-declaration' feature-list.Bruno Cardoso Lopes2016-08-301-0/+1
| | | | | | | | | | | | | This adds support for modules that require (no-)gnu-inline-asm environment, such as the compiler builtin cpuid submodule. This is the gnu-inline-asm variant of https://reviews.llvm.org/D23871 Differential Revision: https://reviews.llvm.org/D23905 rdar://problem/26931199 llvm-svn: 280159
* [OpenCL] Make is_valid_event, create_user_event overloadable.Alexey Bader2016-08-301-2/+2
| | | | | | | | | | | | | | Summary: Make is_valid_event and create_user_event overloadable like other built-ins. Patch by Evgeniy Tyurin. Reviewers: bader, yaxunl Subscribers: Anastasia, cfe-commits Differential Revision: https://reviews.llvm.org/D23914 llvm-svn: 280097
* [X86][AVX512F] minor fix of the parameter namesAsaf Badouh2016-08-211-8/+8
| | | | | | | | | | | | | add "__" prefix Bug 28842 https://llvm.org/bugs/show_bug.cgi?id=29040 Differential Revision: https://reviews.llvm.org/D23753 llvm-svn: 279392
* [CUDA] Improve handling of math functions.Justin Lebar2016-08-182-3/+285
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: A bunch of related changes here to our CUDA math headers. - The second arg to nexttoward is a double (well, technically, long double, but we don't have that), not a float. - Add a forward-declare of llround(float), which is defined in the CUDA headers. We need this for the same reason we need most of the other forward-declares: To prevent a constexpr function in our standard library from becoming host+device. - Add nexttowardf implementation. - Pull "foobarf" functions defined by the CUDA headers in the global namespace into namespace std. This lets you do e.g. std::sinf. - Add overloads for math functions accepting integer types. This lets you do e.g. std::sin(0) without having an ambiguity between the overload that takes a float and the one that takes a double. With these changes, we pass testcases derived from libc++ for cmath and math.h. We can check these testcases in to the test-suite once support for CUDA lands there. Reviewers: tra Subscribers: cfe-commits Differential Revision: https://reviews.llvm.org/D23627 llvm-svn: 279140
* [OpenCL] AMDGPU: Add extensions cl_amd_media_ops and cl_amd_media_ops2Yaxun Liu2016-08-161-0/+190
| | | | | | Differential Revision: https://reviews.llvm.org/D23322 llvm-svn: 278851
* Revert "[X86] Add xgetbv/x[X86] Add xgetbv xsetbv intrinsics to non-windows ↵Reid Kleckner2016-08-162-13/+10
| | | | | | | | platforms" This reverts commit r278783. It breaks usage of _xgetbv on Windows. llvm-svn: 278814
* [X86] Add xgetbv/x[X86] Add xgetbv xsetbv intrinsics to non-windows platformsMarina Yatsina2016-08-162-10/+13
| | | | | | | | commit on behalf of guyblank Differential Revision: https://reviews.llvm.org/D21959 llvm-svn: 278783
* [X86][AVX512] lower __mm512_andnot_ps/__mm512_andnot_pd to IRLama Saba2016-08-101-10/+2
| | | | | | | Differential revision: https://reviews.llvm.org/D23262 llvm-svn: 278209
* [CUDA] Add __device__ overloads for placement new and delete.Justin Lebar2016-08-101-0/+18
| | | | | | | | | | | | | | | Summary: Previously these sort of worked because they didn't end up resulting in calls at the ptx layer. But I'm adding stricter checks that break placement new without these changes. Reviewers: tra Subscribers: cfe-commits Differential Revision: https://reviews.llvm.org/D23239 llvm-svn: 278194
* [AVX512] integer comparisions enumeration.Asaf Badouh2016-08-071-0/+13
| | | | | | | | | | fix Bug 28842 https://llvm.org/bugs/show_bug.cgi?id=28842 Differential Revision: https://reviews.llvm.org/D22212 llvm-svn: 277955
* Headers: Add ARM support to intrin.h for MSVC compatibilitySaleem Abdulrasool2016-08-063-0/+50
| | | | | | | | | | | | | | | | | This fixes compiling with headers from the Windows SDK for ARM, where the YieldProcessor function (in winnt.h) refers to _ARM_BARRIER_ISHST. The actual MSVC armintr.h contains a lot more definitions, but this is enough to build code that uses the Windows SDK but doesn't use ARM intrinsics directly. An alternative would to just keep the addition to intrin.h (to include armintr.h), but not actually ship armintr.h, instead having clang's intrin.h include armintr.h from MSVC's include directory. (That one works fine with clang, at least for building code that uses the Windows SDK.) Patch by Martin Storsjö! llvm-svn: 277928
* [OpenCL] Remove extra native_ functions from opencl-c.hYaxun Liu2016-08-041-112/+0
| | | | | | | | | | There should be no native_ builtin functions with double type arguments. Patch by Aaron En Ye Shi. Differential Revision : https://reviews.llvm.org/D23071 llvm-svn: 277754
* Add more gcc compatibility names to clang's cpuid.hDimitry Andric2016-07-311-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: Some cpuid bit defines are named slightly different from how gcc's cpuid.h calls them. Define a few more compatibility names to appease software built for gcc: * `bit_PCLMUL` alias of `bit_PCLMULQDQ` * `bit_SSE4_1` alias of `bit_SSE41` * `bit_SSE4_2` alias of `bit_SSE42` * `bit_AES` alias of `bit_AESNI` * `bit_CMPXCHG8B` alias of `bit_CX8` While here, add the misssing 29th bit, `bit_F16C` (which is how gcc calls this bit). Reviewers: joerg, rsmith Subscribers: bruno, cfe-commits Differential Revision: https://reviews.llvm.org/D22010 llvm-svn: 277307
* Remove unused variable.Eric Christopher2016-07-291-1/+0
| | | | | | Fixes PR28761. llvm-svn: 277221
* [OpenCL] Added CLK_ABGR definition for get_image_channel_order return valueYaxun Liu2016-07-291-0/+1
| | | | | | | | | | Added CLK_ABGR definition for get_image_channel_order return value inside opencl-c.h file. Patch by Aaron En Ye Shi. Differential Revision: https://reviews.llvm.org/D22767 llvm-svn: 277179
* [X86] Block pbroadcastq instructions on 32-bit targets instead of pbroadcastb.Craig Topper2016-07-242-4/+0
| | | | | | Thanks to Simon Pilgrim for catching the mistake. llvm-svn: 276564
* Add doxygen comments to emmintrin.h's intrinsics.Ekaterina Romanova2016-07-221-0/+769
| | | | | | | | | | | | Only around 50% of the intrinsics in this file are documented now. The patches for the rest of the intrisics in this file will be send out later. The doxygen comments are automatically generated based on Sony's intrinsics docu ment. I got an OK from Eric Christopher to commit doxygen comments without prior code review upstream. This patch was internally reviewed by Paul Robinson. llvm-svn: 276499
* [X86] Add missing __x86_64__ qualifiers on a bunch of intrinsics that assume ↵Craig Topper2016-07-216-7/+47
| | | | | | | | 64-bit GPRs are available. Usages of these intrinsics in a 32-bit build results in assertions in the backend. llvm-svn: 276249
* [X86][SSE] Reimplement SSE fp2si conversion intrinsics instead of using ↵Simon Pilgrim2016-07-203-9/+8
| | | | | | | | | | | | | | | | generic IR D20859 and D20860 attempted to replace the SSE (V)CVTTPS2DQ and VCVTTPD2DQ truncating conversions with generic IR instead. It turns out that the behaviour of these intrinsics is different enough from generic IR that this will cause problems, INF/NAN/out of range values are guaranteed to result in a 0x80000000 value - which plays havoc with constant folding which converts them to either zero or UNDEF. This is also an issue with the scalar implementations (which were already generic IR and what I was trying to match). This patch changes both scalar and packed versions back to using x86-specific builtins. It also deals with the other scalar conversion cases that are runtime rounding mode dependent and can have similar issues with constant folding. Differential Revision: https://reviews.llvm.org/D22105 llvm-svn: 276102
* [X86][AVX512F] minor fix of the parameter namesAsaf Badouh2016-07-141-18/+18
| | | | | | add "__" prefix llvm-svn: 275384
* [Clang][AVX512] Making cosmetic changesMichael Zuckerman2016-07-121-12/+6
| | | | llvm-svn: 275169
* [AVX512] Replace masked AND/OR/XOR intrinsics with native code and remove ↵Craig Topper2016-07-112-253/+139
| | | | | | the builtins. llvm-svn: 275049
* [X86] Use __butilin_shufflevector for 512-bit shufps intrinsics.Craig Topper2016-07-101-16/+28
| | | | llvm-svn: 275012
* [X86] Use __builtin_ia32_vec_ext_v4hi and __builtin_ia32_vec_set_v4hi to ↵Craig Topper2016-07-091-13/+4
| | | | | | | | implement pextrw/pinsertw MMX intrinsics instead of trying to use native IR. Without this we end up generating code that doesn't use mmx registers and probably doesn't work well with other mmx intrinsics. llvm-svn: 274968
* NVPTX: Use the nvvm builtins to read SRegs rather than the legacy ptx onesJustin Bogner2016-07-071-13/+13
| | | | | | The ptx spellings were removed from LLVM in r274769. llvm-svn: 274770
* NVPTX: Rename __builtin_ptx_shfl -> __nvvm_shflJustin Bogner2016-07-061-8/+4
| | | | | | | To match "NVPTX: Make the llvm.nvvm.shfl intrinsics and builtin names consistent" in LLVM. llvm-svn: 274663
* [Clang][Feature] Adding CLFLUSHOPT feature and intrinsic to clangMichael Zuckerman2016-07-053-0/+46
| | | | | | Differential Revision: http://reviews.llvm.org/D21792 llvm-svn: 274559
* [X86][AVX512] Converted the VBROADCAST intrinsics to generic IRSimon Pilgrim2016-07-054-126/+128
| | | | llvm-svn: 274544
* [X86][AVX512F] add float/double abs intrinsicsAsaf Badouh2016-07-051-18/+36
| | | | | | | | | add abs intrinsics that use native LLVM-IR. change _mm512_mask[z]_and_epi{32|64} to use select intrinsic Differential Revision: http://reviews.llvm.org/D21973 llvm-svn: 274542
* [AVX512] minor fix in sqrt{ss|sd} intrinsics argumentsAsaf Badouh2016-07-051-18/+18
| | | | | | Differential Revision: http://reviews.llvm.org/D21988 llvm-svn: 274541
* [OpenCL] An implementation of device side enqueue (DSE) from OpenCL v2.0 ↵Anastasia Stulova2016-07-051-6/+0
| | | | | | | | | | | | | | | | | s6.13.17. - Added new Builtins: enqueue_kernel, get_kernel_work_group_size and get_kernel_preferred_work_group_size_multiple. These Builtins use custom check to diagnose parameters of the passed Blocks i. e. variable number of 'local void*' type params, and check different overloads specified in Table 6.31 of OpenCL v2.0. - IR is generated as an internal library call for each OpenCL Builtin, reusing ObjC Block implementation. Review: http://reviews.llvm.org/D20249 llvm-svn: 274540
* ntrinsics _mm256_permutexvar_epi64 doesn't accept three parameters as ↵Michael Zuckerman2016-07-051-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | specify bellow. I deleted the extra mask parameter. __m256i _mm256_permutexvar_epi64 (__m256i idx, __m256i a) #include "immintrin.h" Instruction: vpermq CPUID Flags: AVX512VL + AVX512F Description Shuffle 64-bit integers in a across lanes using the corresponding index in idx, and store the results in dst. Operation FOR j := 0 to 3 i := j*64 id := idx[i+1:i]*64 dst[i+63:i] := a[id+63:id] ENDFOR dst[MAX:256] := 0 dst[MAX:256] := 0 (From: Intel intrinsics guide) llvm-svn: 274539
* [Clang][BuiltIn][AVX512] adding ↵Michael Zuckerman2016-07-052-0/+54
| | | | | | | | _mm{|256|512}_mask_cvt{s|us|}epi16_storeu_epi8 intrinsics Differential Revision: http://reviews.llvm.org/D21729 llvm-svn: 274532
* [X86] Use undefined instead of setzero in shufflevector based intrinsics ↵Craig Topper2016-07-047-187/+198
| | | | | | when the second source is unused. Rewrite immediate extractions in shuffle intrinsics to be in ((c >> x) & y) form instead of ((c & z) >> x). This way only x varies between each use instead of having to vary x and z. llvm-svn: 274525
* [X86][AVX512] Converted the VSHUFPD intrinsics to generic IRSimon Pilgrim2016-07-042-54/+53
| | | | llvm-svn: 274523
* [X86][AVX512] Converted the VPERMPD/VPERMQ intrinsics to generic IRSimon Pilgrim2016-07-042-53/+69
| | | | llvm-svn: 274502
* [X86][AVX512] Converted the VPERMILPD/VPERMILPS intrinsics to generic IRSimon Pilgrim2016-07-041-18/+40
| | | | llvm-svn: 274492
* [X86][AVX512] Converted the MOVDDUP/MOVSLDUP/MOVSHDUP masked intrinsics to ↵Simon Pilgrim2016-07-022-77/+60
| | | | | | | | generic IR llvm companion patch imminent llvm-svn: 274442
* [X86] Replace 128-bit and 256 masked vpermilps/vpermilpd builtins with ↵Craig Topper2016-07-021-23/+24
| | | | | | native IR. llvm-svn: 274425
* [Clang][Intrinsics][AVX512][BuiltIn] adding intrinsics for vrangesd ↵Michael Zuckerman2016-06-301-0/+12
| | | | | | | | instruction set Differential Revision: http://reviews.llvm.org/D21734 llvm-svn: 274218
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