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* [X86] Move the include of clzerointrin.h from immintrin.h back to x86intrin.h.Craig Topper2018-05-231-0/+5
| | | | | | This is an AMD intrinsic not an Intel intrinsic so it shouldn't be in immintrin.h llvm-svn: 333124
* [X86] Move all Intel defined intrinsic includes into immintrin.hCraig Topper2018-05-231-57/+0
| | | | | | | | | | This matches the Intel documentation which shows them available by importing immintrin.h. x86intrin.h also includes immintrin.h so anyone including x86intrin.h will still get them. This is different than gcc, but I don't think we were a perfect match there already. I'm unclear what gcc's policy is about how they choose which to add things to. Differential Revision: https://reviews.llvm.org/D47182 llvm-svn: 333110
* [X86] ptwrite intrinsicGabor Buella2018-05-101-0/+4
| | | | | | | | | | Reviewers: craig.topper, RKSimon Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D46540 llvm-svn: 331962
* [x86] Introduce the encl[u|s|v] intrinsicsGabor Buella2018-05-081-0/+4
| | | | | | | | | | Reviewers: craig.topper, zvi Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D46435 llvm-svn: 331743
* [x86] Introduce the pconfig intrinsicGabor Buella2018-05-081-0/+4
| | | | | | | | | | Reviewers: craig.topper, zvi Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D46431 llvm-svn: 331740
* [X86] directstore and movdir64b intrinsicsGabor Buella2018-05-011-0/+5
| | | | | | | | | | Reviewers: spatel, craig.topper, RKSimon Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45984 llvm-svn: 331249
* [X86] WaitPKG intrinsicsGabor Buella2018-04-201-0/+4
| | | | | | | | | | Reviewers: craig.topper, zvi Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45254 llvm-svn: 330463
* [X86] Introduce cldemote intrinsicGabor Buella2018-04-131-0/+4
| | | | | | | | | | Reviewers: craig.topper, zvi Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45257 llvm-svn: 329993
* [x86] wbnoinvd intrinsicGabor Buella2018-04-111-0/+4
| | | | | | | | | | | | | | The WBNOINVD instruction writes back all modified cache lines in the processor’s internal cache to main memory but does not invalidate (flush) the internal caches. Reviewers: craig.topper, zvi, ashlykov Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D43817 llvm-svn: 329848
* [X86][LWP] Removing LWP todo comment. NFCI.Simon Pilgrim2017-05-091-2/+0
| | | | | | LWP / lwpintrin.h is now supported llvm-svn: 302557
* [X86][LWP] Add clang support for LWP instructions.Simon Pilgrim2017-05-081-0/+4
| | | | | | | | This patch adds support for the the LightWeight Profiling (LWP) instructions which are available on all AMD Bulldozer class CPUs (bdver1 to bdver4). Differential Revision: https://reviews.llvm.org/D32770 llvm-svn: 302418
* [X86] Clzero flag addition and inclusion under znver1Craig Topper2017-02-091-0/+4
| | | | | | | | | | | | | 1. Adds the command line flag for clzero. 2. Includes the clzero flag under znver1. 3. Defines the macro for clzero. 4. Adds a new file which has the intrinsic definition for clzero instruction. Patch by Ganesh Gopalasubramanian with some additional tests from me. Differential revision: https://reviews.llvm.org/D29386 llvm-svn: 294559
* Add new intrinsic support for MONITORX and MWAITX instructionsAshutosh Nema2016-05-181-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: MONITORX/MWAITX instructions provide similar capability to the MONITOR/MWAIT pair while adding a timer function, such that another termination of the MWAITX instruction occurs when the timer expires. The presence of the MONITORX and MWAITX instructions is indicated by CPUID 8000_0001, ECX, bit 29. The MONITORX and MWAITX instructions are intercepted by the same bits that intercept MONITOR and MWAIT. MONITORX instruction establishes a range to be monitored. MWAITX instruction causes the processor to stop instruction execution and enter an implementation-dependent optimized state until occurrence of a class of events. Opcode of MONITORX instruction is "0F 01 FA". Opcode of MWAITX instruction is "0F 01 FB". These opcode information is used in adding tests for the disassembler. These instructions are enabled for AMD's bdver4 architecture. Patch by Ganesh Gopalasubramanian! Reviewers: echristo, craig.topper Subscribers: RKSimon, joker.eph, llvm-commits, cfe-commits Differential Revision: http://reviews.llvm.org/D19796 llvm-svn: 269907
* [ms] Reintroduce feature guards in intrinsic headers in Microsoft modeNico Weber2016-05-161-0/+24
| | | | | | | | | | | | | | | | | | | | | Visual Studio's C++ standard library headers include intrin.h, so the intrinsic headers get included a lot more often in Microsoft mode than elsewhere. The AVX512 intrinsics are a lot of code (0.7 MB, causing 30% compile time overhead for small programs including e.g. <string> and 6% compile time overhead for larger projects like e.g. v8). Since multiversioning can't be relied on in Microsoft mode (cl.exe doesn't support it), having faster compiles seems like the much better tradeoff until we have a better intrinsic story going forward (which we'll need for e.g. PR19898). Actually using intrinsics on Windows already requires the right /arch: settings, so this patch should have no big behavior change. See also thread "The intrinsics headers (especially avx512) are too big. What to do about it?" on cfe-dev. http://reviews.llvm.org/D20291 llvm-svn: 269675
* Update the intel intrinsic headers to use the target attribute support.Eric Christopher2015-06-171-24/+0
| | | | | | | | | | | | | | | | | | | This involved removing the conditional inclusion and replacing them with target attributes matching the original conditional inclusion and checks. The testcase update removes the macro checks for each file and replaces them with usage of the __target__ attribute, e.g.: int __attribute__((__target__(("sse3")))) foo(int a) { _mm_mwait(0, 0); return 4; } This usage does require the enclosing function have the requisite __target__ attribute for inlining and code generation - also for any macro intrinsic uses in the enclosing function. There's no change for existing uses of the intrinsic headers. llvm-svn: 239883
* Replace a few // comments with /**/ comments in headers, for consistency.Nico Weber2014-07-081-1/+1
| | | | llvm-svn: 212556
* Implement __readeflags and __writeeflags intrinsicsAlexey Bataev2014-03-041-0/+2
| | | | llvm-svn: 202778
* Adding intrinsics to the clang front end for the x86 TBM instruction set.Yunzhong Gao2013-09-301-0/+4
| | | | | | Differential Revision: http://llvm-reviews.chandlerc.com/D1751 llvm-svn: 191681
* Move sha intrinsics to immintrin.hBen Langmuir2013-09-191-4/+0
| | | | | | This is consistent with ICC and Intel's SHA-enabled GCC version. llvm-svn: 191002
* Add C intrinsics for Intel SHA ExtensionsBen Langmuir2013-09-191-0/+4
| | | | | | | | | Intrinsics added shaintrin.h, which is included from x86intrin.h if __SHA__ is enabled. SHA implies SSE2, which is needed for the __m128i type. Also add the -msha/-mno-sha option. llvm-svn: 190999
* Add RDSEED intrinsic support defined in AVX2 extensionMichael Liao2013-03-291-0/+4
| | | | llvm-svn: 178331
* Add PRFCHW intrinsic supportMichael Liao2013-03-261-0/+4
| | | | | | | | | - Add head 'prfchwintrin.h' to define '_m_prefetchw' which is mapped to LLVM/clang prefetch builtin - Add option '-mprfchw' to enable PRFCHW feature and pre-define '__PRFCHW__' macro llvm-svn: 178041
* X86: add F16C support in ClangManman Ren2012-10-111-0/+4
| | | | | | | | | Support the following intrinsics: _mm_cvtph_ps, _mm256_cvtph_ps, _mm_cvtps_ph, _mm256_cvtps_ph rdar://12407875 llvm-svn: 165685
* Begin adding XOP intrinsicsCraig Topper2012-06-101-1/+5
| | | | llvm-svn: 158286
* Update FIXME. ABM is already covered by LZCNT and POPCNT.Craig Topper2012-05-301-1/+1
| | | | llvm-svn: 157676
* Add an ammintrin.h header for SSE4a intrinsics.Benjamin Kramer2012-05-291-1/+5
| | | | | | | This is a clean-room implementation based on public documentation and I tried to validate it as much as possible against gcc. llvm-svn: 157638
* Add 3dNOW intrinsic header to x86intrin.h, conditioned on __3dNOW__ toChandler Carruth2012-02-201-1/+5
| | | | | | | | | | | | | | | | match the behavior of GCC. Also add a test for these intrinsics, which apparently have *zero* tests. =[ Not surprisingly, Clang crashed when compiling these. Fix the bug in CodeGen where we failed to bitcast the argument type to x86mmx prior to calling the LLVM intrinsic. This fixes an assert on the new 3dnow-builtins.c test. This is one issue impacting the efforts to get Clang to emulate the Microsoft intrinsics headers -- 3dnow intrinsics are implictitly made available there. llvm-svn: 150948
* Add FMA4 intrinsics.Craig Topper2011-12-301-0/+4
| | | | llvm-svn: 147372
* Remove an accidental change from r147370. Would only break if the new fma4 ↵Craig Topper2011-12-301-4/+0
| | | | | | flag was used. llvm-svn: 147371
* Add FMA4 feature flag. Intrinsics coming soon. Also make sse4a feature flag ↵Craig Topper2011-12-301-1/+5
| | | | | | imply sse3. Matches gcc behavior. llvm-svn: 147370
* Add popcnt feature flag to match gcc. This flag is implied when sse42 is ↵Craig Topper2011-12-291-1/+5
| | | | | | enabled, but can be disabled separately. Move popcnt intrinsics to popcntintrin.h to match gcc. llvm-svn: 147340
* Add BMI2 intrinsics.Craig Topper2011-12-261-0/+4
| | | | llvm-svn: 147275
* Add intrinsics for lzcnt and tzcnt instructions.Craig Topper2011-12-251-0/+8
| | | | llvm-svn: 147263
* Add x86intrin.h which is generic x86 intrinsics for more than just Intel. ThusNick Lewycky2010-08-221-0/+31
far, this just #include's immintrin.h for compatibility. llvm-svn: 111785
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