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* [X86] Add XSAVE intrinsic familyAmjad Aboud2015-10-131-0/+8
| | | | | | | | | | | | Add intrinsics for the XSAVE instructions (XSAVE/XSAVE64/XRSTOR/XRSTOR64) XSAVEOPT instructions (XSAVEOPT/XSAVEOPT64) XSAVEC instructions (XSAVEC/XSAVEC64) XSAVES instructions (XSAVES/XSAVES64/XRSTORS/XRSTORS64) Differential Revision: http://reviews.llvm.org/D13014 llvm-svn: 250158
* Revert r245923 since it breaks mingw.Michael Kuperstein2015-08-251-54/+0
| | | | llvm-svn: 245929
* [X86] Expose the various _rot intrinsics on non-MS platformsMichael Kuperstein2015-08-251-0/+54
| | | | | | | | | | | | | | _rotl, _rotwl and _lrotl (and their right-shift counterparts) are official x86 intrinsics, and should be supported regardless of environment. This is in contrast to _rotl8, _rotl16, and _rotl64 which are MS-specific. Note that the MS documentation for _lrotl is different from the Intel documentation. Intel explicitly documents it as a 64-bit rotate, while for MS, since sizeof(unsigned long) for MSVC is always 4, a 32-bit rotate is implied. Differential Revision: http://reviews.llvm.org/D12271 llvm-svn: 245923
* [X86] Add FXSR intrinsicsMichael Kuperstein2015-06-301-0/+2
| | | | | | | | | Add intrinsics for the FXSR instructions (FXSAVE/FXSAVE64/FXRSTOR/FXRSTOR64) These were previously declared in Intrin.h for MSVC compatibility, but now that we have them implemented, these declarations can be removed. llvm-svn: 241053
* [x86][AVX512CD] Add conflict and lzcnt intrinsics in their 512bit versionsAsaf Badouh2015-06-291-0/+2
| | | | | | | | | include tests review http://reviews.llvm.org/D10795 llvm-svn: 240941
* Move xtest to its own file to match the gcc header organization.Eric Christopher2015-06-171-9/+1
| | | | llvm-svn: 239926
* Update comments on HLE, RTM, and ADX support for intrinsics.Eric Christopher2015-06-171-3/+6
| | | | llvm-svn: 239925
* Update the intel intrinsic headers to use the target attribute support.Eric Christopher2015-06-171-62/+12
| | | | | | | | | | | | | | | | | | | This involved removing the conditional inclusion and replacing them with target attributes matching the original conditional inclusion and checks. The testcase update removes the macro checks for each file and replaces them with usage of the __target__ attribute, e.g.: int __attribute__((__target__(("sse3")))) foo(int a) { _mm_mwait(0, 0); return 4; } This usage does require the enclosing function have the requisite __target__ attribute for inlining and code generation - also for any macro intrinsic uses in the enclosing function. There's no change for existing uses of the intrinsic headers. llvm-svn: 239883
* AVX-512: Added AVX-512 intrinsics and testsElena Demikhovsky2015-04-301-0/+8
| | | | | | by Asaf Badouh (asaf.badouh@intel.com) llvm-svn: 236218
* Add FSGSBASE intrinsics to x86 intrinsic headers.Craig Topper2014-11-031-0/+52
| | | | llvm-svn: 221130
* [AVX512] Added VPCMPEQ intrinisics to headers.Robert Khasanov2014-10-081-0/+12
| | | | | | | | Added tests. Patch by Maxim Blumenthal <maxim.blumenthal@intel.com> llvm-svn: 219319
* [x86] Added _addcarryx_u32, _addcarryx_u64 intrinsicsRobert Khasanov2014-09-191-0/+4
| | | | llvm-svn: 218117
* AVX-512: Added intrinsics to clang.Elena Demikhovsky2014-07-221-0/+8
| | | | | | | The set is small, that what I have right now. Everybody is welcome to add more. llvm-svn: 213641
* The wmmintrin.h header includes two different sub-headers: one for AES supportRoman Divacky2014-03-041-1/+1
| | | | | | | | | | and one for PCLMUL support. The current immintrin.h header only includes wmmintrin.h if AES support is enabled. It should include it if either AES or PCLMUL is enabled (GCC's version of immintrin.h does this). Patch by John Baldwin! llvm-svn: 202871
* Move sha intrinsics to immintrin.hBen Langmuir2013-09-191-0/+4
| | | | | | This is consistent with ICC and Intel's SHA-enabled GCC version. llvm-svn: 191002
* Add XTEST intrinsic defined in TSX extensionMichael Liao2013-03-291-0/+9
| | | | llvm-svn: 178330
* Add clang support of RTM from TSXMichael Liao2012-11-101-0/+4
| | | | | | | | | | | | - New options '-mrtm'/'-mno-rtm' are added to enable/disable RTM feature - Builtin macro '__RTM__' is defined if RTM feature is enabled - RTM intrinsic header is added and introduces 3 new intrinsics, namely '_xbegin', '_xend', and '_xabort'. - 3 new builtins are added to keep compatible with gcc, namely '__builtin_ia32_xbegin', '__builtin_ia32_xend', and '__builtin_ia32_xabort'. - Test cases for pre-defined macro and new intrinsic codegen are added. llvm-svn: 167665
* Add _rdrand{16,32,64}_step intrinsics to immintrin.hBenjamin Kramer2012-07-121-0/+22
| | | | llvm-svn: 160118
* Add fma3 intrinsic header file.Craig Topper2012-06-041-0/+4
| | | | llvm-svn: 157913
* Add BMI2 intrinsics.Craig Topper2011-12-261-0/+4
| | | | llvm-svn: 147275
* Add intrinsics for lzcnt and tzcnt instructions.Craig Topper2011-12-251-0/+8
| | | | llvm-svn: 147263
* Add BMI, BMI2, and LZCNT feature flags to enable adding intrinsics.Craig Topper2011-12-251-1/+1
| | | | llvm-svn: 147262
* Begin adding AVX2 intrinsics. Necessitated increasing the number of bits ↵Craig Topper2011-12-191-0/+4
| | | | | | used to store builtinID when serializing identifier table. llvm-svn: 146855
* Add immintrin meta header.Benjamin Kramer2010-08-201-0/+59
- This is the official way to get AVX intrinsics, we might want to disallow direct inclusion of avxintrin.h, just like GCC does. llvm-svn: 111660
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