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* [AArch64] Support reserving arbitrary general purpose registersPetr Hosek2019-02-131-0/+42
| | | | | | | | | | | | This is a follow up to D48580 and D48581 which allows reserving arbitrary general purpose registers with the exception of registers with special purpose (X8, X16-X18, X29, X30) and registers used by LLVM (X0, X19). This change also generalizes some of the existing logic to rely entirely on values generated from tablegen. Differential Revision: https://reviews.llvm.org/D56305 llvm-svn: 353957
* Use llvm::is_contained. NFCFangrui Song2019-02-102-4/+3
| | | | llvm-svn: 353635
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-1916-64/+48
| | | | | | | | | | | | | | | | | to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
* Replace getOS() == llvm::Triple::*BSD with isOS*BSD() [NFCI]Michal Gorny2018-12-201-2/+2
| | | | | | | | | | | | Replace multiple comparisons of getOS() value with FreeBSD, NetBSD, OpenBSD and DragonFly with matching isOS*BSD() methods. This should improve the consistency of coding style without changing the behavior. Direct getOS() comparisons were left whenever used in switch or switch- like context. Differential Revision: https://reviews.llvm.org/D55916 llvm-svn: 349752
* [darwin][arm64] use the "cyclone" CPU for Darwin even when `-arch`Alex Lorenz2018-12-172-12/+23
| | | | | | | | | | | | | | | | is not specified The -target option allows the user to specify the build target using LLVM triple. The triple includes the arch, and so the -arch option is redundant. This should work just as well without the -arch. However, the driver has a bug in which it doesn't target the "Cyclone" CPU for darwin if -target is used without -arch. This commit fixes this issue. rdar://46743182 Differential Revision: https://reviews.llvm.org/D55731 llvm-svn: 349382
* [Driver] Don't override '-march' when using '-arch x86_64h'Francis Visoiu Mistrih2018-12-171-5/+1
| | | | | | | | | | | | On Darwin, using '-arch x86_64h' would always override the option passed through '-march'. This patch allows users to use '-march' with x86_64h, while keeping the default to 'core-avx2' Differential Revision: https://reviews.llvm.org/D55775 llvm-svn: 349381
* [PowerPC] Set the default PLT mode on OpenBSD/powerpc to Secure PLT.Brad Smith2018-11-192-4/+8
| | | | | | OpenBSD/powerpc only supports Secure PLT. llvm-svn: 347179
* [driver][mips] Support MIPS R6 target triplesSimon Atanasyan2018-10-161-0/+5
| | | | | | | | | | | | | | | | This change adds support for the following MIPS target triples: mipsisa32r6-linux-gnu mipsisa32r6el-linux-gnu mipsisa64r6-linux-gnuabi64 mipsisa64r6el-linux-gnuabi64 mipsisa64r6-linux-gnuabin32 mipsisa64r6el-linux-gnuabin32 Patch by Yun Qiang Su. Differential revision: https://reviews.llvm.org/D50850 llvm-svn: 344608
* [ARM][AArch64] Pass through endian flags to assembler and linker.Peter Smith2018-10-162-2/+2
| | | | | | | | | | | | | | | | | The big-endian arm32 Linux builds are currently failing when the -mbig-endian flag is used but the binutils default on the system is little endian. This also holds when -mlittle-endian is used and the binutils default is big endian. The patch always passes through -EL or -BE to the assembler and linker, taking into account the target and the -mbig-endian and -mlittle-endian flag. Fixes pr38770 Differential Revision: https://reviews.llvm.org/D52784 llvm-svn: 344597
* [mips] Fix handling of GNUABIN32 environment in a target tripleSimon Atanasyan2018-10-151-0/+3
| | | | | | | | | | | | The `GNUABIN32` environment in a target triple implies using the N32 ABI. This patch adds support for this environment and switches on N32 ABI if necessary. Patch by Patch by YunQiang Su. Differential revision: https://reviews.llvm.org/D51464 llvm-svn: 344570
* [Driver] Add defaults for Android ARM FPUs.Dan Albert2018-10-121-0/+7
| | | | | | | | | | | | | | | | | Summary: Android mandates that devices have at least vfpv3-d16 until Marshmallow and NEON after that. Still honor the user's decision, but raise the defaults for Android targets. Reviewers: srhines, pirama, javed.absar, kristof.beyls, peter.smith Reviewed By: peter.smith Subscribers: peter.smith, rengolin, kristof.beyls, chrib, cfe-commits Differential Revision: https://reviews.llvm.org/D53121 llvm-svn: 344367
* [AArch64][ARM] Context sensitive meaning of cryptoSjoerd Meijer2018-10-042-0/+101
| | | | | | | | | | | | | | For AArch64, crypto means: - sm4 + sha3 + sha2 + aes for Armv8.4-A and up, and - sha2 + aes for Armv8.3-A and earlier. For AArch32: Crypto means sha2 + aes, because the Armv8.2-A crypto instructions were added to AArch64 only. Differential Revision: https://reviews.llvm.org/D50179 llvm-svn: 343758
* [AArch64] Support adding X[8-15,18] registers as CSRs.Tri Vo2018-09-251-0/+27
| | | | | | | | | | | | | | | | | | Summary: Making X[8-15,18] registers call-saved is used to support CONFIG_ARM64_LSE_ATOMICS in Linux kernel. Signed-off-by: Tri Vo <trong@android.com> Reviewers: srhines, nickdesaulniers, javed.absar Reviewed By: nickdesaulniers Subscribers: kristof.beyls, jfb, cfe-commits Differential Revision: https://reviews.llvm.org/D52399 llvm-svn: 342990
* [ARM][AArch64] Add feature +fp16fmlSjoerd Meijer2018-09-242-1/+54
| | | | | | | | | | | | | | | | | | | | | Armv8.4-A adds a few FP16 instructions that can optionally be implemented in CPUs of Armv8.2-A and above. This patch adds a feature to clang to permit selection of these instructions. This interacts with the +fp16 option as follows: Prior to Armv8.4-A: *) +fp16fml implies +fp16 *) +nofp16 implies +nofp16fml From Armv8.4-A: *) The above conditions apply, additionally: +fp16 implies +fp16fml Patch by Bernard Ogden. Differential Revision: https://reviews.llvm.org/D50229 llvm-svn: 342862
* [AArch64] Support reserving x1-7 registers.Tri Vo2018-09-121-0/+21
| | | | | | | | | | | | | | Summary: Reserving registers x1-7 is used to support CONFIG_ARM64_LSE_ATOMICS in Linux kernel. This change adds support for reserving registers x1 through x7. Reviewers: javed.absar, efriedma, nickdesaulniers, srhines, phosek Reviewed By: nickdesaulniers Subscribers: manojgupta, jfb, cfe-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D48581 llvm-svn: 342100
* [x86/SLH] Add a real Clang flag and LLVM IR attribute for SpeculativeChandler Carruth2018-09-041-5/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Load Hardening. Wires up the existing pass to work with a proper IR attribute rather than just a hidden/internal flag. The internal flag continues to work for now, but I'll likely remove it soon. Most of the churn here is adding the IR attribute. I talked about this Kristof Beyls and he seemed at least initially OK with this direction. The idea of using a full attribute here is that we *do* expect at least some forms of this for other architectures. There isn't anything *inherently* x86-specific about this technique, just that we only have an implementation for x86 at the moment. While we could potentially expose this as a Clang-level attribute as well, that seems like a good question to defer for the moment as it isn't 100% clear whether that or some other programmer interface (or both?) would be best. We'll defer the programmer interface side of this for now, but at least get to the point where the feature can be enabled without relying on implementation details. This also allows us to do something that was really hard before: we can enable *just* the indirect call retpolines when using SLH. For x86, we don't have any other way to mitigate indirect calls. Other architectures may take a different approach of course, and none of this is surfaced to user-level flags. Differential Revision: https://reviews.llvm.org/D51157 llvm-svn: 341363
* [x86/retpoline] Split the LLVM concept of retpolines into separateChandler Carruth2018-08-231-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | subtarget features for indirect calls and indirect branches. This is in preparation for enabling *only* the call retpolines when using speculative load hardening. I've continued to use subtarget features for now as they continue to seem the best fit given the lack of other retpoline like constructs so far. The LLVM side is pretty simple. I'd like to eventually get rid of the old feature, but not sure what backwards compatibility issues that will cause. This does remove the "implies" from requesting an external thunk. This always seemed somewhat questionable and is now clearly not desirable -- you specify a thunk the same way no matter which set of things are getting retpolines. I really want to keep this nicely isolated from end users and just an LLVM implementation detail, so I've moved the `-mretpoline` flag in Clang to no longer rely on a specific subtarget feature by that name and instead to be directly handled. In some ways this is simpler, but in order to preserve existing behavior I've had to add some fallback code so that users who relied on merely passing -mretpoline-external-thunk continue to get the same behavior. We should eventually remove this I suspect (we have never tested that it works!) but I've not done that in this patch. Differential Revision: https://reviews.llvm.org/D51150 llvm-svn: 340515
* Remove trailing spaceFangrui Song2018-07-301-1/+1
| | | | | | sed -Ei 's/[[:space:]]+$//' include/**/*.{def,h,td} lib/**/*.{cpp,h} llvm-svn: 338291
* OpenBSD/arm has switched to float ABI SoftFP.Brad Smith2018-07-221-1/+1
| | | | llvm-svn: 337660
* Change \t to spacesFangrui Song2018-07-202-2/+2
| | | | llvm-svn: 337530
* [mips] Add '-mvirt', '-mno-virt', '-mginv', '-mno-ginv' optionsVladimir Stefanovic2018-07-111-0/+4
| | | | | | | | | '-mvirt'/'-mno-virt' enables/disables Virtualization ASE. '-mginv'/'-mno-ginv' enables/disables GINV (Global Invalidate) ASE. Differential revision: https://reviews.llvm.org/D48982 llvm-svn: 336798
* [Driver,AArch64] Add support for -mcpu=native.Florian Hahn2018-07-061-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | This patches adds support for passing -mcpu=native for AArch64. It will get turned into the host CPU name, before we get the target features. CPU = native is handled in a similar fashion in getAArch64MicroArchFetauresFromMtune and getAArch64TargetCPU already. Having a good test case for this is hard, as it depends on the host CPU of the machine running the test. But we can check that native has been replaced with something else. When cross-compiling, we will get a CPU name from the host architecture and get ` the clang compiler does not support '-mcpu=native'` as error message, which seems reasonable to me. Reviewers: rengolin, peter.smith, dlj, javed.absar, t.p.northover Reviewed By: peter.smith Tags: #clang Differential Revision: https://reviews.llvm.org/D48931 llvm-svn: 336429
* [mips] Add '-mcrc', '-mno-crc' options to enable/disable CRC ASEVladimir Stefanovic2018-07-051-0/+2
| | | | | | | | | '-mcrc' is shared with ARM. '-mno-crc' is Mips-only (ARM uses '-mnocrc'). Differential revision: https://reviews.llvm.org/D48169 llvm-svn: 336347
* [mips] Use more conservative default CPUs for MIPS on FreeBSD.John Baldwin2018-06-261-0/+7
| | | | | | | | | | | | FreeBSD defaults to mips3 for all MIPS ABIs with GCC as that is the minimum MIPS architecture FreeBSD supports. Use mips3 for MIPS64 and mips2 for MIPS32 to match. Reviewed By: atanasyan Differential Revision: https://reviews.llvm.org/D48499 llvm-svn: 335653
* Use Triple::isMIPS() instead of enumerating all Triples. NFCAlexander Richardson2018-06-252-12/+1
| | | | | | | | Reviewed By: atanasyan Differential Revision: https://reviews.llvm.org/D48549 llvm-svn: 335495
* [AArch64] Support reserving x20 registerPetr Hosek2018-06-121-0/+3
| | | | | | | | | | | | Register x20 is a callee-saved register which may be used for other purposes in certain contexts, for example to hold special variables within the kernel. This change adds support for reserving this register both to frontend and backend to make this register usable for these purposes. Differential Revision: https://reviews.llvm.org/D46552 llvm-svn: 334531
* [RISCV] Add -mrelax/-mno-relax flags to enable/disable RISCV linker relaxationShiva Chen2018-05-291-0/+5
| | | | | | Differential Revision: https://reviews.llvm.org/D44888 llvm-svn: 333385
* [Sparc] Use the leon arch for Leon3's when using an external assemblerDaniel Cederman2018-05-241-4/+19
| | | | | | | | | | | | | | Summary: This allows the use of the casa instruction available in most Leon3's. Reviewers: jyknight Reviewed By: jyknight Subscribers: joerg, fedor.sergeev, jrtc27, cfe-commits Differential Revision: https://reviews.llvm.org/D47138 llvm-svn: 333157
* [mips] Improve handling of -fno-[pic/PIC] optionAleksandar Beserminji2018-05-071-3/+12
| | | | | | | | | | | | | | | In order to disable PIC and to match GCC behaviour, -mno-abicalls option is neccessary. When -fno-[pic/PIC] is used witout -mno-abicalls, warning is reported. An error is reported when -fno-pic or -fno-PIC is used in combination with -mabicalls. In this commit, test case is added. Depends on D44381. Differential Revision: https://reviews.llvm.org/D44684 llvm-svn: 331640
* Revert "[mips] Improve handling of -fno-[pic/PIC] option"Aleksandar Beserminji2018-05-071-12/+3
| | | | | | This reverts commit r331636. Forgot to add the test case. llvm-svn: 331639
* [mips] Improve handling of -fno-[pic/PIC] optionAleksandar Beserminji2018-05-071-3/+12
| | | | | | | | | | | | | In order to disable PIC and to match GCC behaviour, -mno-abicalls option is neccessary. When -fno-[pic/PIC] is used witout -mno-abicalls, warning is reported. An error is reported when -fno-pic or -fno-PIC is used in combination with -mabicalls. Depends on D44381. Differential Revision: https://reviews.llvm.org/D44684 llvm-svn: 331636
* Switch to Clang's isDigit function.Richard Trieu2018-04-251-4/+4
| | | | | | | | std::isdigit can be overloaded, causing the template deduction to fail. Use Clang's isDigit function which to avoid this. Switch the other calls for consistency. llvm-svn: 330887
* Include <cctype> to get std::isdigit, fixes MSVC STL buildReid Kleckner2018-04-251-0/+1
| | | | llvm-svn: 330886
* [RISCV] More validations on the input value of -march=Ana Pazos2018-04-251-20/+270
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Supporting additional rules for parsing ISA string. - RISC-V ISA strings must be lowercase. E.g.: rv32IMC is not supported, rv32imc is correct. - Multi-letter extensions are to be separated by a single underscore '_'. The extension prefix counts as a letter. This means extensions that start with 's', 'sx' and 'sx' are all multi-letter. E.g.: xasb is a single non-standard extension named 'xasb' xa_sb are two extensions, the non-standard user level extension 'xa', and the supervisor level extension 'sb'. - Standard user-level extensions are specified following a canonical order, according to Table 22.1 in RISC-V User-Level ISA V2.2. - Non-standard user-level 'x' extensions, standard supervisor-level 's' extensions and non-standard supervisor-level 'sx' extensions are also specified following a canonical order according to Table 22.1 in RISC-V User-Level ISA V2.2: 'x' extensions, follwed by 's' extensions and then 'sx' extensions. - Extensions might have a version number. Underscores may be used to separate ISA subset components to improve readability and to provide disambiguation. E.g.: rv32i2_m3_a1_f2_d2 - Version numbers are divided into major and minor numbers, separated by a 'p'. If the minor version is 0, then 'p0' can be omitted. - Additional checks for dependent extensions and invalid extensions combinations. E.g.: 'e' requires rv32 'e' can't be combined with 'f' nor 'd' 'q' requires rv64 - TODO items have also been marked with comments in the code. Reviewers: asb, kito-cheng Reviewed By: asb Subscribers: edward-jones, mgrang, zzheng, rbar, johnrusso, simoncook, jordy.potman.lists, sabuasal, niosHD, shiva0217, cfe-commits Differential Revision: https://reviews.llvm.org/D45284 llvm-svn: 330880
* [PowerPC] Option for secure plt modeStrahinja Petrovic2018-04-112-0/+17
| | | | | | | | | This patch enables option for secure plt mode in clang (-msecure-plt). Differential Revision: https://reviews.llvm.org/D44921 llvm-svn: 329795
* Fix typos in clangAlexander Kornienko2018-04-061-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Found via codespell -q 3 -I ../clang-whitelist.txt Where whitelist consists of: archtype cas classs checkk compres definit frome iff inteval ith lod methode nd optin ot pres statics te thru Patch by luzpaz! (This is a subset of D44188 that applies cleanly with a few files that have dubious fixes reverted.) Differential revision: https://reviews.llvm.org/D44188 llvm-svn: 329399
* [PATCH] [RISCV] Verify the input value of -march=Shiva Chen2018-03-281-6/+67
| | | | | | | | | | | | | | Summary: This patch doing more check and verify the -march= string and will issue an error if it's a invalid combination. Reviewers: asb, apazos Differential Revision: https://reviews.llvm.org/D44189 Patch by Kito Cheng. llvm-svn: 328690
* [mips] Spectre variant two mitigation for MIPSR2Simon Dardis2018-02-212-0/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch provides mitigation for CVE-2017-5715, Spectre variant two, which affects the P5600 and P6600. It provides the option -mindirect-jump=hazard, which instructs the LLVM backend to replace indirect branches with their hazard barrier variants. This option is accepted when targeting MIPS revision two or later. The migitation strategy suggested by MIPS for these processors is to use two hazard barrier instructions. 'jalr.hb' and 'jr.hb' are hazard barrier variants of the 'jalr' and 'jr' instructions respectively. These instructions impede the execution of instruction stream until architecturally defined hazards (changes to the instruction stream, privileged registers which may affect execution) are cleared. These instructions in MIPS' designs are not speculated past. These instructions are used with the option -mindirect-jump=hazard when branching indirectly and for indirect function calls. These instructions are defined by the MIPS32R2 ISA, so this mitigation method is not compatible with processors which implement an earlier revision of the MIPS ISA. Implementation note: I've opted to provide this as an -mindirect-jump={hazard,...} style option in case alternative mitigation methods are required for other implementations of the MIPS ISA in future, e.g. retpoline style solutions. Reviewers: atanasyan Differential Revision: https://reviews.llvm.org/D43487 llvm-svn: 325651
* [ARM] disable FPU features when using soft floating point.Keith Walker2018-02-191-5/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | To be compatible with GCC if soft floating point is in effect any FPU specified is effectively ignored, eg, -mfloat-abi=soft -fpu=neon If any floating point features which require FPU hardware are enabled they must be disable. There was some support for doing this for NEON, but it did not handle VFP, nor did it prevent the backend from emitting the build attribute Tag_FP_arch describing the generated code as using the floating point hardware if a FPU was specified (even though soft float does not use the FPU). Disabling the hardware floating point features for targets which are compiling for soft float has meant that some tests which were incorrectly checking for hardware support also needed to be updated. In such cases, where appropriate the tests have been updated to check compiling for soft float and a non-soft float variant (usually softfp). This was usually because the target specified in the test defaulted to soft float. Differential Revision: https://reviews.llvm.org/D42569 llvm-svn: 325492
* [clang-cl] Add support for /arch:AVX512F and /arch:AVX512Nico Weber2018-01-251-5/+6
| | | | | | | | | | | | | | | | | | | | | For /arch:AVX512F: clang-cl and cl.exe both defines __AVX512F__ __AVX512CD__. clang-cl also defines __AVX512ER__ __AVX512PF__. 64-bit cl.exe also defines (according to /Bz) _NO_PREFETCHW. For /arch:AVX512: clang-cl and cl.exe both define __AVX512F__ __AVX512CD__ __AVX512BW__ __AVX512DQ__ __AVX512VL__. 64-bit cl.exe also defines _NO_PREFETCHW. So not 100% identical, but pretty close. Also refactor the existing AVX / AVX2 code to not repeat itself in both the 32-bit and 64-bit cases. https://reviews.llvm.org/D42538 llvm-svn: 323433
* clang-cl: Simplify handling of /arch: flag.Nico Weber2018-01-251-27/+5
| | | | | | | | | | | | | | | | | | | r213083 initially implemented /arch: support by mapping it to CPU features. Then r241077 additionally mapped it to CPU, which made the feature flags redundant (if harmless). This change here removes the redundant mapping to feature flags, and rewrites test/Driver/cl-x86-flags.c to be a bit more of an integration test that checks for preprocessor defines like AVX (like documented on MSDN) instead of for driver flags. To keep emitting warn_drv_unused_argument, use getLastArgNoClaim() followed by an explicit claim() if needed. This is in preparation for adding support for /arch:AVX512(F). No intended behavior change. https://reviews.llvm.org/D42497 llvm-svn: 323426
* [RISCV] Add the RISCV target and compiler driverAlex Bradbury2018-01-112-0/+93
| | | | | | | | | As RV64 codegen has not yet been upstreamed into LLVM, we focus on RV32 driver support (RV64 to follow). Differential Revision: https://reviews.llvm.org/D39963 llvm-svn: 322276
* Revert [ARM] disable FPU features when using soft floating point.Keith Walker2017-11-301-15/+5
| | | | | | | This reverts r319420 It is failing the test Driver/arm-mfpu.c so reverting while I investigate the failure. llvm-svn: 319425
* [ARM] disable FPU features when using soft floating point.Keith Walker2017-11-301-5/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | To be compatible with GCC if soft floating point is in effect any FPU specified is effectively ignored, eg, -mfloat-abi=soft -fpu=neon If any floating point features which require FPU hardware are enabled they must be disable. There was some support for doing this for NEON, but it did not handle VFP, nor did it prevent the backend from emitting the build attribute Tag_FP_arch describing the generated code as using the floating point hardware if a FPU was specified (even though soft float does not use the FPU). Disabling the hardware floating point features for targets which are compiling for soft float has meant that some tests which were incorrectly checking for hardware support also needed to be updated. In such cases, where appropriate the tests have been updated to check compiling for soft float and a non-soft float variant (usually softfp). This was usually because the target specified in the test defaulted to soft float. Differential Revision: https://reviews.llvm.org/D40256 llvm-svn: 319420
* [AArch64] Fix PR34625 -mtune without -mcpu should not set -target-cpuPeter Smith2017-10-241-6/+10
| | | | | | | | | | | | | | | | | | | | When -mtune is used on AArch64 the -target-cpu is passed the value of the cpu given to -mtune. As well as setting micro-architectural features of the -mtune cpu, this will also add the architectural features such as support for instructions. This can result in the backend using instructions that are supported in the -mtune cpu but not supported in the target architecture. For example use of the v8.1-a LSE extensions with -march=v8. This change removes the setting of -target-cpu for -mtune, the -mcpu must be used to set -target-cpu. This has the effect of removing all non-hard coded benefits of mtune but it does produce correct output when -mtune cpu with a later architecture than v8 is used. Fixes PR34625 Differential Revision: https://reviews.llvm.org/D39179 llvm-svn: 316424
* [ARM] Option for reading thread pointer from coprocessor registerStrahinja Petrovic2017-09-122-0/+31
| | | | | | | | | This patch enables option for reading thread pointer directly from coprocessor register (-mtp=soft/cp15). Differential Revision: https://reviews.llvm.org/D34878 llvm-svn: 313018
* [mips] Replace Triple::Environment check by the isGNUEnvironment() call. NFCSimon Atanasyan2017-09-071-1/+1
| | | | llvm-svn: 312701
* [mips] Introducing option -mabs=[legacy/2008]Petar Jovanovic2017-08-241-0/+22
| | | | | | | | | | | | | | | | | In patch r205628 using abs.[ds] instruction is forced, as they should behave in accordance with flags Has2008 and ABS2008. Unfortunately for revisions prior mips32r6 and mips64r6, abs.[ds] is not generating correct result when working with NaNs. To generate a sequence which always produce a correct result but also to allow user more control on how his code is compiled, option -mabs is added where user can choose legacy or 2008. By default legacy mode is used on revisions prior R6. Mips32r6 and mips64r6 use abs2008 mode by default. Patch by Aleksandar Beserminji Differential Revision: https://reviews.llvm.org/D35982 llvm-svn: 311669
* [mips] Rename getSupportedNanEncoding() to getIEEE754Standard()Petar Jovanovic2017-08-222-25/+26
| | | | | | | | | | | Rename the function getSupportedNanEncoding() to getIEEE754Standard(), since this function will be used for non-nan related features. Patch by Aleksandar Beserminji. Differential Revision: https://reviews.llvm.org/D36824 llvm-svn: 311454
* [mips] Remove checking of the redundant condition. NFCSimon Atanasyan2017-08-211-2/+1
| | | | llvm-svn: 311334
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