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* [RISCV] Implement RISCV ABI loweringAlex Bradbury2018-01-151-0/+181
| | | | | | | | | | | | | | | | | | | | RISCVABIInfo is implemented in terms of XLen, supporting both RV32 and RV64. Unfortunately we need to count argument registers in the frontend in order to determine when to emit signext and zeroext attributes. Integer scalars are extended according to their type up to 32-bits and then sign-extended to XLen when passed in registers, but are anyext when passed on the stack. This patch only implements the base integer (soft float) ABIs. For more information on the RISC-V ABI, see [the ABI doc](https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md), my [golden model](https://github.com/lowRISC/riscv-calling-conv-model), and the [LLVM RISC-V calling convention patch](https://reviews.llvm.org/D39898#2d1595b4) (specifically the comment documenting frontend expectations). Differential Revision: https://reviews.llvm.org/D40023 llvm-svn: 322494
* Refactor handling of signext/zeroext in ABIArgInfoAlex Bradbury2018-01-121-51/+47
| | | | | | | | | | | | | | | | | | | | As @rjmccall suggested in D40023, we can get rid of ABIInfo::shouldSignExtUnsignedType (used to handle cases like the Mips calling convention where 32-bit integers are always sign extended regardless of the sign of the type) by adding a SignExt field to ABIArgInfo. In the common case, this new field is set automatically by ABIArgInfo::getExtend based on the sign of the type. For targets that want greater control, they can use ABIArgInfo::getSignExtend or ABIArgInfo::getZeroExtend when necessary. This change also cleans up logic in CGCall.cpp. There is no functional change intended in this patch, and all tests pass unchanged. As noted in D40023, Mips might want to sign-extend unsigned 32-bit integer return types. A future patch might modify MipsABIInfo::classifyReturnType to use MipsABIInfo::extendType. Differential Revision: https://reviews.llvm.org/D41999 llvm-svn: 322396
* Simplify the internal API for checking whether swiftcall passes a type ↵John McCall2018-01-071-12/+6
| | | | | | indirectly and expose that API externally. llvm-svn: 321957
* SystemZ Swift TargetInfo: swifterror support in the backend is brokenArnold Schwaighofer2017-11-071-1/+1
| | | | | | Return false for swifterror support until the backend is fixed. llvm-svn: 317589
* CodeGen: fix PPC Darwin variadicsSaleem Abdulrasool2017-10-251-1/+37
| | | | | | | | | Darwin uses char * for the variadic list type (va_list). We use the PPC SVR4 ABI for PPC, which uses a structure type for the va_list. When constructing the GEP, we would fail due to the incorrect handling for the va_list. Correct this to use the right type. llvm-svn: 316599
* [AMDGPU] Fix bug in enqueued block codegen due to an extra lineYaxun Liu2017-10-191-1/+0
| | | | llvm-svn: 316165
* Convert clang::LangAS to a strongly typed enumAlexander Richardson2017-10-151-19/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Convert clang::LangAS to a strongly typed enum Currently both clang AST address spaces and target specific address spaces are represented as unsigned which can lead to subtle errors if the wrong type is passed. It is especially confusing in the CodeGen files as it is not possible to see what kind of address space should be passed to a function without looking at the implementation. I originally made this change for our LLVM fork for the CHERI architecture where we make extensive use of address spaces to differentiate between capabilities and pointers. When merging the upstream changes I usually run into some test failures or runtime crashes because the wrong kind of address space is passed to a function. By converting the LangAS enum to a C++11 we can catch these errors at compile time. Additionally, it is now obvious from the function signature which kind of address space it expects. I found the following errors while writing this patch: - ItaniumRecordLayoutBuilder::LayoutField was passing a clang AST address space to TargetInfo::getPointer{Width,Align}() - TypePrinter::printAttributedAfter() prints the numeric value of the clang AST address space instead of the target address space. However, this code is not used so I kept the current behaviour - initializeForBlockHeader() in CGBlocks.cpp was passing LangAS::opencl_generic to TargetInfo::getPointer{Width,Align}() - CodeGenFunction::EmitBlockLiteral() was passing a AST address space to TargetInfo::getPointerWidth() - CGOpenMPRuntimeNVPTX::translateParameter() passed a target address space to Qualifiers::addAddressSpace() - CGOpenMPRuntimeNVPTX::getParameterAddress() was using llvm::Type::getPointerTo() with a AST address space - clang_getAddressSpace() returns either a LangAS or a target address space. As this is exposed to C I have kept the current behaviour and added a comment stating that it is probably not correct. Other than this the patch should not cause any functional changes. Reviewers: yaxunl, pcc, bader Reviewed By: yaxunl, bader Subscribers: jlebar, jholewinski, nhaehnle, Anastasia, cfe-commits Differential Revision: https://reviews.llvm.org/D38816 llvm-svn: 315871
* Fix build failure on android due to missing std::to_string()Yaxun Liu2017-10-141-1/+2
| | | | llvm-svn: 315805
* [OpenCL] Emit enqueued block as kernelYaxun Liu2017-10-141-0/+111
| | | | | | | | | | | | | | | | | In OpenCL the kernel function and non-kernel function has different calling conventions. For certain targets they have different argument ABIs. Also kernels have special function attributes and metadata for runtime to launch them. The blocks passed to enqueue_kernel is supposed to be executed as kernels. As such, the block invoke function should be emitted as kernel with proper calling convention and argument ABI. This patch emits enqueued block as kernel. If a block is both called directly and passed to enqueue_kernel, separate functions will be generated. Differential Revision: https://reviews.llvm.org/D38134 llvm-svn: 315804
* [ubsan] Function Sanitizer: Don't require writable text segmentsVedant Kumar2017-09-131-13/+6
| | | | | | | | | | | | | | | | | | This change will make it possible to use -fsanitize=function on Darwin and possibly on other platforms. It fixes an issue with the way RTTI is stored into function prologue data. On Darwin, addresses stored in prologue data can't require run-time fixups and must be PC-relative. Run-time fixups are undesirable because they necessitate writable text segments, which can lead to security issues. And absolute addresses are undesirable because they break PIE mode. The fix is to create a private global which points to the RTTI, and then to encode a PC-relative reference to the global into prologue data. Differential Revision: https://reviews.llvm.org/D37597 llvm-svn: 313096
* [CodeGen][x86_64] Enable 'force_align_arg_pointer' attribute at x86_64Erich Keane2017-08-301-0/+18
| | | | | | | | | | | | | This attribute is useful in OS development when we jump from 32 to 64 bit code and expect that 64bit function forces correct stack alignment. Related discussion: http://lists.llvm.org/pipermail/cfe-dev/2017-June/054358.html Patch By: anatol.pomozov (anatol.pomozov@gmail.com) Differential Revision:https://reviews.llvm.org/D36272 llvm-svn: 312173
* Add flag to request Clang is ABI-compatible with older versions of itselfRichard Smith2017-08-261-3/+12
| | | | | | | | | | | | | | | | | | This patch adds a flag -fclang-abi-compat that can be used to request that Clang attempts to be ABI-compatible with some older version of itself. This is provided on a best-effort basis; right now, this can be used to undo the ABI change in r310401, reverting Clang to its prior C++ ABI for pass/return by value of class types affected by that change, and to undo the ABI change in r262688, reverting Clang to using integer registers rather than SSE registers for passing <1 x long long> vectors. The intent is that we will maintain this backwards compatibility path as we make ABI-breaking fixes in future. The reversion to the old behavior for r310401 is also applied to the PS4 target since that change is not part of its platform ABI (which is essentially to do whatever Clang 3.2 did). llvm-svn: 311823
* [Clang][x86][Inline Asm] support for GCC style inline asm - Y<x> constraintsCoby Tayree2017-08-241-1/+5
| | | | | | | | | | This patch is intended to enable the use of basic double letter constraints used in GCC extended inline asm {Yi Y2 Yz Y0 Ym Yt}. Supersedes D35205 llvm counterpart: D36369 Differential Revision: https://reviews.llvm.org/D36371 llvm-svn: 311643
* [ObjC] Use consistent comment style in inline asmOliver Stannard2017-08-211-3/+3
| | | | | | | | | The comment markers accepted by the assembler vary between different targets, but '//' is always accepted, so we should use that for consistency. Differential revision: https://reviews.llvm.org/D36666 llvm-svn: 311325
* Revert r302670 for the upcoming 5.0.0 releaseStefan Maksimovic2017-08-111-8/+0
| | | | | | | | | | This is causing failures when compiling clang with -O3 as one of the structures used by clang is passed by value and uses the fastcc calling convention. Faliures manifest for stage2 mips build. llvm-svn: 310704
* Remove unused functionMatt Arsenault2017-08-101-9/+0
| | | | llvm-svn: 310540
* AMDGPU: Use direct struct returns and argumentsMatt Arsenault2017-08-091-17/+190
| | | | | | | | | | | | | | | | This is an improvement over always using byval for structs. This will use registers until ~16 are used, and then switch back to byval. This needs more work, since I'm not sure it ever really makes sense to use byval. If the register limit is exceeded, the arguments still end up passed on the stack, but with a different ABI. It also may make sense to base this on number of registers used for non-struct arguments, rather than just arguments that appear first in the argument list. llvm-svn: 310527
* Add OpenCL 2.0 atomic builtin functions as Clang builtinYaxun Liu2017-08-041-0/+27
| | | | | | | | | | | | | | | | | | | | | OpenCL 2.0 atomic builtin functions have a scope argument which is ideally represented as synchronization scope argument in LLVM atomic instructions. Clang supports translating Clang atomic builtin functions to LLVM atomic instructions. However it currently does not support synchronization scope of LLVM atomic instructions. Without this, users have to use LLVM assembly code to implement OpenCL atomic builtin functions. This patch adds OpenCL 2.0 atomic builtin functions as Clang builtin functions, which supports generating LLVM atomic instructions with synchronization scope operand. Currently only constant memory scope argument is supported. Support of non-constant memory scope argument will be added later. Differential Revision: https://reviews.llvm.org/D28691 llvm-svn: 310082
* [mips] Revert r309942 & r309940Simon Dardis2017-08-031-14/+0
| | | | | | | | This reverts commit r309942 & commit r309940. A revert was requested following post commit review. llvm-svn: 309978
* [mips] Implement -muninit-const-in-rodataSimon Dardis2017-08-031-0/+14
| | | | | | | | | | | This option when combined with -mgpopt and -membedded-data places all uninitialized constant variables in the read-only section. Reviewers: atanasyan, nitesh.jain Differential Revision: https://reviews.llvm.org/D35917 llvm-svn: 309940
* [CodeGen][ARM] ARM runtime helper functions are not always soft-fpPeter Smith2017-07-271-10/+7
| | | | | | | Re-commit r309257 with less precise register checks in arm-float-helpers.c test. llvm-svn: 309263
* [CodeGen][ARM] Revert r309257Peter Smith2017-07-271-7/+10
| | | | | | | The test arm-float-helpers.c appears to be failing on some builders and needs some work to make it more robust. llvm-svn: 309259
* [CodeGen][ARM] ARM runtime helper functions are not always soft-fpPeter Smith2017-07-271-10/+7
| | | | | | | | | | | | | | | | | | | The ARM Runtime ABI document (IHI0043) defines the AEABI floating point helper functions in 4.1.2 The floating-point helper functions. These functions always use the base PCS (soft-fp). However helper functions defined outside of this document such as the complex-number multiply and divide helpers are not covered by this requirement and should use hard-float PCS if the target is hard-float as both compiler-rt and libgcc for a hard-float sysroot implement these functions with a hard-float PCS. All of the floating point helper functions that are explicitly soft float are expanded in the llvm ARM backend. This change makes clang not force the BuiltinCC to AAPCS for AAPCS_VFP. With this change the ARM compiler-rt tests involving _Complex pass with both hard-fp and soft-fp targets. Differential Revision: https://reviews.llvm.org/D35538 llvm-svn: 309257
* Remove Bitrig: Clang ChangesErich Keane2017-07-211-1/+0
| | | | | | | | Bitrig code has been merged back to OpenBSD, thus the OS has been abandoned. Differential Revision: https://reviews.llvm.org/D35708 llvm-svn: 308797
* Complex Long Double classification In RegCall calling conventionErich Keane2017-07-211-13/+28
| | | | | | | | | | | | | This change is part of the RegCall calling convention support for LLVM. Existing RegCall implementation was extended to include correct handling of Complex Long Double type. Complex long double types should be returned/passed in memory and not register stack. This patch implements this behavior. Patch by: eandrews Differential Revision: https://reviews.llvm.org/D35259 llvm-svn: 308769
* [CodeGen][mips] Support `long_call/far/near` attributesSimon Atanasyan2017-07-201-37/+81
| | | | | | | | | | | This patch adds support for the `long_call`, `far`, and `near` attributes for MIPS targets. The `long_call` and `far` attributes are synonyms. All these attributes override `-mlong-calls` / `-mno-long-calls` command line options for particular function. Differential revision: https://reviews.llvm.org/D35479 llvm-svn: 308667
* [AArch64] Produce correct defaultlib directives for windows in MSVC styleMartin Storsjo2017-07-201-1/+18
| | | | | | Differential Revision: https://reviews.llvm.org/D35546 llvm-svn: 308584
* [AArch64] Produce the right kind of va_arg for windowsMartin Storsjo2017-07-131-3/+18
| | | | | | | | On windows on arm64, the va_list is a plain pointer. Differential Revision: https://reviews.llvm.org/D35008 llvm-svn: 307933
* Fix build failure with gcc about mixing enum and non-enumYaxun Liu2017-07-081-1/+2
| | | | llvm-svn: 307483
* CodeGen: Fix address space of global variableYaxun Liu2017-07-081-0/+46
| | | | | | | | | | | | | Certain targets (e.g. amdgcn) require global variable to stay in global or constant address space. In C or C++ global variables are emitted in the default (generic) address space. This patch introduces virtual functions TargetCodeGenInfo::getGlobalVarAddressSpace and TargetInfo::getConstantAddressSpace to handle this in a general approach. It only affects IR generated for amdgcn target. Differential Revision: https://reviews.llvm.org/D33842 llvm-svn: 307470
* Correct VectorCall x86 (32 bit) behavior for SSE Register AssignmentErich Keane2017-06-211-72/+56
| | | | | | | | | | | | | | | | | | | In running some internal vectorcall tests in 32 bit mode, we discovered that the behavior I'd previously implemented for x64 (and applied to x32) regarding the assignment of SSE registers was incorrect. See spec here: https://msdn.microsoft.com/en-us/library/dn375768.aspx My previous implementation applied register argument position from the x64 version to both. This isn't correct for x86, so this removes and refactors that section. Additionally, it corrects the integer/int-pointer assignments. Unlike x64, x86 permits integers to be assigned independent of position. Finally, the code for 32 bit was cleaned up a little to clarify the intent, as well as given a descriptive comment. Differential Revision: https://reviews.llvm.org/D34455 llvm-svn: 305928
* [OpenCL] Fix OpenCL and SPIR version metadata generation.Alexey Bader2017-06-201-41/+0
| | | | | | | | | | | | | | Summary: OpenCL and SPIR version metadata must be generated once per module instead of once per mangled global value. Reviewers: Anastasia, yaxunl Reviewed By: Anastasia Subscribers: ahatanak, cfe-commits Differential Revision: https://reviews.llvm.org/D34235 llvm-svn: 305796
* [OpenCL] Makes kernels use the SPIR_KERNEL CC by default.Pekka Jaaskelainen2017-06-011-1/+21
| | | | | | | | | | | | | | | | Rationale: OpenCL kernels are called via an explicit runtime API with arguments set with clSetKernelArg(), not as normal sub-functions. Return SPIR_KERNEL by default as the kernel calling convention to ensure the fingerprint is fixed such way that each OpenCL argument gets one matching argument in the produced kernel function argument list to enable feasible implementation of clSetKernelArg() with aggregates etc. In case we would use the default C calling conv here, clSetKernelArg() might break depending on the target-specific conventions; different targets might split structs passed as values to multiple function arguments etc. https://reviews.llvm.org/D33639 llvm-svn: 304389
* CodeGen: Define Swift's legal vector types for AArch64, ARMArnold Schwaighofer2017-05-261-0/+30
| | | | | | rdar://32401301 llvm-svn: 304017
* [mips] Support `micromips` attributeSimon Atanasyan2017-05-221-0/+5
| | | | | | | | | This patch adds support for the `micromips` and `nomicromips` attributes for MIPS targets. Differential revision: https://reviews.llvm.org/D33363 llvm-svn: 303546
* CodeGen: Cast alloca to expected address spaceYaxun Liu2017-05-181-4/+8
| | | | | | | | | | | Alloca always returns a pointer in alloca address space, which may be different from the type defined by the language. For example, in C++ the auto variables are in the default address space. Therefore cast alloca to the expected address space when necessary. Differential Revision: https://reviews.llvm.org/D32248 llvm-svn: 303370
* [Hexagon] Make sure to pass empty struct arguments with nontrivial ctorsKrzysztof Parzyszek2017-05-121-3/+3
| | | | | | | | Thanks to Richard Smith for the suggested fix. This fixes llvm.org/PR33009 llvm-svn: 302895
* Reland: [mips] Impose a threshold for coercion of aggregatesPetar Jovanovic2017-05-101-0/+8
| | | | | | | | | | | | | | Modified MipsABIInfo::classifyArgumentType so that it now coerces aggregate structures only if the size of said aggregate is less than 16/64 bytes, depending on the ABI. Patch by Stefan Maksimovic. Differential Revision: https://reviews.llvm.org/D32900 with minor changes (use regexp instead of the hardcoded values) to the test. llvm-svn: 302670
* Suppress all uses of LLVM_END_WITH_NULL. NFC.Serge Guelton2017-05-091-6/+4
| | | | | | | | | | Use variadic templates instead of relying on <cstdarg> + sentinel. This enforces better type checking and makes code more readable. Differential revision: https://reviews.llvm.org/D32550 llvm-svn: 302572
* Revert r302547 ([mips] Impose a threshold for coercion of aggregates)Petar Jovanovic2017-05-091-8/+0
| | | | | | | | | | Reverting Modified MipsABIInfo::classifyArgumentType so that it now coerces aggregate structures only if the size of said aggregate is less than 16/64 bytes, depending on the ABI. as it broke clang-with-lto-ubuntu builder. llvm-svn: 302555
* [mips] Impose a threshold for coercion of aggregatesPetar Jovanovic2017-05-091-0/+8
| | | | | | | | | | | | Modified MipsABIInfo::classifyArgumentType so that it now coerces aggregate structures only if the size of said aggregate is less than 16/64 bytes, depending on the ABI. Patch by Stefan Maksimovic. Differential Revision: https://reviews.llvm.org/D32900 llvm-svn: 302547
* AArch64: fix weird edge case in ABI.Tim Northover2017-05-051-4/+9
| | | | | | | | | | | | | | | | | It turns out there are some sort-of-but-not-quite empty structs that break all the rules. For example: struct SuperEmpty { int arr[0]; }; struct SortOfEmpty { struct SuperEmpty e; }; Both of these have sizeof == 0, even in C++ mode, for GCC compatibility. The first one also doesn't occupy a register when passed by value in GNU C++ mode, unlike everything else. On Darwin, we want to ignore the lot (and especially don't want to try to use an i0 as we were). llvm-svn: 302313
* Re-land r301697 "[IR] Make add/remove Attributes use AttrBuilder instead of ↵Reid Kleckner2017-05-021-8/+2
| | | | | | | | | | AttributeList" This time, I fixed, built, and tested clang. This reverts r301712. llvm-svn: 301981
* [AMDGPU] Translate reqd_work_group_size into amdgpu_flat_work_group_sizeStanislav Mekhanoshin2017-04-061-3/+8
| | | | | | | | | | | | | These two attributes specify the same info in a different way. AMGPU BE only checks the latter as a target specific attribute as opposed to language specific reqd_work_group_size. This change produces amdgpu_flat_work_group_size out of reqd_work_group_size if specified. Differential Revision: https://reviews.llvm.org/D31728 llvm-svn: 299678
* [TargetInfo] Use llvm::alignOf() instead of rewriting it. NFCI.Davide Italiano2017-04-031-2/+2
| | | | llvm-svn: 299364
* Update Clang for LLVM rename AttributeSet -> AttributeListReid Kleckner2017-03-211-8/+8
| | | | llvm-svn: 298394
* CodeGen: use # as the comment leader for ARC markerSaleem Abdulrasool2017-02-111-1/+1
| | | | | | | | | | Use # as the comment leader for AArch64 auto-release elision marker. This is to keep it in sync with the value used in swift. When building libdispatch for Linux AArch64, the auto-release elision marker was emitted. However, ELF uses # as the comment leader while MachO accepts both ; and #. Use the common marker for it instead. llvm-svn: 294877
* [AVR] Add support for the 'interrupt' and 'naked' attributesDylan McKay2017-02-081-0/+28
| | | | | | | | | | | | | | | | Summary: This teaches clang how to parse and lower the 'interrupt' and 'naked' attributes. This allows interrupt signal handlers to be written. Reviewers: aaron.ballman Subscribers: malcolm.parsons, cfe-commits Differential Revision: https://reviews.llvm.org/D28451 llvm-svn: 294402
* Use less byval on 32-bit Windows x86 for classes with basesReid Kleckner2017-01-131-22/+38
| | | | | | | | | | | | This comes up in V8, which has a Handle template class that wraps a typed pointer, and is frequently passed by value. The pointer is stored in the base, HandleBase. This change allows us to pass the struct as a pointer instead of using byval. This avoids creating tons of temporary allocas that we copy from during call lowering. Eventually, it would be good to use FCAs here instead. llvm-svn: 291917
* Correct Vectorcall Register passing and HVA BehaviorErich Keane2017-01-051-26/+180
| | | | | | | | | | | | | Front end component (back end changes are D27392). The vectorcall calling convention was broken subtly in two cases. First, it didn't properly handle homogeneous vector aggregates (HVAs). Second, the vectorcall specification requires that only the first 6 parameters be eligible for register assignment. This patch fixes both issues. Differential Revision: https://reviews.llvm.org/D27529 llvm-svn: 291041
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