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* AArch64: fix weird edge case in ABI.Tim Northover2017-05-051-4/+9
| | | | | | | | | | | | | | | | | It turns out there are some sort-of-but-not-quite empty structs that break all the rules. For example: struct SuperEmpty { int arr[0]; }; struct SortOfEmpty { struct SuperEmpty e; }; Both of these have sizeof == 0, even in C++ mode, for GCC compatibility. The first one also doesn't occupy a register when passed by value in GNU C++ mode, unlike everything else. On Darwin, we want to ignore the lot (and especially don't want to try to use an i0 as we were). llvm-svn: 302313
* Re-land r301697 "[IR] Make add/remove Attributes use AttrBuilder instead of ↵Reid Kleckner2017-05-021-8/+2
| | | | | | | | | | AttributeList" This time, I fixed, built, and tested clang. This reverts r301712. llvm-svn: 301981
* [AMDGPU] Translate reqd_work_group_size into amdgpu_flat_work_group_sizeStanislav Mekhanoshin2017-04-061-3/+8
| | | | | | | | | | | | | These two attributes specify the same info in a different way. AMGPU BE only checks the latter as a target specific attribute as opposed to language specific reqd_work_group_size. This change produces amdgpu_flat_work_group_size out of reqd_work_group_size if specified. Differential Revision: https://reviews.llvm.org/D31728 llvm-svn: 299678
* [TargetInfo] Use llvm::alignOf() instead of rewriting it. NFCI.Davide Italiano2017-04-031-2/+2
| | | | llvm-svn: 299364
* Update Clang for LLVM rename AttributeSet -> AttributeListReid Kleckner2017-03-211-8/+8
| | | | llvm-svn: 298394
* CodeGen: use # as the comment leader for ARC markerSaleem Abdulrasool2017-02-111-1/+1
| | | | | | | | | | Use # as the comment leader for AArch64 auto-release elision marker. This is to keep it in sync with the value used in swift. When building libdispatch for Linux AArch64, the auto-release elision marker was emitted. However, ELF uses # as the comment leader while MachO accepts both ; and #. Use the common marker for it instead. llvm-svn: 294877
* [AVR] Add support for the 'interrupt' and 'naked' attributesDylan McKay2017-02-081-0/+28
| | | | | | | | | | | | | | | | Summary: This teaches clang how to parse and lower the 'interrupt' and 'naked' attributes. This allows interrupt signal handlers to be written. Reviewers: aaron.ballman Subscribers: malcolm.parsons, cfe-commits Differential Revision: https://reviews.llvm.org/D28451 llvm-svn: 294402
* Use less byval on 32-bit Windows x86 for classes with basesReid Kleckner2017-01-131-22/+38
| | | | | | | | | | | | This comes up in V8, which has a Handle template class that wraps a typed pointer, and is frequently passed by value. The pointer is stored in the base, HandleBase. This change allows us to pass the struct as a pointer instead of using byval. This avoids creating tons of temporary allocas that we copy from during call lowering. Eventually, it would be good to use FCAs here instead. llvm-svn: 291917
* Correct Vectorcall Register passing and HVA BehaviorErich Keane2017-01-051-26/+180
| | | | | | | | | | | | | Front end component (back end changes are D27392). The vectorcall calling convention was broken subtly in two cases. First, it didn't properly handle homogeneous vector aggregates (HVAs). Second, the vectorcall specification requires that only the first 6 parameters be eligible for register assignment. This patch fixes both issues. Differential Revision: https://reviews.llvm.org/D27529 llvm-svn: 291041
* Re-commit r289252 and r289285, and fix PR31374Yaxun Liu2016-12-151-1/+35
| | | | llvm-svn: 289787
* Revert 289252 (and follow-up 289285), it caused PR31374Nico Weber2016-12-141-35/+1
| | | | llvm-svn: 289713
* Replace APFloatBase static fltSemantics data members with getter functionsStephan Bergmann2016-12-141-7/+7
| | | | | | | | | | | | | At least the plugin used by the LibreOffice build (<https://wiki.documentfoundation.org/Development/Clang_plugins>) indirectly uses those members (through inline functions in LLVM/Clang include files in turn using them), but they are not exported by utils/extract_symbols.py on Windows, and accessing data across DLL/EXE boundaries on Windows is generally problematic. Differential Revision: https://reviews.llvm.org/D26671 llvm-svn: 289647
* Add support for non-zero null pointer for C and OpenCLYaxun Liu2016-12-091-1/+35
| | | | | | | | | | | | | | | | | | In amdgcn target, null pointers in global, constant, and generic address space take value 0 but null pointers in private and local address space take value -1. Currently LLVM assumes all null pointers take value 0, which results in incorrectly translated IR. To workaround this issue, instead of emit null pointers in local and private address space, a null pointer in generic address space is emitted and casted to local and private address space. Tentative definition of global variables with non-zero initializer will have weak linkage instead of common linkage since common linkage requires zero initializer and does not have explicit section to hold the non-zero value. Virtual member functions getNullPointer and performAddrSpaceCast are added to TargetCodeGenInfo which by default returns ConstantPointerNull and emitting addrspacecast instruction. A virtual member function getNullPointerValue is added to TargetInfo which by default returns 0. Each target can override these virtual functions to get target specific null pointer and the null pointer value for specific address space, and perform specific translations for addrspacecast. Wrapper functions getNullPointer is added to CodegenModule and getTargetNullPointerValue is added to ASTContext to facilitate getting the target specific null pointers and their values. This change has no effect on other targets except amdgcn target. Other targets can provide support of non-zero null pointer in a similar way. This change only provides support for non-zero null pointer for C and OpenCL. Supporting for other languages will be added later incrementally. Differential Revision: https://reviews.llvm.org/D26196 llvm-svn: 289252
* [OpenCL] Fix SPIR version generation.Alexey Bader2016-12-071-2/+4
| | | | | | | | | | | | Patch by Egor Churaev (echuraev). Reviewers: Anastasia Subscribers: bader, yaxunl, cfe-commits Differential Revision: https://reviews.llvm.org/D27300 llvm-svn: 288890
* swiftcc: Add an api to query whether a target ABI stores swifterror in a ↵Arnold Schwaighofer2016-12-011-0/+21
| | | | | | register llvm-svn: 288394
* IRGen: Remove all uses of CreateDefaultAlignedLoad.Peter Collingbourne2016-11-281-5/+7
| | | | | | Differential Revision: https://reviews.llvm.org/D27157 llvm-svn: 288083
* Add a little endian variant of TCE.Pekka Jaaskelainen2016-11-161-0/+1
| | | | llvm-svn: 287112
* regcall: Implement regcall Calling Conv in clangErich Keane2016-11-021-26/+125
| | | | | | | | | | This patch implements the register call calling convention, which ensures as many values as possible are passed in registers. CodeGen changes were committed in https://reviews.llvm.org/rL284108. Differential Revision: https://reviews.llvm.org/D25204 llvm-svn: 285849
* Fix Clang-tidy readability-redundant-string-cstr warningsMalcolm Parsons2016-11-021-2/+2
| | | | | | | | | | Reviewers: aaron.ballman, mehdi_amini, dblaikie Subscribers: cfe-commits Differential Revision: https://reviews.llvm.org/D26206 llvm-svn: 285799
* Declare WinX86_64ABIInfo to satisfy SwiftABI infoArnold Schwaighofer2016-10-121-2/+8
| | | | | | | | | This is minimal support that allows swift's test cases on non windows platforms to pass. rdar://28738985 llvm-svn: 284032
* [PowerPC] Enable soft-float for PPC64, and +soft-float -> -hard-floatHal Finkel2016-10-021-7/+19
| | | | | | | | | | Enable soft-float support on PPC64, as the backend now supports it. Also, the backend now uses -hard-float instead of +soft-float, so set the target features accordingly. Fixes PR26970. llvm-svn: 283061
* [AMDGPU] Expose flat work group size, register and wave control attributesKonstantin Zhuravlyov2016-09-261-11/+41
| | | | | | | | | __attribute__((amdgpu_flat_work_group_size(<min>, <max>))) - request minimum and maximum flat work group size __attribute__((amdgpu_waves_per_eu(<min>[, <max>]))) - request minimum and/or maximum waves per execution unit Differential Revision: https://reviews.llvm.org/D24513 llvm-svn: 282371
* CodeGen: simplify the logic a slight bitSaleem Abdulrasool2016-09-141-4/+0
| | | | | | | | | Move the definition of `getTriple()` into the header. It would just call `getTarget().getTriple()`. Inline the definition to allow the compiler to see the same amount of the layout as previously. Remove the more verbose `getTarget().getTriple()` in favour of `getTriple()`. llvm-svn: 281487
* Fix whitespace issuesMatt Arsenault2016-09-071-2/+1
| | | | | | ^M and extra space llvm-svn: 280786
* [PowerPC] Update the DWARF register-size tableHal Finkel2016-08-301-3/+9
| | | | | | | | | The PPC64 DWARF register-size table did not match the ABI specification (or GCC, for that matter). Fix that, and add a regression test. Fixes PR27931. llvm-svn: 280053
* [MS] Win64 va_arg should expect large arguments to be passed indirectlyReid Kleckner2016-08-251-1/+11
| | | | | | Fixes PR20569 llvm-svn: 279774
* AMDGPU: Handle structs directly in AMDGPUABIInfoMatt Arsenault2016-08-221-1/+41
| | | | | | | | | | | | | | | | Structs are currently handled as pointer + byval, which makes AMDGPU LLVM backend generate incorrect code when structs are used. This patch changes struct argument to be handled directly and without flattening, which Clover (Mesa 3D Gallium OpenCL state tracker) will be able to handle. Flattening would expand the struct to individual elements and pass each as a separate argument, which Clover can not handle. Furthermore, such expansion does not fit the OpenCL programming model which requires to explicitely specify each argument index, size and memory location. Patch by Vedran Miletić llvm-svn: 279463
* [CodeGen] Ignore unnamed bitfields before handling vector fieldsDavid Majnemer2016-08-151-4/+5
| | | | | | | | | | | | We processed unnamed bitfields after our logic for non-vector field elements in records larger than 128 bits. The vector logic would determine that the bit-field disqualifies the record from occupying a register despite the unnamed bit-field not participating in the record size nor its alignment. N.B. This behavior matches GCC and ICC. llvm-svn: 278656
* [CodeGen] Correctly implement the AVX512 psABI rulesDavid Majnemer2016-08-151-7/+10
| | | | | | | | | | | | | | An __m512 vector type wrapped in a structure should be passed in a vector register. Our prior implementation was based on a draft version of the psABI. This fixes PR28975. N.B. The update to the ABI was made here: https://github.com/hjl-tools/x86-psABI/commit/30f9c9 llvm-svn: 278655
* Revert "[Attr] Add support for the `ms_hook_prologue` attribute."Charles Davis2016-08-081-8/+0
| | | | | | | This reverts commit r278050. It depends on r278048, which will be reverted. llvm-svn: 278052
* [Attr] Add support for the `ms_hook_prologue` attribute.Charles Davis2016-08-081-0/+8
| | | | | | | | | | | | | | | | | | | | | | | Summary: Based on a patch by Michael Mueller. This attribute specifies that a function can be hooked or patched. This mechanism was originally devised by Microsoft for hotpatching their binaries (which they're constantly updating to stay ahead of crackers, script kiddies, and other ne'er-do-wells on the Internet), but it's now commonly abused by Windows programs that want to hook API functions. It is for this reason that this attribute was added to GCC--hence the name, `ms_hook_prologue`. Depends on D19908. Reviewers: rnk, aaron.ballman Subscribers: cfe-commits Differential Revision: https://reviews.llvm.org/D19909 llvm-svn: 278050
* [OpenCL] Fix size of image typeYaxun Liu2016-08-031-9/+0
| | | | | | | | | | The size of image type is reported incorrectly as size of a pointer to address space 0, which causes error when casting image type to pointers by __builtin_astype. The fix is to get image address space from TargetInfo then report the size accordingly. Differential Revision: https://reviews.llvm.org/D22927 llvm-svn: 277647
* Adjust coercion of aggregates on RenderScriptPirama Arumuga Nainar2016-07-271-0/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: In RenderScript, the size of the argument or return value emitted in the IR is expected to be the same as the size of corresponding qualified type. For ARM and AArch64, the coercion performed by Clang can change the parameter or return value to a type whose size is different (usually larger) than the original aggregate type. Specifically, this can happen in the following cases: - Aggregate parameters of size <= 64 bytes and return values smaller than 4 bytes on ARM - Aggregate parameters and return values smaller than bytes on AArch64 This patch coerces the cases above to an integer array that is the same size and alignment as the original aggregate. A new field is added to TargetInfo to detect a RenderScript target and limit this coercion just to that case. Tests added to test/CodeGen/renderscript.c Reviewers: rsmith Subscribers: aemerson, srhines, llvm-commits Differential Revision: https://reviews.llvm.org/D22822 llvm-svn: 276904
* [OpenCL] AMDGCN target will generate images in constant address spaceYaxun Liu2016-07-201-0/+10
| | | | | | | | | | | | | Allows AMDGCN target to generate images (such as %opencl.image2d_t) in constant address space. Images will still be generated in global address space by default. Added tests to existing opencl-types.cl in test\CodeGenOpenCL. Patch by Aaron En Ye Shi. Differential Revision: https://reviews.llvm.org/D22523 llvm-svn: 276161
* [OpenCL] Fixes bug of missing OCL version metadata on the AMDGCN targetYaxun Liu2016-07-191-1/+12
| | | | | | | | | | | | Added the opencl.ocl.version metadata to be emitted with amdgcn. Created a static function emitOCLVerMD which is shared between triple spir and target amdgcn. Also added new testcases to existing test file, spir_version.cl inside test/CodeGenOpenCL. Patch by Aaron En Ye Shi. Differential Revision: https://reviews.llvm.org/D22424 llvm-svn: 276010
* Use arrays or initializer lists to feed ArrayRefs instead of SmallVector ↵Benjamin Kramer2016-07-021-3/+2
| | | | | | | | where possible. No functionality change intended llvm-svn: 274432
* AMDGPU: Set amdgpu_kernel calling convention for OpenCL kernels.Nikolay Haustov2016-06-301-0/+13
| | | | | | | | | | | | | | | | | | Summary: Summary: Change Clang calling convention SpirKernel to OpenCLKernel. Set calling convention OpenCLKernel for amdgcn as well. Add virtual method .getOpenCLKernelCallingConv() to TargetCodeGenInfo and use it to set target calling convention for AMDGPU and SPIR. Update tests. Reviewers: rsmith, tstellarAMD, Anastasia, yaxunl Subscribers: kzhuravl, cfe-commits Differential Revision: http://reviews.llvm.org/D21367 llvm-svn: 274220
* Add support for musl-libc on ARM Linux.Rafael Espindola2016-06-241-0/+4
| | | | | | Patch by Lei Zhang! llvm-svn: 273735
* This patch fixes problem with passing structures and unionsStrahinja Petrovic2016-06-241-1/+2
| | | | | | | | smaller than register as argument in variadic functions on big endian architectures. Differential Revision: http://reviews.llvm.org/D21611 llvm-svn: 273665
* CodeGen: support linker options on Windows ARMSaleem Abdulrasool2016-06-231-0/+10
| | | | | | | | We would incorrectly emit the directive sections due to the missing overridden methods. We now emit the expected "/DEFAULTLIB" rather than "-l" options for requested linkage llvm-svn: 273558
* [Sparc] Complex return value ABI compliance.Chris Dewhurst2016-06-081-0/+45
| | | | | | | | | | | | According to the Sparc V8 ABI, complex numbers should be passed and returned as pairs of registers: https://docs.oracle.com/cd/E26502_01/html/E28387/gentextid-2734.html This fix ensures this is the case. Without this, complex numbers are returned as a struct of two floats, which breaks the ABI rules. Differential Review: http://reviews.llvm.org/D20955 llvm-svn: 272149
* Use new triple API to check comdat /NFCXinliang David Li2016-05-251-1/+1
| | | | llvm-svn: 270728
* Fix some typos.Richard Smith2016-05-141-7/+7
| | | | llvm-svn: 269528
* [CodeGen] Clang does not choose aapcs-vfp calling convention for ARM bare ↵Oleg Ranevskyy2016-05-131-1/+2
| | | | | | | | | | | | | | | | | | | metal target with hard float (EABIHF) Summary: Clang does not detect `aapcs-vfp` for the EABIHF environment. The reason is that only GNUEABIHF is considered while choosing calling convention, EABIHF is ignored. This causes clang to use `aapcs` for EABIHF and add the `arm_aapcscc` specifier to functions in generated IR. The modified `arm-cc.c` test checks that no calling convention specifier is added to functions for EABIHF, which means the default one is used (`CallingConv::ARM_AAPCS_VFP`). Reviewers: rengolin, compnerd, t.p.northover Subscribers: aemerson, rengolin, asl, cfe-commits Differential Revision: http://reviews.llvm.org/D20219 llvm-svn: 269419
* Revert "AMDGPU/SI: Use amdgpu_kernel calling convention for OpenCL kernels."Nikolay Haustov2016-05-061-8/+0
| | | | | | | | This reverts commit f7053ec90d0fc56f0837e43c2c759e85b56c21a1. It broke calling OpenCL kernel from another kernel. llvm-svn: 268740
* AMDGPU/SI: Use amdgpu_kernel calling convention for OpenCL kernels.Nikolay Haustov2016-05-061-0/+8
| | | | | | | | | | Reviewers: tstellarAMD, arsenm Subscribers: cfe-commits Differential Revision: http://reviews.llvm.org/D19918 llvm-svn: 268718
* AArch64: fixup comment after changeTim Northover2016-05-031-1/+1
| | | | llvm-svn: 268423
* AArch64: simplify illegal vector check. NFC.Tim Northover2016-05-031-1/+1
| | | | | | | | Use a utility function to check whether the number of elements is a power of 2 and drop the redundant upper limit (a 128-bit vector with more than 16 elements would have each element < 8 bits, not possible). llvm-svn: 268422
* Expand aggregate arguments more often on 32-bit WindowsReid Kleckner2016-05-021-83/+89
| | | | | | | | | | | | | | | | | | | | Before this change, we would pass all non-HFA record arguments on Windows with byval. Byval often blocks optimizations and results in bad code generation. Windows now uses the existing workaround that other x86_32 platforms use. I also expanded the workaround to handle C++ records with constructors on Windows. On non-Windows platforms, we have to keep generating the same LLVM IR prototypes if we want our bitcode to be ABI compatible. Otherwise we will encounter mismatch issues like PR21573. Essentially fixes PR27522 in Clang instead of LLVM. Reviewers: hans Differential Revision: http://reviews.llvm.org/D19756 llvm-svn: 268261
* [SystemZ] Support Swift calling conventionBryan Chan2016-04-281-2/+8
| | | | | | | | | | | | | | | Summary: Port rL265324 to SystemZ to allow using the 'swiftcall' attribute on that architecture. Depends on D19414. Reviewers: kbarton, rjmccall, uweigand Subscribers: cfe-commits Differential Revision: http://reviews.llvm.org/D19432 llvm-svn: 267879
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