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* [SPIR] Remove an assert mandating SPIR for OpenCL sources only.Anastasia Stulova2016-04-261-1/+0
| | | | | | | | | SPIR target can be used for C/C++ inputs too (i.e. in OpenCL compatible mode for the libs creation). Patch by Neil Henning! Review: http://reviews.llvm.org/D19478 llvm-svn: 267561
* trying to fix the windows build broken by r267496Kostya Serebryany2016-04-261-1/+1
| | | | llvm-svn: 267513
* [lanai] Update handling of structs in arguments to be passed in registers.Jacques Pienaar2016-04-261-7/+59
| | | | | | Previously aggregate types were passed byval, change the ABI to pass these in registers instead. llvm-svn: 267496
* [CodeGen] Widen non-power-of-2 vector HFA base types.Ahmed Bougacha2016-04-191-1/+12
| | | | | | | | | | | | | | | | | | | | | | | Currently, for the ppc64--gnu and aarch64 ABIs, we recognize: typedef __attribute__((__ext_vector_type__(3))) float v3f32; typedef __attribute__((__ext_vector_type__(16))) char v16i8; struct HFA { v3f32 a; v16i8 b; }; as an HFA. Since the first type encountered is used as the base type, we pass the HFA as: [2 x <3 x float>] Which leads to incorrect IR (relying on padding values) when the second field is used. Instead, explicitly widen the vector (after size rounding) in isHomogeneousAggregate. Differential Revision: http://reviews.llvm.org/D18998 llvm-svn: 266784
* [CodeGen] Fix whitespace. NFC.Ahmed Bougacha2016-04-191-1/+1
| | | | llvm-svn: 266783
* [CodeGen] Avoid ctor/dtor boilerplate with some C++11Reid Kleckner2016-04-131-62/+61
| | | | | | | | | | | | | | Non-owning pointers that cache LLVM types and constants can use 'nullptr' default member initializers so that we don't need to mention them in the constructor initializer list. Owning pointers should use std::unique_ptr so that we don't need to manually delete them in the destructor. They also don't need to be mentioned in the constructor at that point. NFC llvm-svn: 266263
* revert SVN r265702, r265640Saleem Abdulrasool2016-04-081-3/+2
| | | | | | | | | | | Revert the two changes to thread CodeGenOptions into the TargetInfo allocation and to fix the layering violation by moving CodeGenOptions into Basic. Code Generation is arguably not particularly "basic". This addresses Richard's post-commit review comments. This change purely does the mechanical revert and will be followed up with an alternate approach to thread the desired information into TargetInfo. llvm-svn: 265806
* Basic: move CodeGenOptions from FrontendSaleem Abdulrasool2016-04-071-2/+3
| | | | | | | | This is a mechanical move of CodeGenOptions from libFrontend to libBasic. This fixes the layering violation introduced earlier by threading CodeGenOptions into TargetInfo. It should also fix the modules based self-hosting builds. NFC. llvm-svn: 265702
* Move class into an anonymous namespace. NFC.Benjamin Kramer2016-04-071-0/+2
| | | | llvm-svn: 265654
* IRGen-level lowering for the Swift calling convention.John McCall2016-04-041-8/+79
| | | | llvm-svn: 265324
* [lanai] Add Lanai backend to clang driver.Jacques Pienaar2016-03-281-0/+74
| | | | | | | | | | Changes to clang to add Lanai backend. Adds a new target, ABI and toolchain. General Lanai backend discussion on llvm-dev thread "[RFC] Lanai backend" (http://lists.llvm.org/pipermail/llvm-dev/2016-February/095118.html). Differential Revision: http://reviews.llvm.org/D17002 llvm-svn: 264655
* [OpenCL] Add ocl and spir version for spir targetXiuli Pan2016-03-241-0/+44
| | | | | | | | | | | | Summary: Add opencl.spir.version and opencl.ocl.version metadata for CodeGen to identify OpenCL version. Reviewers: yaxunl, Anastasia Subscribers: cfe-commits, pekka.jaaskelainen Differential Revision: http://reviews.llvm.org/D17596 llvm-svn: 264241
* Add -fnative-half-arguments-and-returnsPirama Arumuga Nainar2016-03-181-2/+2
| | | | | | | | | | | | | | | | | | Summary: r246764 handled __fp16 arguments and returns for AAPCS, but skipped this handling for OpenCL. Simlar to OpenCL, RenderScript also handles __fp16 type natively. This patch adds the -fnative-half-arguments-and-returns command line flag to allow such languages to skip this coercion of __fp16. Reviewers: srhines, olista01 Subscribers: cfe-commits Differential Revision: http://reviews.llvm.org/D18138 llvm-svn: 263795
* Add a coerce-and-expand ABIArgInfo as a generalization of someJohn McCall2016-03-111-0/+7
| | | | | | | | of the things we do with Expand / Direct. NFC for now, but this will be used by swiftcall expansion. llvm-svn: 263192
* [X86] Pass __m64 types via SSE registers for GCC compatibilityDavid Majnemer2016-03-041-6/+22
| | | | | | | | | | For compatibility with GCC, classify __m64 as SSE. However, clang is a platform compiler for certain targets; retain our old behavior on those targets: classify __m64 as integer. This fixes PR26832. llvm-svn: 262688
* Default vaarg lowering should support indirect struct types.James Y Knight2016-02-241-12/+68
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fixes PR11517 for SPARC. On most targets, clang lowers va_arg itself, eschewing the use of the llvm vaarg instruction. This is necessary (at least for now) as the type argument to the vaarg instruction cannot represent all the ABI information that is needed to support complex calling conventions. However, on targets with a simpler varrags ABIs, the LLVM instruction can work just fine, and clang can simply lower to it. Unfortunately, even on such targets, vaarg with a struct argument would fail, because the default lowering to vaarg was naive: it didn't take into account the ABI attribute computed by classifyArgumentType. In particular, for the DefaultABIInfo, structs are supposed to be passed indirectly and so llvm's vaarg instruction should be emitted with a pointer argument. Now, vaarg instruction emission is able to use computed ABIArgInfo for the provided argument type, which allows the default ABI support to work for structs too. I haven't touched the EmitVAArg implementation for PPC32_SVR4 or XCore, although I believe both are now redundant, and could be switched over to use the default implementation as well. Differential Revision: http://reviews.llvm.org/D16154 llvm-svn: 261717
* [WebAssembly] Lower va_arg in clang.Dan Gohman2016-02-221-0/+11
| | | | | | | This uses the general emitVoidPtrVAArg lowering logic for everything, since this supports all types, and we don't have any special requirements. llvm-svn: 261557
* Add support for Android Vector calling convention for AArch64Nirav Dave2016-02-221-5/+7
| | | | | | | | | | | | | | | | | | | | | | | This modification applies the following Android commit when we have an Android environment. This is the sole non-renderscript in the Android repo commit 9212d4fb30a3ca2f4ee966dd2748c35573d9682c Author: Tim Murray <timmurray@google.com> Date: Fri Aug 15 16:00:15 2014 -0700 Update vector calling convention for AArch64. bug 16846318 Change-Id: I3cfd167758b4bd634d8480ee6ba6bb55d61f82a7 Reviewers: srhines, jyknight Subscribers: mcrosier, aemerson, rengolin, tberghammer, danalbert, srhines Differential Revision: http://reviews.llvm.org/D17448 llvm-svn: 261533
* Fix handling of vaargs on PPC32 when going from regsave to overflow.Roman Divacky2016-02-201-1/+4
| | | | | | | | | | | | It can happen that when we only have 1 more register left in the regsave area we need to store a value bigger than 1 register and therefore we go to the overflow area. In this case we have to leave the last slot in the regsave area unused and keep using overflow area. Do this by storing a limit value to the used register counter in the overflow block. Issue diagnosed by and solution tested by Mark Millard! llvm-svn: 261422
* [MCU] Fix assertion failure on function returning empty union.Denis Zobnin2016-02-111-1/+5
| | | | | | | | Treat empty struct/union in return type as void for MCU ABI. PR26438. Differential Revision: http://reviews.llvm.org/D16808 llvm-svn: 260510
* Add an ARC autoreleased-return-value caller marker on i386.John McCall2016-02-051-0/+5
| | | | | | rdar://24531556 llvm-svn: 259932
* CodeGen: correct Windows ARM C++ assertionSaleem Abdulrasool2016-02-051-15/+0
| | | | | | | | | | | Because the Decl is explicitly passed as nullptr further up the call chain, it is possible to invoke isa on a nullptr, which will assert. Guard against the nullptr. Take the opportunity to reuse the helper method rather than re-implementing this logic. llvm-svn: 259874
* Annotate dump() methods with LLVM_DUMP_METHOD, addressing Richard Smith ↵Yaron Keren2016-01-291-1/+1
| | | | | | r259192 post commit comment. llvm-svn: 259232
* ARMv7k: select ABI based on v7k Arch rather than watchos OS.Tim Northover2016-01-271-1/+1
| | | | | | | | Various bits we'd like to use the new ABI actually compile with "-arch armv7k -miphoneos-version-min=9.0". Not ideal, but also not ridiculous given how slices work. llvm-svn: 258976
* [X86] Support 'interrupt' attribute for x86Alexey Bataev2016-01-151-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This attribute may be attached to a function definition and instructs the backend to generate appropriate function entry/exit code so that it can be used directly as an interrupt handler. The IRET instruction, instead of the RET instruction, is used to return from interrupt or exception handlers. All registers, except for the EFLAGS register which is restored by the IRET instruction, are preserved by the compiler. Any interruptible-without-stack-switch code must be compiled with -mno-red-zone since interrupt handlers can and will, because of the hardware design, touch the red zone. interrupt handler must be declared with a mandatory pointer argument: struct interrupt_frame; __attribute__ ((interrupt)) void f (struct interrupt_frame *frame) { ... } and user must properly define the structure the pointer pointing to. exception handler: The exception handler is very similar to the interrupt handler with a different mandatory function signature: #ifdef __x86_64__ typedef unsigned long long int uword_t; #else typedef unsigned int uword_t; #endif struct interrupt_frame; __attribute__ ((interrupt)) void f (struct interrupt_frame *frame, uword_t error_code) { ... } and compiler pops the error code off stack before the IRET instruction. The exception handler should only be used for exceptions which push an error code and all other exceptions must use the interrupt handler. The system will crash if the wrong handler is used. Differential Revision: http://reviews.llvm.org/D15709 llvm-svn: 257867
* Update for LLVM function name change.Rui Ueyama2016-01-141-18/+18
| | | | llvm-svn: 257802
* [X86] Better support for the MCU psABI (clang part)Michael Kuperstein2015-12-281-30/+65
| | | | | | | | | | | | | | | | This adds support for the MCU psABI in a way different from r251223 and r251224, basically reverting most of these two patches. The problem with the approach taken in r251223/4 is that it only handled libcalls that originated from the backend. However, the mid-end also inserts quite a few libcalls and assumes these use the platform's default calling convention. The previous patch tried to insert inregs when necessary both in the FE and, somewhat hackily, in the CG. Instead, we now define a new default calling convention for the MCU, which doesn't use inreg marking at all, similarly to what x86-64 does. Differential Revision: http://reviews.llvm.org/D15055 llvm-svn: 256495
* [Power PC] add soft float support for ppc32Petar Jovanovic2015-12-141-9/+15
| | | | | | | | | | | | This patch enables soft float support for ppc32 architecture and fixes the ABI for variadic functions. This is the first in a set of patches for soft float support in LLVM. Patch by Strahinja Petrovic. Differential Revision: http://reviews.llvm.org/D13351 llvm-svn: 255515
* LLDB JIT needs android vector passing rules.Stephen Hines2015-12-041-9/+26
| | | | | | | | | | | | | | | | Summary: Looking into some recent issues with LLDBs expression parser highlighted that upstream clang passes vectors types differently to Android Open Source Project's clang for Arm Android targets. This patch reflects the changes present in the AOSP and allows LLDB's JIT expression evaluation to work correctly for Arm Android targets when passing vectors. This is submitted with consent of the original author Stephen Hines. Reviewers: asl, rsmith, ADodds, rnk Subscribers: rnk, aemerson, tberghammer, danalbert, srhines, cfe-commits, pirama Differential Revision: http://reviews.llvm.org/D14639 llvm-svn: 254682
* [PowerPC] Fix calculating address of arguments on stack for variadic funcPetar Jovanovic2015-12-041-28/+34
| | | | | | | | | | | Fix calculating address of arguments larger than 32 bit on stack for variadic functions (rounding up address to alignment) on ppc32 architecture. Patch by Strahinja Petrovic. Differential Revision: http://reviews.llvm.org/D14871 llvm-svn: 254670
* Fixed default label in fully covered switch warning that was introduced in ↵Daniel Sanders2015-11-271-1/+0
| | | | | | r254203. llvm-svn: 254208
* [mips] Interrupt attribute support.Daniel Sanders2015-11-271-0/+21
| | | | | | | | | | | | | | Summary: This patch adds support for the interrupt attribute for mips32r2+. Patch by Simon Dardis. Reviewers: dsanders, aaron.ballman Subscribers: aaron.ballman, cfe-commits Differential Revision: http://reviews.llvm.org/D10802 llvm-svn: 254205
* Revert r254203: [mips] Interrupt attribute support.Daniel Sanders2015-11-271-21/+0
| | | | | | I forgot to credit the author. llvm-svn: 254204
* [mips] Interrupt attribute support.Daniel Sanders2015-11-271-0/+21
| | | | | | | | | | | | Summary: This patch adds support for the interrupt attribute for mips32r2+. Reviewers: dsanders, aaron.ballman Subscribers: aaron.ballman, cfe-commits Differential Revision: http://reviews.llvm.org/D10802 llvm-svn: 254203
* Remove some legacy mingw-w64 gcc struct infoMartell Malone2015-11-031-4/+0
| | | | | | | | As of gcc 4.7 mingw-w64 no longer emits 128-bit structs as i128 Differential Revision: http://reviews.llvm.org/D14179 llvm-svn: 251930
* Fix va_arg on watchOS.Tim Northover2015-11-021-0/+4
| | | | | | As in other contexts, alignments can go up to 16 bytes in a va_list. llvm-svn: 251821
* ARMv7k: implement ABI changes for watchOS from standard iOS.Tim Northover2015-10-301-8/+63
| | | | llvm-svn: 251710
* Fix the calling convention of Mingw64 long double valuesReid Kleckner2015-10-281-11/+22
| | | | | | | | | | GCC uses the x87DoubleExtended model for long doubles, and passes them indirectly by address through function calls. Also replace the existing mingw-long-double assembly emitting test with an IR-level test. llvm-svn: 251567
* Access the right triple field for IAMCU.Michael Kuperstein2015-10-271-2/+2
| | | | llvm-svn: 251396
* [X86] Mark inregs correctly for MCU psABIMichael Kuperstein2015-10-251-5/+18
| | | | | | | | | The MCU psABI calling convention is somewhat, but not quite, like -mregparm 3. In particular, the rules involving structs are different. Differential Revision: http://reviews.llvm.org/D13978 llvm-svn: 251224
* Roll-back r250822.Angel Garcia Gomez2015-10-201-1/+1
| | | | | | | | | | Summary: It breaks the build for the ASTMatchers Subscribers: klimek, cfe-commits Differential Revision: http://reviews.llvm.org/D13893 llvm-svn: 250827
* Apply modernize-use-default to clang.Angel Garcia Gomez2015-10-201-1/+1
| | | | | | | | | | | | Summary: Replace empty bodies of default constructors and destructors with '= default'. Reviewers: bkramer, klimek Subscribers: klimek, alexfh, cfe-commits Differential Revision: http://reviews.llvm.org/D13890 llvm-svn: 250822
* Fix 'will be initialized after' warning.Manuel Klimek2015-10-191-2/+2
| | | | llvm-svn: 250691
* [X86] Enable soft float ABI for x86Michael Kuperstein2015-10-191-11/+16
| | | | | | | | | The Intel MCU psABI requires floating-point values to be passed in-reg. This makes the x86-32 ABI code respect "-mfloat-abi soft" and generate float inreg arguments. Differential Revision: http://reviews.llvm.org/D13554 llvm-svn: 250689
* Use saner variable names. NFC.Michael Kuperstein2015-10-191-15/+23
| | | | llvm-svn: 250687
* Make a bunch of static arrays const.Craig Topper2015-10-181-1/+1
| | | | llvm-svn: 250647
* [CodeGen] [CodeGen] Attach function attributes to functions created inAkira Hatanaka2015-10-081-8/+8
| | | | | | | | | | | | | | | | | | CGBlocks.cpp. This commit fixes a bug in clang's code-gen where it creates the following functions but doesn't attach function attributes to them: __copy_helper_block_ __destroy_helper_block_ __Block_byref_object_copy_ __Block_byref_object_dispose_ rdar://problem/20828324 Differential Revision: http://reviews.llvm.org/D13525 llvm-svn: 249735
* Support __builtin_ms_va_list.Charles Davis2015-09-171-0/+15
| | | | | | | | | | | | | | | | | | Summary: This change adds support for `__builtin_ms_va_list`, a GCC extension for variadic `ms_abi` functions. The existing `__builtin_va_list` support is inadequate for this because `va_list` is defined differently in the Win64 ABI vs. the System V/AMD64 ABI. Depends on D1622. Reviewers: rsmith, rnk, rjmccall CC: cfe-commits Differential Revision: http://reviews.llvm.org/D1623 llvm-svn: 247941
* [WebAssembly] Simplify code by avoiding duplicating the default behavior.Dan Gohman2015-09-141-1/+0
| | | | llvm-svn: 247623
* Compute and preserve alignment more faithfully in IR-generation.John McCall2015-09-081-732/+796
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Introduce an Address type to bundle a pointer value with an alignment. Introduce APIs on CGBuilderTy to work with Address values. Change core APIs on CGF/CGM to traffic in Address where appropriate. Require alignments to be non-zero. Update a ton of code to compute and propagate alignment information. As part of this, I've promoted CGBuiltin's EmitPointerWithAlignment helper function to CGF and made use of it in a number of places in the expression emitter. The end result is that we should now be significantly more correct when performing operations on objects that are locally known to be under-aligned. Since alignment is not reliably tracked in the type system, there are inherent limits to this, but at least we are no longer confused by standard operations like derived-to-base conversions and array-to-pointer decay. I've also fixed a large number of bugs where we were applying the complete-object alignment to a pointer instead of the non-virtual alignment, although most of these were hidden by the very conservative approach we took with member alignment. Also, because IRGen now reliably asserts on zero alignments, we should no longer be subject to an absurd but frustrating recurring bug where an incomplete type would report a zero alignment and then we'd naively do a alignmentAtOffset on it and emit code using an alignment equal to the largest power-of-two factor of the offset. We should also now be emitting much more aggressive alignment attributes in the presence of over-alignment. In particular, field access now uses alignmentAtOffset instead of min. Several times in this patch, I had to change the existing code-generation pattern in order to more effectively use the Address APIs. For the most part, this seems to be a strict improvement, like doing pointer arithmetic with GEPs instead of ptrtoint. That said, I've tried very hard to not change semantics, but it is likely that I've failed in a few places, for which I apologize. ABIArgInfo now always carries the assumed alignment of indirect and indirect byval arguments. In order to cut down on what was already a dauntingly large patch, I changed the code to never set align attributes in the IR on non-byval indirect arguments. That is, we still generate code which assumes that indirect arguments have the given alignment, but we don't express this information to the backend except where it's semantically required (i.e. on byvals). This is likely a minor regression for those targets that did provide this information, but it'll be trivial to add it back in a later patch. I partially punted on applying this work to CGBuiltin. Please do not add more uses of the CreateDefaultAligned{Load,Store} APIs; they will be going away eventually. llvm-svn: 246985
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