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* [CodeGen][ARM] ARM runtime helper functions are not always soft-fpPeter Smith2017-07-271-10/+7
| | | | | | | Re-commit r309257 with less precise register checks in arm-float-helpers.c test. llvm-svn: 309263
* [CodeGen][ARM] Revert r309257Peter Smith2017-07-271-7/+10
| | | | | | | The test arm-float-helpers.c appears to be failing on some builders and needs some work to make it more robust. llvm-svn: 309259
* [CodeGen][ARM] ARM runtime helper functions are not always soft-fpPeter Smith2017-07-271-10/+7
| | | | | | | | | | | | | | | | | | | The ARM Runtime ABI document (IHI0043) defines the AEABI floating point helper functions in 4.1.2 The floating-point helper functions. These functions always use the base PCS (soft-fp). However helper functions defined outside of this document such as the complex-number multiply and divide helpers are not covered by this requirement and should use hard-float PCS if the target is hard-float as both compiler-rt and libgcc for a hard-float sysroot implement these functions with a hard-float PCS. All of the floating point helper functions that are explicitly soft float are expanded in the llvm ARM backend. This change makes clang not force the BuiltinCC to AAPCS for AAPCS_VFP. With this change the ARM compiler-rt tests involving _Complex pass with both hard-fp and soft-fp targets. Differential Revision: https://reviews.llvm.org/D35538 llvm-svn: 309257
* Remove Bitrig: Clang ChangesErich Keane2017-07-211-1/+0
| | | | | | | | Bitrig code has been merged back to OpenBSD, thus the OS has been abandoned. Differential Revision: https://reviews.llvm.org/D35708 llvm-svn: 308797
* Complex Long Double classification In RegCall calling conventionErich Keane2017-07-211-13/+28
| | | | | | | | | | | | | This change is part of the RegCall calling convention support for LLVM. Existing RegCall implementation was extended to include correct handling of Complex Long Double type. Complex long double types should be returned/passed in memory and not register stack. This patch implements this behavior. Patch by: eandrews Differential Revision: https://reviews.llvm.org/D35259 llvm-svn: 308769
* [CodeGen][mips] Support `long_call/far/near` attributesSimon Atanasyan2017-07-201-37/+81
| | | | | | | | | | | This patch adds support for the `long_call`, `far`, and `near` attributes for MIPS targets. The `long_call` and `far` attributes are synonyms. All these attributes override `-mlong-calls` / `-mno-long-calls` command line options for particular function. Differential revision: https://reviews.llvm.org/D35479 llvm-svn: 308667
* [AArch64] Produce correct defaultlib directives for windows in MSVC styleMartin Storsjo2017-07-201-1/+18
| | | | | | Differential Revision: https://reviews.llvm.org/D35546 llvm-svn: 308584
* [AArch64] Produce the right kind of va_arg for windowsMartin Storsjo2017-07-131-3/+18
| | | | | | | | On windows on arm64, the va_list is a plain pointer. Differential Revision: https://reviews.llvm.org/D35008 llvm-svn: 307933
* Fix build failure with gcc about mixing enum and non-enumYaxun Liu2017-07-081-1/+2
| | | | llvm-svn: 307483
* CodeGen: Fix address space of global variableYaxun Liu2017-07-081-0/+46
| | | | | | | | | | | | | Certain targets (e.g. amdgcn) require global variable to stay in global or constant address space. In C or C++ global variables are emitted in the default (generic) address space. This patch introduces virtual functions TargetCodeGenInfo::getGlobalVarAddressSpace and TargetInfo::getConstantAddressSpace to handle this in a general approach. It only affects IR generated for amdgcn target. Differential Revision: https://reviews.llvm.org/D33842 llvm-svn: 307470
* Correct VectorCall x86 (32 bit) behavior for SSE Register AssignmentErich Keane2017-06-211-72/+56
| | | | | | | | | | | | | | | | | | | In running some internal vectorcall tests in 32 bit mode, we discovered that the behavior I'd previously implemented for x64 (and applied to x32) regarding the assignment of SSE registers was incorrect. See spec here: https://msdn.microsoft.com/en-us/library/dn375768.aspx My previous implementation applied register argument position from the x64 version to both. This isn't correct for x86, so this removes and refactors that section. Additionally, it corrects the integer/int-pointer assignments. Unlike x64, x86 permits integers to be assigned independent of position. Finally, the code for 32 bit was cleaned up a little to clarify the intent, as well as given a descriptive comment. Differential Revision: https://reviews.llvm.org/D34455 llvm-svn: 305928
* [OpenCL] Fix OpenCL and SPIR version metadata generation.Alexey Bader2017-06-201-41/+0
| | | | | | | | | | | | | | Summary: OpenCL and SPIR version metadata must be generated once per module instead of once per mangled global value. Reviewers: Anastasia, yaxunl Reviewed By: Anastasia Subscribers: ahatanak, cfe-commits Differential Revision: https://reviews.llvm.org/D34235 llvm-svn: 305796
* [OpenCL] Makes kernels use the SPIR_KERNEL CC by default.Pekka Jaaskelainen2017-06-011-1/+21
| | | | | | | | | | | | | | | | Rationale: OpenCL kernels are called via an explicit runtime API with arguments set with clSetKernelArg(), not as normal sub-functions. Return SPIR_KERNEL by default as the kernel calling convention to ensure the fingerprint is fixed such way that each OpenCL argument gets one matching argument in the produced kernel function argument list to enable feasible implementation of clSetKernelArg() with aggregates etc. In case we would use the default C calling conv here, clSetKernelArg() might break depending on the target-specific conventions; different targets might split structs passed as values to multiple function arguments etc. https://reviews.llvm.org/D33639 llvm-svn: 304389
* CodeGen: Define Swift's legal vector types for AArch64, ARMArnold Schwaighofer2017-05-261-0/+30
| | | | | | rdar://32401301 llvm-svn: 304017
* [mips] Support `micromips` attributeSimon Atanasyan2017-05-221-0/+5
| | | | | | | | | This patch adds support for the `micromips` and `nomicromips` attributes for MIPS targets. Differential revision: https://reviews.llvm.org/D33363 llvm-svn: 303546
* CodeGen: Cast alloca to expected address spaceYaxun Liu2017-05-181-4/+8
| | | | | | | | | | | Alloca always returns a pointer in alloca address space, which may be different from the type defined by the language. For example, in C++ the auto variables are in the default address space. Therefore cast alloca to the expected address space when necessary. Differential Revision: https://reviews.llvm.org/D32248 llvm-svn: 303370
* [Hexagon] Make sure to pass empty struct arguments with nontrivial ctorsKrzysztof Parzyszek2017-05-121-3/+3
| | | | | | | | Thanks to Richard Smith for the suggested fix. This fixes llvm.org/PR33009 llvm-svn: 302895
* Reland: [mips] Impose a threshold for coercion of aggregatesPetar Jovanovic2017-05-101-0/+8
| | | | | | | | | | | | | | Modified MipsABIInfo::classifyArgumentType so that it now coerces aggregate structures only if the size of said aggregate is less than 16/64 bytes, depending on the ABI. Patch by Stefan Maksimovic. Differential Revision: https://reviews.llvm.org/D32900 with minor changes (use regexp instead of the hardcoded values) to the test. llvm-svn: 302670
* Suppress all uses of LLVM_END_WITH_NULL. NFC.Serge Guelton2017-05-091-6/+4
| | | | | | | | | | Use variadic templates instead of relying on <cstdarg> + sentinel. This enforces better type checking and makes code more readable. Differential revision: https://reviews.llvm.org/D32550 llvm-svn: 302572
* Revert r302547 ([mips] Impose a threshold for coercion of aggregates)Petar Jovanovic2017-05-091-8/+0
| | | | | | | | | | Reverting Modified MipsABIInfo::classifyArgumentType so that it now coerces aggregate structures only if the size of said aggregate is less than 16/64 bytes, depending on the ABI. as it broke clang-with-lto-ubuntu builder. llvm-svn: 302555
* [mips] Impose a threshold for coercion of aggregatesPetar Jovanovic2017-05-091-0/+8
| | | | | | | | | | | | Modified MipsABIInfo::classifyArgumentType so that it now coerces aggregate structures only if the size of said aggregate is less than 16/64 bytes, depending on the ABI. Patch by Stefan Maksimovic. Differential Revision: https://reviews.llvm.org/D32900 llvm-svn: 302547
* AArch64: fix weird edge case in ABI.Tim Northover2017-05-051-4/+9
| | | | | | | | | | | | | | | | | It turns out there are some sort-of-but-not-quite empty structs that break all the rules. For example: struct SuperEmpty { int arr[0]; }; struct SortOfEmpty { struct SuperEmpty e; }; Both of these have sizeof == 0, even in C++ mode, for GCC compatibility. The first one also doesn't occupy a register when passed by value in GNU C++ mode, unlike everything else. On Darwin, we want to ignore the lot (and especially don't want to try to use an i0 as we were). llvm-svn: 302313
* Re-land r301697 "[IR] Make add/remove Attributes use AttrBuilder instead of ↵Reid Kleckner2017-05-021-8/+2
| | | | | | | | | | AttributeList" This time, I fixed, built, and tested clang. This reverts r301712. llvm-svn: 301981
* [AMDGPU] Translate reqd_work_group_size into amdgpu_flat_work_group_sizeStanislav Mekhanoshin2017-04-061-3/+8
| | | | | | | | | | | | | These two attributes specify the same info in a different way. AMGPU BE only checks the latter as a target specific attribute as opposed to language specific reqd_work_group_size. This change produces amdgpu_flat_work_group_size out of reqd_work_group_size if specified. Differential Revision: https://reviews.llvm.org/D31728 llvm-svn: 299678
* [TargetInfo] Use llvm::alignOf() instead of rewriting it. NFCI.Davide Italiano2017-04-031-2/+2
| | | | llvm-svn: 299364
* Update Clang for LLVM rename AttributeSet -> AttributeListReid Kleckner2017-03-211-8/+8
| | | | llvm-svn: 298394
* CodeGen: use # as the comment leader for ARC markerSaleem Abdulrasool2017-02-111-1/+1
| | | | | | | | | | Use # as the comment leader for AArch64 auto-release elision marker. This is to keep it in sync with the value used in swift. When building libdispatch for Linux AArch64, the auto-release elision marker was emitted. However, ELF uses # as the comment leader while MachO accepts both ; and #. Use the common marker for it instead. llvm-svn: 294877
* [AVR] Add support for the 'interrupt' and 'naked' attributesDylan McKay2017-02-081-0/+28
| | | | | | | | | | | | | | | | Summary: This teaches clang how to parse and lower the 'interrupt' and 'naked' attributes. This allows interrupt signal handlers to be written. Reviewers: aaron.ballman Subscribers: malcolm.parsons, cfe-commits Differential Revision: https://reviews.llvm.org/D28451 llvm-svn: 294402
* Use less byval on 32-bit Windows x86 for classes with basesReid Kleckner2017-01-131-22/+38
| | | | | | | | | | | | This comes up in V8, which has a Handle template class that wraps a typed pointer, and is frequently passed by value. The pointer is stored in the base, HandleBase. This change allows us to pass the struct as a pointer instead of using byval. This avoids creating tons of temporary allocas that we copy from during call lowering. Eventually, it would be good to use FCAs here instead. llvm-svn: 291917
* Correct Vectorcall Register passing and HVA BehaviorErich Keane2017-01-051-26/+180
| | | | | | | | | | | | | Front end component (back end changes are D27392). The vectorcall calling convention was broken subtly in two cases. First, it didn't properly handle homogeneous vector aggregates (HVAs). Second, the vectorcall specification requires that only the first 6 parameters be eligible for register assignment. This patch fixes both issues. Differential Revision: https://reviews.llvm.org/D27529 llvm-svn: 291041
* Re-commit r289252 and r289285, and fix PR31374Yaxun Liu2016-12-151-1/+35
| | | | llvm-svn: 289787
* Revert 289252 (and follow-up 289285), it caused PR31374Nico Weber2016-12-141-35/+1
| | | | llvm-svn: 289713
* Replace APFloatBase static fltSemantics data members with getter functionsStephan Bergmann2016-12-141-7/+7
| | | | | | | | | | | | | At least the plugin used by the LibreOffice build (<https://wiki.documentfoundation.org/Development/Clang_plugins>) indirectly uses those members (through inline functions in LLVM/Clang include files in turn using them), but they are not exported by utils/extract_symbols.py on Windows, and accessing data across DLL/EXE boundaries on Windows is generally problematic. Differential Revision: https://reviews.llvm.org/D26671 llvm-svn: 289647
* Add support for non-zero null pointer for C and OpenCLYaxun Liu2016-12-091-1/+35
| | | | | | | | | | | | | | | | | | In amdgcn target, null pointers in global, constant, and generic address space take value 0 but null pointers in private and local address space take value -1. Currently LLVM assumes all null pointers take value 0, which results in incorrectly translated IR. To workaround this issue, instead of emit null pointers in local and private address space, a null pointer in generic address space is emitted and casted to local and private address space. Tentative definition of global variables with non-zero initializer will have weak linkage instead of common linkage since common linkage requires zero initializer and does not have explicit section to hold the non-zero value. Virtual member functions getNullPointer and performAddrSpaceCast are added to TargetCodeGenInfo which by default returns ConstantPointerNull and emitting addrspacecast instruction. A virtual member function getNullPointerValue is added to TargetInfo which by default returns 0. Each target can override these virtual functions to get target specific null pointer and the null pointer value for specific address space, and perform specific translations for addrspacecast. Wrapper functions getNullPointer is added to CodegenModule and getTargetNullPointerValue is added to ASTContext to facilitate getting the target specific null pointers and their values. This change has no effect on other targets except amdgcn target. Other targets can provide support of non-zero null pointer in a similar way. This change only provides support for non-zero null pointer for C and OpenCL. Supporting for other languages will be added later incrementally. Differential Revision: https://reviews.llvm.org/D26196 llvm-svn: 289252
* [OpenCL] Fix SPIR version generation.Alexey Bader2016-12-071-2/+4
| | | | | | | | | | | | Patch by Egor Churaev (echuraev). Reviewers: Anastasia Subscribers: bader, yaxunl, cfe-commits Differential Revision: https://reviews.llvm.org/D27300 llvm-svn: 288890
* swiftcc: Add an api to query whether a target ABI stores swifterror in a ↵Arnold Schwaighofer2016-12-011-0/+21
| | | | | | register llvm-svn: 288394
* IRGen: Remove all uses of CreateDefaultAlignedLoad.Peter Collingbourne2016-11-281-5/+7
| | | | | | Differential Revision: https://reviews.llvm.org/D27157 llvm-svn: 288083
* Add a little endian variant of TCE.Pekka Jaaskelainen2016-11-161-0/+1
| | | | llvm-svn: 287112
* regcall: Implement regcall Calling Conv in clangErich Keane2016-11-021-26/+125
| | | | | | | | | | This patch implements the register call calling convention, which ensures as many values as possible are passed in registers. CodeGen changes were committed in https://reviews.llvm.org/rL284108. Differential Revision: https://reviews.llvm.org/D25204 llvm-svn: 285849
* Fix Clang-tidy readability-redundant-string-cstr warningsMalcolm Parsons2016-11-021-2/+2
| | | | | | | | | | Reviewers: aaron.ballman, mehdi_amini, dblaikie Subscribers: cfe-commits Differential Revision: https://reviews.llvm.org/D26206 llvm-svn: 285799
* Declare WinX86_64ABIInfo to satisfy SwiftABI infoArnold Schwaighofer2016-10-121-2/+8
| | | | | | | | | This is minimal support that allows swift's test cases on non windows platforms to pass. rdar://28738985 llvm-svn: 284032
* [PowerPC] Enable soft-float for PPC64, and +soft-float -> -hard-floatHal Finkel2016-10-021-7/+19
| | | | | | | | | | Enable soft-float support on PPC64, as the backend now supports it. Also, the backend now uses -hard-float instead of +soft-float, so set the target features accordingly. Fixes PR26970. llvm-svn: 283061
* [AMDGPU] Expose flat work group size, register and wave control attributesKonstantin Zhuravlyov2016-09-261-11/+41
| | | | | | | | | __attribute__((amdgpu_flat_work_group_size(<min>, <max>))) - request minimum and maximum flat work group size __attribute__((amdgpu_waves_per_eu(<min>[, <max>]))) - request minimum and/or maximum waves per execution unit Differential Revision: https://reviews.llvm.org/D24513 llvm-svn: 282371
* CodeGen: simplify the logic a slight bitSaleem Abdulrasool2016-09-141-4/+0
| | | | | | | | | Move the definition of `getTriple()` into the header. It would just call `getTarget().getTriple()`. Inline the definition to allow the compiler to see the same amount of the layout as previously. Remove the more verbose `getTarget().getTriple()` in favour of `getTriple()`. llvm-svn: 281487
* Fix whitespace issuesMatt Arsenault2016-09-071-2/+1
| | | | | | ^M and extra space llvm-svn: 280786
* [PowerPC] Update the DWARF register-size tableHal Finkel2016-08-301-3/+9
| | | | | | | | | The PPC64 DWARF register-size table did not match the ABI specification (or GCC, for that matter). Fix that, and add a regression test. Fixes PR27931. llvm-svn: 280053
* [MS] Win64 va_arg should expect large arguments to be passed indirectlyReid Kleckner2016-08-251-1/+11
| | | | | | Fixes PR20569 llvm-svn: 279774
* AMDGPU: Handle structs directly in AMDGPUABIInfoMatt Arsenault2016-08-221-1/+41
| | | | | | | | | | | | | | | | Structs are currently handled as pointer + byval, which makes AMDGPU LLVM backend generate incorrect code when structs are used. This patch changes struct argument to be handled directly and without flattening, which Clover (Mesa 3D Gallium OpenCL state tracker) will be able to handle. Flattening would expand the struct to individual elements and pass each as a separate argument, which Clover can not handle. Furthermore, such expansion does not fit the OpenCL programming model which requires to explicitely specify each argument index, size and memory location. Patch by Vedran Miletić llvm-svn: 279463
* [CodeGen] Ignore unnamed bitfields before handling vector fieldsDavid Majnemer2016-08-151-4/+5
| | | | | | | | | | | | We processed unnamed bitfields after our logic for non-vector field elements in records larger than 128 bits. The vector logic would determine that the bit-field disqualifies the record from occupying a register despite the unnamed bit-field not participating in the record size nor its alignment. N.B. This behavior matches GCC and ICC. llvm-svn: 278656
* [CodeGen] Correctly implement the AVX512 psABI rulesDavid Majnemer2016-08-151-7/+10
| | | | | | | | | | | | | | An __m512 vector type wrapped in a structure should be passed in a vector register. Our prior implementation was based on a draft version of the psABI. This fixes PR28975. N.B. The update to the ABI was made here: https://github.com/hjl-tools/x86-psABI/commit/30f9c9 llvm-svn: 278655
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