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* Revert "[Attr] Add support for the `ms_hook_prologue` attribute."Charles Davis2016-08-081-8/+0
| | | | | | | This reverts commit r278050. It depends on r278048, which will be reverted. llvm-svn: 278052
* [Attr] Add support for the `ms_hook_prologue` attribute.Charles Davis2016-08-081-0/+8
| | | | | | | | | | | | | | | | | | | | | | | Summary: Based on a patch by Michael Mueller. This attribute specifies that a function can be hooked or patched. This mechanism was originally devised by Microsoft for hotpatching their binaries (which they're constantly updating to stay ahead of crackers, script kiddies, and other ne'er-do-wells on the Internet), but it's now commonly abused by Windows programs that want to hook API functions. It is for this reason that this attribute was added to GCC--hence the name, `ms_hook_prologue`. Depends on D19908. Reviewers: rnk, aaron.ballman Subscribers: cfe-commits Differential Revision: https://reviews.llvm.org/D19909 llvm-svn: 278050
* [OpenCL] Fix size of image typeYaxun Liu2016-08-031-9/+0
| | | | | | | | | | The size of image type is reported incorrectly as size of a pointer to address space 0, which causes error when casting image type to pointers by __builtin_astype. The fix is to get image address space from TargetInfo then report the size accordingly. Differential Revision: https://reviews.llvm.org/D22927 llvm-svn: 277647
* Adjust coercion of aggregates on RenderScriptPirama Arumuga Nainar2016-07-271-0/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: In RenderScript, the size of the argument or return value emitted in the IR is expected to be the same as the size of corresponding qualified type. For ARM and AArch64, the coercion performed by Clang can change the parameter or return value to a type whose size is different (usually larger) than the original aggregate type. Specifically, this can happen in the following cases: - Aggregate parameters of size <= 64 bytes and return values smaller than 4 bytes on ARM - Aggregate parameters and return values smaller than bytes on AArch64 This patch coerces the cases above to an integer array that is the same size and alignment as the original aggregate. A new field is added to TargetInfo to detect a RenderScript target and limit this coercion just to that case. Tests added to test/CodeGen/renderscript.c Reviewers: rsmith Subscribers: aemerson, srhines, llvm-commits Differential Revision: https://reviews.llvm.org/D22822 llvm-svn: 276904
* [OpenCL] AMDGCN target will generate images in constant address spaceYaxun Liu2016-07-201-0/+10
| | | | | | | | | | | | | Allows AMDGCN target to generate images (such as %opencl.image2d_t) in constant address space. Images will still be generated in global address space by default. Added tests to existing opencl-types.cl in test\CodeGenOpenCL. Patch by Aaron En Ye Shi. Differential Revision: https://reviews.llvm.org/D22523 llvm-svn: 276161
* [OpenCL] Fixes bug of missing OCL version metadata on the AMDGCN targetYaxun Liu2016-07-191-1/+12
| | | | | | | | | | | | Added the opencl.ocl.version metadata to be emitted with amdgcn. Created a static function emitOCLVerMD which is shared between triple spir and target amdgcn. Also added new testcases to existing test file, spir_version.cl inside test/CodeGenOpenCL. Patch by Aaron En Ye Shi. Differential Revision: https://reviews.llvm.org/D22424 llvm-svn: 276010
* Use arrays or initializer lists to feed ArrayRefs instead of SmallVector ↵Benjamin Kramer2016-07-021-3/+2
| | | | | | | | where possible. No functionality change intended llvm-svn: 274432
* AMDGPU: Set amdgpu_kernel calling convention for OpenCL kernels.Nikolay Haustov2016-06-301-0/+13
| | | | | | | | | | | | | | | | | | Summary: Summary: Change Clang calling convention SpirKernel to OpenCLKernel. Set calling convention OpenCLKernel for amdgcn as well. Add virtual method .getOpenCLKernelCallingConv() to TargetCodeGenInfo and use it to set target calling convention for AMDGPU and SPIR. Update tests. Reviewers: rsmith, tstellarAMD, Anastasia, yaxunl Subscribers: kzhuravl, cfe-commits Differential Revision: http://reviews.llvm.org/D21367 llvm-svn: 274220
* Add support for musl-libc on ARM Linux.Rafael Espindola2016-06-241-0/+4
| | | | | | Patch by Lei Zhang! llvm-svn: 273735
* This patch fixes problem with passing structures and unionsStrahinja Petrovic2016-06-241-1/+2
| | | | | | | | smaller than register as argument in variadic functions on big endian architectures. Differential Revision: http://reviews.llvm.org/D21611 llvm-svn: 273665
* CodeGen: support linker options on Windows ARMSaleem Abdulrasool2016-06-231-0/+10
| | | | | | | | We would incorrectly emit the directive sections due to the missing overridden methods. We now emit the expected "/DEFAULTLIB" rather than "-l" options for requested linkage llvm-svn: 273558
* [Sparc] Complex return value ABI compliance.Chris Dewhurst2016-06-081-0/+45
| | | | | | | | | | | | According to the Sparc V8 ABI, complex numbers should be passed and returned as pairs of registers: https://docs.oracle.com/cd/E26502_01/html/E28387/gentextid-2734.html This fix ensures this is the case. Without this, complex numbers are returned as a struct of two floats, which breaks the ABI rules. Differential Review: http://reviews.llvm.org/D20955 llvm-svn: 272149
* Use new triple API to check comdat /NFCXinliang David Li2016-05-251-1/+1
| | | | llvm-svn: 270728
* Fix some typos.Richard Smith2016-05-141-7/+7
| | | | llvm-svn: 269528
* [CodeGen] Clang does not choose aapcs-vfp calling convention for ARM bare ↵Oleg Ranevskyy2016-05-131-1/+2
| | | | | | | | | | | | | | | | | | | metal target with hard float (EABIHF) Summary: Clang does not detect `aapcs-vfp` for the EABIHF environment. The reason is that only GNUEABIHF is considered while choosing calling convention, EABIHF is ignored. This causes clang to use `aapcs` for EABIHF and add the `arm_aapcscc` specifier to functions in generated IR. The modified `arm-cc.c` test checks that no calling convention specifier is added to functions for EABIHF, which means the default one is used (`CallingConv::ARM_AAPCS_VFP`). Reviewers: rengolin, compnerd, t.p.northover Subscribers: aemerson, rengolin, asl, cfe-commits Differential Revision: http://reviews.llvm.org/D20219 llvm-svn: 269419
* Revert "AMDGPU/SI: Use amdgpu_kernel calling convention for OpenCL kernels."Nikolay Haustov2016-05-061-8/+0
| | | | | | | | This reverts commit f7053ec90d0fc56f0837e43c2c759e85b56c21a1. It broke calling OpenCL kernel from another kernel. llvm-svn: 268740
* AMDGPU/SI: Use amdgpu_kernel calling convention for OpenCL kernels.Nikolay Haustov2016-05-061-0/+8
| | | | | | | | | | Reviewers: tstellarAMD, arsenm Subscribers: cfe-commits Differential Revision: http://reviews.llvm.org/D19918 llvm-svn: 268718
* AArch64: fixup comment after changeTim Northover2016-05-031-1/+1
| | | | llvm-svn: 268423
* AArch64: simplify illegal vector check. NFC.Tim Northover2016-05-031-1/+1
| | | | | | | | Use a utility function to check whether the number of elements is a power of 2 and drop the redundant upper limit (a 128-bit vector with more than 16 elements would have each element < 8 bits, not possible). llvm-svn: 268422
* Expand aggregate arguments more often on 32-bit WindowsReid Kleckner2016-05-021-83/+89
| | | | | | | | | | | | | | | | | | | | Before this change, we would pass all non-HFA record arguments on Windows with byval. Byval often blocks optimizations and results in bad code generation. Windows now uses the existing workaround that other x86_32 platforms use. I also expanded the workaround to handle C++ records with constructors on Windows. On non-Windows platforms, we have to keep generating the same LLVM IR prototypes if we want our bitcode to be ABI compatible. Otherwise we will encounter mismatch issues like PR21573. Essentially fixes PR27522 in Clang instead of LLVM. Reviewers: hans Differential Revision: http://reviews.llvm.org/D19756 llvm-svn: 268261
* [SystemZ] Support Swift calling conventionBryan Chan2016-04-281-2/+8
| | | | | | | | | | | | | | | Summary: Port rL265324 to SystemZ to allow using the 'swiftcall' attribute on that architecture. Depends on D19414. Reviewers: kbarton, rjmccall, uweigand Subscribers: cfe-commits Differential Revision: http://reviews.llvm.org/D19432 llvm-svn: 267879
* [SPIR] Remove an assert mandating SPIR for OpenCL sources only.Anastasia Stulova2016-04-261-1/+0
| | | | | | | | | SPIR target can be used for C/C++ inputs too (i.e. in OpenCL compatible mode for the libs creation). Patch by Neil Henning! Review: http://reviews.llvm.org/D19478 llvm-svn: 267561
* trying to fix the windows build broken by r267496Kostya Serebryany2016-04-261-1/+1
| | | | llvm-svn: 267513
* [lanai] Update handling of structs in arguments to be passed in registers.Jacques Pienaar2016-04-261-7/+59
| | | | | | Previously aggregate types were passed byval, change the ABI to pass these in registers instead. llvm-svn: 267496
* [CodeGen] Widen non-power-of-2 vector HFA base types.Ahmed Bougacha2016-04-191-1/+12
| | | | | | | | | | | | | | | | | | | | | | | Currently, for the ppc64--gnu and aarch64 ABIs, we recognize: typedef __attribute__((__ext_vector_type__(3))) float v3f32; typedef __attribute__((__ext_vector_type__(16))) char v16i8; struct HFA { v3f32 a; v16i8 b; }; as an HFA. Since the first type encountered is used as the base type, we pass the HFA as: [2 x <3 x float>] Which leads to incorrect IR (relying on padding values) when the second field is used. Instead, explicitly widen the vector (after size rounding) in isHomogeneousAggregate. Differential Revision: http://reviews.llvm.org/D18998 llvm-svn: 266784
* [CodeGen] Fix whitespace. NFC.Ahmed Bougacha2016-04-191-1/+1
| | | | llvm-svn: 266783
* [CodeGen] Avoid ctor/dtor boilerplate with some C++11Reid Kleckner2016-04-131-62/+61
| | | | | | | | | | | | | | Non-owning pointers that cache LLVM types and constants can use 'nullptr' default member initializers so that we don't need to mention them in the constructor initializer list. Owning pointers should use std::unique_ptr so that we don't need to manually delete them in the destructor. They also don't need to be mentioned in the constructor at that point. NFC llvm-svn: 266263
* revert SVN r265702, r265640Saleem Abdulrasool2016-04-081-3/+2
| | | | | | | | | | | Revert the two changes to thread CodeGenOptions into the TargetInfo allocation and to fix the layering violation by moving CodeGenOptions into Basic. Code Generation is arguably not particularly "basic". This addresses Richard's post-commit review comments. This change purely does the mechanical revert and will be followed up with an alternate approach to thread the desired information into TargetInfo. llvm-svn: 265806
* Basic: move CodeGenOptions from FrontendSaleem Abdulrasool2016-04-071-2/+3
| | | | | | | | This is a mechanical move of CodeGenOptions from libFrontend to libBasic. This fixes the layering violation introduced earlier by threading CodeGenOptions into TargetInfo. It should also fix the modules based self-hosting builds. NFC. llvm-svn: 265702
* Move class into an anonymous namespace. NFC.Benjamin Kramer2016-04-071-0/+2
| | | | llvm-svn: 265654
* IRGen-level lowering for the Swift calling convention.John McCall2016-04-041-8/+79
| | | | llvm-svn: 265324
* [lanai] Add Lanai backend to clang driver.Jacques Pienaar2016-03-281-0/+74
| | | | | | | | | | Changes to clang to add Lanai backend. Adds a new target, ABI and toolchain. General Lanai backend discussion on llvm-dev thread "[RFC] Lanai backend" (http://lists.llvm.org/pipermail/llvm-dev/2016-February/095118.html). Differential Revision: http://reviews.llvm.org/D17002 llvm-svn: 264655
* [OpenCL] Add ocl and spir version for spir targetXiuli Pan2016-03-241-0/+44
| | | | | | | | | | | | Summary: Add opencl.spir.version and opencl.ocl.version metadata for CodeGen to identify OpenCL version. Reviewers: yaxunl, Anastasia Subscribers: cfe-commits, pekka.jaaskelainen Differential Revision: http://reviews.llvm.org/D17596 llvm-svn: 264241
* Add -fnative-half-arguments-and-returnsPirama Arumuga Nainar2016-03-181-2/+2
| | | | | | | | | | | | | | | | | | Summary: r246764 handled __fp16 arguments and returns for AAPCS, but skipped this handling for OpenCL. Simlar to OpenCL, RenderScript also handles __fp16 type natively. This patch adds the -fnative-half-arguments-and-returns command line flag to allow such languages to skip this coercion of __fp16. Reviewers: srhines, olista01 Subscribers: cfe-commits Differential Revision: http://reviews.llvm.org/D18138 llvm-svn: 263795
* Add a coerce-and-expand ABIArgInfo as a generalization of someJohn McCall2016-03-111-0/+7
| | | | | | | | of the things we do with Expand / Direct. NFC for now, but this will be used by swiftcall expansion. llvm-svn: 263192
* [X86] Pass __m64 types via SSE registers for GCC compatibilityDavid Majnemer2016-03-041-6/+22
| | | | | | | | | | For compatibility with GCC, classify __m64 as SSE. However, clang is a platform compiler for certain targets; retain our old behavior on those targets: classify __m64 as integer. This fixes PR26832. llvm-svn: 262688
* Default vaarg lowering should support indirect struct types.James Y Knight2016-02-241-12/+68
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fixes PR11517 for SPARC. On most targets, clang lowers va_arg itself, eschewing the use of the llvm vaarg instruction. This is necessary (at least for now) as the type argument to the vaarg instruction cannot represent all the ABI information that is needed to support complex calling conventions. However, on targets with a simpler varrags ABIs, the LLVM instruction can work just fine, and clang can simply lower to it. Unfortunately, even on such targets, vaarg with a struct argument would fail, because the default lowering to vaarg was naive: it didn't take into account the ABI attribute computed by classifyArgumentType. In particular, for the DefaultABIInfo, structs are supposed to be passed indirectly and so llvm's vaarg instruction should be emitted with a pointer argument. Now, vaarg instruction emission is able to use computed ABIArgInfo for the provided argument type, which allows the default ABI support to work for structs too. I haven't touched the EmitVAArg implementation for PPC32_SVR4 or XCore, although I believe both are now redundant, and could be switched over to use the default implementation as well. Differential Revision: http://reviews.llvm.org/D16154 llvm-svn: 261717
* [WebAssembly] Lower va_arg in clang.Dan Gohman2016-02-221-0/+11
| | | | | | | This uses the general emitVoidPtrVAArg lowering logic for everything, since this supports all types, and we don't have any special requirements. llvm-svn: 261557
* Add support for Android Vector calling convention for AArch64Nirav Dave2016-02-221-5/+7
| | | | | | | | | | | | | | | | | | | | | | | This modification applies the following Android commit when we have an Android environment. This is the sole non-renderscript in the Android repo commit 9212d4fb30a3ca2f4ee966dd2748c35573d9682c Author: Tim Murray <timmurray@google.com> Date: Fri Aug 15 16:00:15 2014 -0700 Update vector calling convention for AArch64. bug 16846318 Change-Id: I3cfd167758b4bd634d8480ee6ba6bb55d61f82a7 Reviewers: srhines, jyknight Subscribers: mcrosier, aemerson, rengolin, tberghammer, danalbert, srhines Differential Revision: http://reviews.llvm.org/D17448 llvm-svn: 261533
* Fix handling of vaargs on PPC32 when going from regsave to overflow.Roman Divacky2016-02-201-1/+4
| | | | | | | | | | | | It can happen that when we only have 1 more register left in the regsave area we need to store a value bigger than 1 register and therefore we go to the overflow area. In this case we have to leave the last slot in the regsave area unused and keep using overflow area. Do this by storing a limit value to the used register counter in the overflow block. Issue diagnosed by and solution tested by Mark Millard! llvm-svn: 261422
* [MCU] Fix assertion failure on function returning empty union.Denis Zobnin2016-02-111-1/+5
| | | | | | | | Treat empty struct/union in return type as void for MCU ABI. PR26438. Differential Revision: http://reviews.llvm.org/D16808 llvm-svn: 260510
* Add an ARC autoreleased-return-value caller marker on i386.John McCall2016-02-051-0/+5
| | | | | | rdar://24531556 llvm-svn: 259932
* CodeGen: correct Windows ARM C++ assertionSaleem Abdulrasool2016-02-051-15/+0
| | | | | | | | | | | Because the Decl is explicitly passed as nullptr further up the call chain, it is possible to invoke isa on a nullptr, which will assert. Guard against the nullptr. Take the opportunity to reuse the helper method rather than re-implementing this logic. llvm-svn: 259874
* Annotate dump() methods with LLVM_DUMP_METHOD, addressing Richard Smith ↵Yaron Keren2016-01-291-1/+1
| | | | | | r259192 post commit comment. llvm-svn: 259232
* ARMv7k: select ABI based on v7k Arch rather than watchos OS.Tim Northover2016-01-271-1/+1
| | | | | | | | Various bits we'd like to use the new ABI actually compile with "-arch armv7k -miphoneos-version-min=9.0". Not ideal, but also not ridiculous given how slices work. llvm-svn: 258976
* [X86] Support 'interrupt' attribute for x86Alexey Bataev2016-01-151-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This attribute may be attached to a function definition and instructs the backend to generate appropriate function entry/exit code so that it can be used directly as an interrupt handler. The IRET instruction, instead of the RET instruction, is used to return from interrupt or exception handlers. All registers, except for the EFLAGS register which is restored by the IRET instruction, are preserved by the compiler. Any interruptible-without-stack-switch code must be compiled with -mno-red-zone since interrupt handlers can and will, because of the hardware design, touch the red zone. interrupt handler must be declared with a mandatory pointer argument: struct interrupt_frame; __attribute__ ((interrupt)) void f (struct interrupt_frame *frame) { ... } and user must properly define the structure the pointer pointing to. exception handler: The exception handler is very similar to the interrupt handler with a different mandatory function signature: #ifdef __x86_64__ typedef unsigned long long int uword_t; #else typedef unsigned int uword_t; #endif struct interrupt_frame; __attribute__ ((interrupt)) void f (struct interrupt_frame *frame, uword_t error_code) { ... } and compiler pops the error code off stack before the IRET instruction. The exception handler should only be used for exceptions which push an error code and all other exceptions must use the interrupt handler. The system will crash if the wrong handler is used. Differential Revision: http://reviews.llvm.org/D15709 llvm-svn: 257867
* Update for LLVM function name change.Rui Ueyama2016-01-141-18/+18
| | | | llvm-svn: 257802
* [X86] Better support for the MCU psABI (clang part)Michael Kuperstein2015-12-281-30/+65
| | | | | | | | | | | | | | | | This adds support for the MCU psABI in a way different from r251223 and r251224, basically reverting most of these two patches. The problem with the approach taken in r251223/4 is that it only handled libcalls that originated from the backend. However, the mid-end also inserts quite a few libcalls and assumes these use the platform's default calling convention. The previous patch tried to insert inregs when necessary both in the FE and, somewhat hackily, in the CG. Instead, we now define a new default calling convention for the MCU, which doesn't use inreg marking at all, similarly to what x86-64 does. Differential Revision: http://reviews.llvm.org/D15055 llvm-svn: 256495
* [Power PC] add soft float support for ppc32Petar Jovanovic2015-12-141-9/+15
| | | | | | | | | | | | This patch enables soft float support for ppc32 architecture and fixes the ABI for variadic functions. This is the first in a set of patches for soft float support in LLVM. Patch by Strahinja Petrovic. Differential Revision: http://reviews.llvm.org/D13351 llvm-svn: 255515
* LLDB JIT needs android vector passing rules.Stephen Hines2015-12-041-9/+26
| | | | | | | | | | | | | | | | Summary: Looking into some recent issues with LLDBs expression parser highlighted that upstream clang passes vectors types differently to Android Open Source Project's clang for Arm Android targets. This patch reflects the changes present in the AOSP and allows LLDB's JIT expression evaluation to work correctly for Arm Android targets when passing vectors. This is submitted with consent of the original author Stephen Hines. Reviewers: asl, rsmith, ADodds, rnk Subscribers: rnk, aemerson, tberghammer, danalbert, srhines, cfe-commits, pirama Differential Revision: http://reviews.llvm.org/D14639 llvm-svn: 254682
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