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* Implement AArch64 Neon instruction set Bitwise Extract.Jiangning Liu2013-11-061-0/+4
| | | | llvm-svn: 194119
* Implement AArch64 Neon Crypto instruction classes AES, SHA, and 3 SHA.Jiangning Liu2013-11-051-30/+71
| | | | llvm-svn: 194086
* Implemented aarch64 neon intrinsic vcopy_lane with float type.Kevin Qin2013-11-051-2/+4
| | | | llvm-svn: 194042
* [AArch64] Add support for NEON scalar fixed-point convert to floating-point ↵Chad Rosier2013-10-311-0/+14
| | | | | | instructions. llvm-svn: 193817
* [AArch64] Add support for NEON scalar shift immediate instructions.Chad Rosier2013-10-311-2/+105
| | | | llvm-svn: 193791
* Add CodeGenABITypes.h for use in LLDB.Mark Lacey2013-10-301-0/+1
| | | | | | | | | | | | | | | | | | CodeGenABITypes is a wrapper built on top of CodeGenModule that exposes some of the functionality of CodeGenTypes (held by CodeGenModule), specifically methods that determine the LLVM types appropriate for function argument and return values. I addition to CodeGenABITypes.h, CGFunctionInfo.h is introduced, and the definitions of ABIArgInfo, RequiredArgs, and CGFunctionInfo are moved into this new header from the private headers ABIInfo.h and CGCall.h. Exposing this functionality is one part of making it possible for LLDB to determine the actual ABI locations of function arguments and return values, making it possible for it to determine this for any supported target without hard-coding ABI knowledge in the LLDB code. llvm-svn: 193717
* [AArch64] Add support for NEON scalar floating-point compare instructions.Chad Rosier2013-10-301-15/+109
| | | | llvm-svn: 193692
* Implement function type checker for the undefined behavior sanitizer.Peter Collingbourne2013-10-201-1/+1
| | | | | | | | | This uses function prefix data to store function type information at the function pointer. Differential Revision: http://llvm-reviews.chandlerc.com/D1338 llvm-svn: 193058
* [AArch64] Add support for NEON scalar extract narrow instructions.Chad Rosier2013-10-181-2/+23
| | | | llvm-svn: 192971
* [AArch64] Add support for NEON scalar three register different instructionChad Rosier2013-10-171-2/+24
| | | | | | | | class. The instruction class includes the signed saturating doubling multiply-add long, signed saturating doubling multiply-subtract long, and the signed saturating doubling multiply long instructions. llvm-svn: 192909
* [AArch64] Add support for NEON scalar negate instruction.Chad Rosier2013-10-161-0/+4
| | | | llvm-svn: 192845
* [AArch64] Add support for NEON scalar absolute value instruction.Chad Rosier2013-10-161-0/+4
| | | | llvm-svn: 192844
* Update comment.Chad Rosier2013-10-161-1/+1
| | | | llvm-svn: 192807
* [AArch64] Add support for NEON scalar signed saturating accumulated of unsignedChad Rosier2013-10-161-0/+14
| | | | | | value and unsigned saturating accumulate of signed value instructions. llvm-svn: 192801
* [AArch64] Add support for NEON scalar signed saturating absolute value andChad Rosier2013-10-151-0/+14
| | | | | | scalar signed saturating negate instructions. llvm-svn: 192734
* [AArch64] Add support for NEON scalar integer compare instructions.Chad Rosier2013-10-141-5/+74
| | | | llvm-svn: 192597
* Implemented aarch64 SIMD copy related ACLE intrinsic :Kevin Qin2013-10-111-0/+28
| | | | | | vget_lane, vset_lane, vcopy_lane, vcreate, vdup_n, vdup_lane, vmov_n. llvm-svn: 192411
* Implement AArch64 vector load/store multiple N-element structure class ↵Hao Liu2013-10-101-0/+34
| | | | | | | | | | | | SIMD(lselem). Including following 14 instructions: 4 ld1 insts: load multiple 1-element structure to sequential 1/2/3/4 registers. ld2/ld3/ld4: load multiple N-element structure to sequential N registers (N=2,3,4). 4 st1 insts: store multiple 1-element structure from sequential 1/2/3/4 registers. st2/st3/st4: store multiple N-element structure from sequential N registers (N = 2,3,4). llvm-svn: 192362
* Revert "Implement AArch64 vector load/store multiple N-element structure ↵Tim Northover2013-10-101-34/+0
| | | | | | | | | class SIMD(lselem). " This reverts commit r192351. The LLVM side broke the build and the Clang tests will inevitably fail without it. llvm-svn: 192356
* Implement AArch64 vector load/store multiple N-element structure class ↵Hao Liu2013-10-101-0/+34
| | | | | | | | | | | | | | | SIMD(lselem). Including following 14 instructions: 4 ld1 insts: load multiple 1-element structure to sequential 1/2/3/4 registers. ld2/ld3/ld4: load multiple N-element structure to sequential N registers (N=2,3,4). 4 st1 insts: store multiple 1-element structure from sequential 1/2/3/4 registers. st2/st3/st4: store multiple N-element structure from sequential N registers (N = 2,3,4). E.g. ld1(3 registers version) will load 32-bit elements {A, B, C, D, E, F} sequentially into the three 64-bit vectors list {BA, DC, FE}. E.g. ld3 will load 32-bit elements {A, B, C, D, E, F} into the three 64-bit vectors list {DA, EB, FC}. llvm-svn: 192351
* [AArch64] Add support for NEON scalar floating-point reciprocal estimate,Chad Rosier2013-10-081-0/+15
| | | | | | reciprocal exponent, and reciprocal square root estimate instructions. llvm-svn: 192243
* [AArch64] Add support for NEON scalar signed/unsigned integer to floating-pointChad Rosier2013-10-081-0/+14
| | | | | | convert instructions. llvm-svn: 192232
* Fix objectsize tests after r192117Matt Arsenault2013-10-071-2/+3
| | | | llvm-svn: 192120
* [AArch64] Add support for NEON scalar arithmetic instructions:Chad Rosier2013-10-071-0/+25
| | | | | | SQDMULH, SQRDMULH, FMULX, FRECPS, and FRSQRTS. llvm-svn: 192112
* Implement aarch64 neon instruction set AdvSIMD (Across).Jiangning Liu2013-10-051-111/+147
| | | | llvm-svn: 192029
* Do not emit undefined lsrh/ashr for NEON shiftsAmaury de la Vieuville2013-10-041-12/+35
| | | | | | | | These IR instructions are undefined when the amount is equal to operand size, but NEON right shifts support such shifts. Work around that by emitting a different IR in these cases. llvm-svn: 191953
* Implement aarch64 neon instruction set AdvSIMD (3V elem).Jiangning Liu2013-10-041-0/+40
| | | | llvm-svn: 191945
* [ARM] Add a builtin to allow you to use the 'sevl' instruction.Joey Gouly2013-10-021-0/+5
| | | | llvm-svn: 191816
* Mark an impossible path as unreachable to pacify GCC.Benjamin Kramer2013-09-261-0/+1
| | | | llvm-svn: 191436
* Remove tabs.Benjamin Kramer2013-09-261-91/+91
| | | | llvm-svn: 191427
* CGBuiltin.cpp: Prune a stray default: label. [-Wcovered-switch-default]NAKAMURA Takumi2013-09-241-2/+0
| | | | llvm-svn: 191277
* Initial support for Neon scalar instructions.Jiangning Liu2013-09-241-8/+228
| | | | | | | | | | Patch by Ana Pazos. 1.Added support for v1ix and v1fx types. 2.Added Scalar Pairwise Reduce instructions. 3.Added initial implementation of Scalar Arithmetic instructions. llvm-svn: 191264
* Add _mm_stream_si64 intrinsic.Eli Friedman2013-09-231-2/+12
| | | | | | | | | While I'm here, also fix the alignment computation for the whole family of intrinsics. PR17298. llvm-svn: 191243
* [ARMv8] Add builtins for CRC instructions.Joey Gouly2013-09-181-0/+43
| | | | | | Patch by Bradley Smith! llvm-svn: 190931
* Restore the sqrt -> llvm.sqrt mapping in fast-math modeHal Finkel2013-09-121-6/+13
| | | | | | | | | | | | | | | This restores the sqrt -> llvm.sqrt mapping, but only in fast-math mode (specifically, when the UnsafeFPMath or NoNaNsFPMath CodeGen options are enabled). The @llvm.sqrt* intrinsics have slightly different semantics from the libm call, specifically, they are undefined when given a non-zero negative number (the libm calls will always return NaN for any negative number). This mapping was removed in r100613, and replaced with a TODO, but at that time the fast-math flags were not yet implemented. Now that we have these, restoring this mapping is important because it will enable autovectorization of sqrt calls in loops (at least in fast-math mode). llvm-svn: 190646
* Implement aarch64 neon instruction set AdvSIMD (3V Diff), covering the ↵Jiangning Liu2013-09-091-0/+16
| | | | | | | | following 26 instructions, SADDL, UADDL, SADDW, UADDW, SSUBL, USUBL, SSUBW, USUBW, ADDHN, RADDHN, SABAL, UABAL, SUBHN, RSUBHN, SABDL, UABDL, SMLAL, UMLAL, SMLSL, UMLSL, SQDMLAL, SQDMLSL, SMULL, UMULL, SQDMULL, PMULL llvm-svn: 190289
* Inplement aarch64 neon instructions in AdvSIMD(shift). About 24 shift ↵Hao Liu2013-09-041-37/+110
| | | | | | | | | | instructions: sshr,ushr,ssra,usra,srshr,urshr,srsra,ursra,sri,shl,sli,sqshlu,sqshl,uqshl,shrn,sqrshr$ and 4 convert instructions: scvtf,ucvtf,fcvtzs,fcvtzu llvm-svn: 189926
* ARM: comment on why vmull intrinsic has to exist for now.Tim Northover2013-08-281-0/+5
| | | | llvm-svn: 189464
* ARM: Emit normal IR for vaddhn/vsubhn NEON intrinsicsTim Northover2013-08-281-6/+36
| | | | | | | | | | | | | These operations "vector add high-half narrow" actually correspond to the sequence: %sum = add <4 x i32> %lhs, %rhs %high = lshr <4 x i32> %sum, <i32 16, i32 16, i32 16, i32 16> %res = trunc <4 x i32> %high to <4 x i16> Now that LLVM can spot this, Clang should emit the corresponding LLVM IR. llvm-svn: 189463
* ARM: use vqdmull and vqadds/vqsubs to implement vqdmlal/vqdmlslTim Northover2013-08-281-6/+22
| | | | | | | | | | | The NEON intrinsics vqdmlal and vqdmlsl are really just combinations of a saturating-doubling-multiply (vqdmull) and a saturating add/sub, so now that LLVM can spot those patterns Clang should emit them instead of specialised intrinsics. Feature already tested by existing ARM NEON intrinsics tests. llvm-svn: 189462
* Fix last commit.Juergen Ributzka2013-08-191-1/+1
| | | | llvm-svn: 188724
* Simplify code by using CreateMemTemp. No functional change intended.Juergen Ributzka2013-08-191-18/+9
| | | | | Reviewer: Eli llvm-svn: 188722
* Fix the name and the type of the argument for intriniscJuergen Ributzka2013-08-171-0/+10
| | | | | | | | _mm256_broadcastsi128_si256 to align with the Intel documentation. This fixes bug PR 16581 and rdar:14747994. llvm-svn: 188609
* Fix the build failure of Realease versionHao Liu2013-08-151-1/+1
| | | | llvm-svn: 188456
* Clang and AArch64 backend patches to support shll/shl and vmovl instructions ↵Hao Liu2013-08-151-0/+43
| | | | | | and ACLE functions llvm-svn: 188452
* AArch64: initial NEON supportTim Northover2013-08-011-1/+196
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Patch by Ana Pazos - Completed implementation of instruction formats: AdvSIMD three same AdvSIMD modified immediate AdvSIMD scalar pairwise - Completed implementation of instruction classes (some of the instructions in these classes belong to yet unfinished instruction formats): Vector Arithmetic Vector Immediate Vector Pairwise Arithmetic - Initial implementation of instruction formats: AdvSIMD scalar two-reg misc AdvSIMD scalar three same - Intial implementation of instruction class: Scalar Arithmetic - Initial clang changes to support arm v8 intrinsics. Note: no clang changes for scalar intrinsics function name mangling yet. - Comprehensive test cases for added instructions To verify auto codegen, encoding, decoding, diagnosis, intrinsics. llvm-svn: 187568
* [PowerPC] Support powerpc64le as a syntax-checking target.Bill Schmidt2013-07-261-0/+1
| | | | | | | | | | | | | | | | | | | This patch provides basic support for powerpc64le as an LLVM target. However, use of this target will not actually generate little-endian code. Instead, use of the target will cause the correct little-endian built-in defines to be generated, so that code that tests for __LITTLE_ENDIAN__, for example, will be correctly parsed for syntax-only testing. Code generation will otherwise be the same as powerpc64 (big-endian), for now. The patch leaves open the possibility of creating a little-endian PowerPC64 back end, but there is no immediate intent to create such a thing. The new test case variant ensures that correct built-in defines for little-endian code are generated. llvm-svn: 187180
* Partial revert of r185568.Eli Bendersky2013-07-241-11/+8
| | | | | | | | r186899 and r187061 added a preferred way for some architectures not to get intrinsic generation for math builtins. So the code changes in r185568 can now be undone (the test remains). llvm-svn: 187079
* ARM: implement low-level intrinsics for the atomic exclusive operations.Tim Northover2013-07-161-6/+58
| | | | | | | | | | | | This adds three overloaded intrinsics to Clang: T __builtin_arm_ldrex(const volatile T *addr) int __builtin_arm_strex(T val, volatile T *addr) void __builtin_arm_clrex() The intent is that these do what users would expect when given most sensible types. Currently, "sensible" translates to ints, floats and pointers. llvm-svn: 186394
* Add a __builtin_addressof that performs the same functionality as the built-inRichard Smith2013-07-111-0/+2
| | | | | | | | | | | & operator (ignoring any overloaded operator& for the type). The purpose of this builtin is for use in std::addressof, to allow it to be made constexpr; the existing implementation technique (reinterpret_cast to some reference type, take address, reinterpert_cast back) does not permit this because reinterpret_cast between reference types is not permitted in a constant expression in C++11 onwards. llvm-svn: 186053
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