summaryrefslogtreecommitdiffstats
path: root/clang/lib/CodeGen/CGBuiltin.cpp
Commit message (Collapse)AuthorAgeFilesLines
...
* Add some MS aliases for existing intrinsicsAlbert Gutowski2016-09-141-0/+24
| | | | | | | | | | Reviewers: thakis, compnerd, majnemer, rsmith, rnk Subscribers: alexshap, cfe-commits Differential Revision: https://reviews.llvm.org/D24330 llvm-svn: 281540
* Convert finite to builtinDehao Chen2016-09-141-0/+6
| | | | | | | | | | | | Summary: This patch converts finite/__finite to builtin functions so that it will be inlined by compiler. Reviewers: hfinkel, davidxl, efriedma Subscribers: efriedma, llvm-commits Differential Revision: https://reviews.llvm.org/D24483 llvm-svn: 281509
* Temporary fix for MS _Interlocked intrinsicsAlbert Gutowski2016-09-131-10/+2
| | | | llvm-svn: 281401
* Reverse commit 281375 (breaks building Chromium)Albert Gutowski2016-09-131-24/+0
| | | | llvm-svn: 281399
* Add bunch of _Interlocked builtinsAlbert Gutowski2016-09-131-14/+38
| | | | | | | | | | Reviewers: compnerd, thakis, Prazek, majnemer, rnk Subscribers: cfe-commits Differential Revision: https://reviews.llvm.org/D24153 llvm-svn: 281378
* Add some MS aliases for existing intrinsicsAlbert Gutowski2016-09-131-0/+24
| | | | | | | | | | Reviewers: thakis, compnerd, majnemer, rsmith, rnk Subscribers: cfe-commits Differential Revision: https://reviews.llvm.org/D24330 llvm-svn: 281375
* Implement MS _rot intrinsicsAlbert Gutowski2016-09-081-0/+52
| | | | | | | | | | Reviewers: thakis, Prazek, compnerd, rnk Subscribers: majnemer, cfe-commits Differential Revision: https://reviews.llvm.org/D24311 llvm-svn: 280997
* AMDGPU: Add clang builtin for ds_swizzle.Changpeng Fang2016-08-181-0/+3
| | | | | | | | | | | Summary: int __builtin_amdgcn_ds_swizzle (int a, int imm); while imm is a constant. Differential Revision: http://reviews.llvm.org/D23682 llvm-svn: 279165
* Revert "[X86] Add xgetbv/x[X86] Add xgetbv xsetbv intrinsics to non-windows ↵Reid Kleckner2016-08-161-5/+1
| | | | | | | | platforms" This reverts commit r278783. It breaks usage of _xgetbv on Windows. llvm-svn: 278814
* [X86] Add xgetbv/x[X86] Add xgetbv xsetbv intrinsics to non-windows platformsMarina Yatsina2016-08-161-1/+5
| | | | | | | | commit on behalf of guyblank Differential Revision: https://reviews.llvm.org/D21959 llvm-svn: 278783
* [x86] Fix a really nasty bug introduced in r276417 where alignmentChandler Carruth2016-08-101-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | constraints were added to _mm256_broadcast_{pd,ps} intel intrinsics. The spec for these intrinics is ... pretty much silent on alignment. This is especially frustrating considering the amount of discussion of alignment in the load and store instrinsics. So I was forced to rely on the specification for the VBROADCASTF128 instruction. That instruction's spec is *also* completely silent on alignment. Fortunately, when it comes to the instruction's spec, silence is enough. There is no #GP fault option for an underaligned address so this instruction, and by inference the intrinsic, can read any alignment. As it happens, the old code worked exactly this way and in fact we have plenty of code that hands pointers with less than 16-byte alignment to these intrinsics. This code broke pretty spectacularly with this commit. Fortunately, the fix is super simple! Change a 16 to a 1, and ta da! Anyways, a lot of debugging for a really boring fix. =] llvm-svn: 278202
* AMDGPU : Add Clang builtin intrinsics for compare with the fullWei Ding2016-08-051-0/+8
| | | | | | | | wavefront result. Differential Revision: http://reviews.llvm.org/D22934 llvm-svn: 277824
* [OpenCL] Added underscores to the names of 'to_addr' OpenCL built-ins.Alexey Bader2016-08-041-2/+3
| | | | | | | | | | | | | | | Summary: In order to re-define OpenCL built-in functions 'to_{private,local,global}' in OpenCL run-time library LLVM names must be different from the clang built-in function names. Reviewers: yaxunl, Anastasia Subscribers: cfe-commits Differential Revision: https://reviews.llvm.org/D23120 llvm-svn: 277743
* [X86][AVX] Added support for lowering to VBROADCASTF128/VBROADCASTI128 with ↵Simon Pilgrim2016-07-221-0/+27
| | | | | | | | | | generic IR As discussed on D22460, I've updated the vbroadcastf128 pd256/ps256 builtins to map directly to generic IR - load+splat a 128-bit vector to both lanes of a 256-bit vector. Fix for PR28657. llvm-svn: 276417
* AMDGPU: Remove legacy ldexp builtinMatt Arsenault2016-07-151-8/+0
| | | | llvm-svn: 275623
* AMDGPU: Update for rsq intrinsic changesMatt Arsenault2016-07-151-14/+12
| | | | llvm-svn: 275622
* AMDGPU: Add Clang Builtin for v_lerp_u8Wei Ding2016-07-151-0/+2
| | | | | | Differential Revision: http://reviews.llvm.org/D22380 llvm-svn: 275577
* AMDGPU: Export workitem builtinsJan Vesely2016-07-101-0/+28
| | | | | | | | Reviewers: tstellardAMD Differential Revision: http://reviews.llvm.org/D20299 llvm-svn: 275030
* [CodeGen] Use llvm::Type::getVectorNumElements instead of casting to ↵Craig Topper2016-07-081-3/+2
| | | | | | llvm::VectorType and calling getNumElements. This is equivalent and shorter. llvm-svn: 274823
* [X86] Reuse existing lambda and remove unnecessary argument from vector cmp ↵Craig Topper2016-07-081-16/+11
| | | | | | builtin handling. NFC llvm-svn: 274821
* [X86] Remove a couple calls to create V2F64 and V4F32 types for builtin ↵Craig Topper2016-07-081-29/+17
| | | | | | handling. Just get the type from the operand of the builtin instead. NFC llvm-svn: 274820
* [X86] Use native IR for immediate values 0-7 of packed fp cmp builtins. This ↵Craig Topper2016-07-061-0/+45
| | | | | | makes them the same as what is done when using the SSE builtins for these same encodings. llvm-svn: 274608
* [AVX512] Use the generic ctlz intrinsic to implement the vplzcntd/q builtins.Craig Topper2016-07-061-0/+12
| | | | llvm-svn: 274603
* [OpenCL] An implementation of device side enqueue (DSE) from OpenCL v2.0 ↵Anastasia Stulova2016-07-051-0/+142
| | | | | | | | | | | | | | | | | s6.13.17. - Added new Builtins: enqueue_kernel, get_kernel_work_group_size and get_kernel_preferred_work_group_size_multiple. These Builtins use custom check to diagnose parameters of the passed Blocks i. e. variable number of 'local void*' type params, and check different overloads specified in Table 6.31 of OpenCL v2.0. - IR is generated as an internal library call for each OpenCL Builtin, reusing ObjC Block implementation. Review: http://reviews.llvm.org/D20249 llvm-svn: 274540
* [OpenCL] Make OpenCL Builtins added according to the right version.Anastasia Stulova2016-07-041-1/+1
| | | | | | | | | | Currently we only have OpenCL 2.0 Builtins i.e. pipes or address space conversions. They have to be added only in the version 2.0 compilation mode to make the identifiers available for use in the other versions. Review: http://reviews.llvm.org/D20249 llvm-svn: 274509
* [AVX512] Modify what indices we emit for the zero vector we use for zero ↵Craig Topper2016-07-041-1/+1
| | | | | | extension of the result of a v2i1 or v4i1 masked compare. This way we emit something that the backend easily interprets as a concatenation rather than a true shuffle. This delivers slightly better codegen with the current backend capabilities. llvm-svn: 274484
* Emit more intrinsics for builtin functionsMatt Arsenault2016-07-011-39/+92
| | | | | | | | | | | | This is important for building libclc. Since r273039 tests are failing due to now emitting calls to these functions instead of emitting the DAG node. The libm function names are implemented for OpenCL, and should call the locally defined versions, so -fno-builtin is used. The IR Some functions use the __builtins and expect the intrinsics to be emitted. Without this we end up with nobuiltin calls to intrinsics or to unsupported library calls. llvm-svn: 274370
* [AVX512] Zero extend cmp intrinsic return value.Igor Breger2016-06-291-2/+2
| | | | | | Differential Revision: http://reviews.llvm.org/D21746 llvm-svn: 274110
* AMDGPU: Add builtin to read exec maskMatt Arsenault2016-06-281-4/+14
| | | | llvm-svn: 273965
* [AVX512] Replace masked integer cmp and ucmp builtins with native IR.Craig Topper2016-06-221-7/+57
| | | | llvm-svn: 273378
* [X86][SSE4A] Use native IR for mask movntsd/movntss intrinsics.Simon Pilgrim2016-06-171-0/+20
| | | | | | Depends on llvm side commit r273002. llvm-svn: 273003
* [ARM] Add mrrc/mrrc2 intrinsics and update existing mcrr/mcrr2 intrinsics.Ranjeet Singh2016-06-171-0/+68
| | | | | | | | | | Reapplying patch in r272777 which was reverted because the llvm patch which added support for generating the mcrr/mcrr2 instructions from the intrinsic was causing an assertion failure. This has now been fixed in llvm. llvm-svn: 272983
* [x86] generate IR for AVX2 integer min/max builtinsSanjay Patel2016-06-161-5/+17
| | | | | | | Sibling patch to r272932: http://reviews.llvm.org/rL272932 llvm-svn: 272933
* [Builtin] Make __builtin_thread_pointer target-independent.Marcin Koscielnicki2016-06-161-0/+7
| | | | | | | | This is now supported for ARM, AArch64, PowerPC, SystemZ, SPARC, Mips. Differential Revision: http://reviews.llvm.org/D19589 llvm-svn: 272893
* [x86] translate SSE packed FP comparison builtins to IRSanjay Patel2016-06-151-124/+74
| | | | | | | | | | | | | As noted in the code comment, a potential follow-on would be to remove the builtins themselves. Other than ord/unord, this already works as expected. Eg: typedef float v4sf __attribute__((__vector_size__(16))); v4sf fcmpgt(v4sf a, v4sf b) { return a > b; } Differential Revision: http://reviews.llvm.org/D21268 llvm-svn: 272840
* [x86] generate IR for SSE integer min/max builtinsSanjay Patel2016-06-151-0/+27
| | | | | | | Sibling patch to r272806: http://reviews.llvm.org/rL272806 llvm-svn: 272807
* Reverting r272777 because one of the testsRanjeet Singh2016-06-151-68/+0
| | | | | | | added in the llvm patch is causing an assertion to fail. llvm-svn: 272790
* [AVX512] Use native IR for mask pcmpeq/pcmpgt intrinsics.Craig Topper2016-06-151-0/+49
| | | | llvm-svn: 272787
* [ARM] Add mrrc/mrrc2 intrinsics and update existing mcrr/mcrr2 intrinsics.Ranjeet Singh2016-06-151-0/+68
| | | | | | | | | | | | | | Patch adds intrinsics for mrrc/mrrc2. The intrinsics for mrrc/mrrc2 return a single uint64_t to represent two 32 bit values. The mcrr/mcrr2 intrinsic was changed to accept a single uint64_t instead of two 32 bit values as the input for consistency. Differential Revision: http://reviews.llvm.org/D21179 llvm-svn: 272777
* Fix unused variable warningSimon Pilgrim2016-06-131-51/+50
| | | | llvm-svn: 272541
* [Clang][X86] Convert non-temporal store builtins to generic ↵Simon Pilgrim2016-06-131-63/+51
| | | | | | | | | | | | | | __builtin_nontemporal_store in headers We can now use __builtin_nontemporal_store instead of target specific builtins for naturally aligned nontemporal stores which avoids the need for handling in CGBuiltin.cpp The scalar integer nontemporal (unaligned) store builtins will have to wait as __builtin_nontemporal_store currently assumes natural alignment and doesn't accept the 'packed struct' trick that we use for normal unaligned load/stores. The nontemporal loads require further backend support before we can safely convert them to __builtin_nontemporal_load Differential Revision: http://reviews.llvm.org/D21272 llvm-svn: 272540
* [CodeGen] Update to use an ArrayRef of uint32_t instead of int in calls to ↵Craig Topper2016-06-121-10/+10
| | | | | | CreateShuffleVector to match llvm interface change. llvm-svn: 272492
* [X86] Handle AVX2 pslldqi and psrldqi intrinsics shufflevector creation ↵Craig Topper2016-06-091-52/+0
| | | | | | directly in the header file instead of in CGBuiltin.cpp. Simplify the sse2 equivalents as well. llvm-svn: 272246
* [X86] Reuse the EmitX86Select routine to handle the select for masked ↵Craig Topper2016-06-091-16/+7
| | | | | | palignr too. llvm-svn: 272245
* [AVX512] Emit select instruction instead of using x86 specific instrinsics.Igor Breger2016-06-081-33/+59
| | | | | | | | This will allow us to remove the x86 instrinics from the backend. Differential Revision: http://reviews.llvm.org/D21060 llvm-svn: 272141
* [AVX512] Convert masked palignr builtins directly to native IR similar to ↵Craig Topper2016-06-061-5/+23
| | | | | | the other palignr builtins, but with a select to handle masking. llvm-svn: 271873
* [AVX512] Convert masked load builtins to generic masked load intrinsics ↵Craig Topper2016-05-311-0/+67
| | | | | | | | instead of the x86 specific ones. This will allow the x86 intrinsics to be removed from the backend. llvm-svn: 271253
* [AVX512] Emit generic masked store instrinsics instead of using x86 specific ↵Craig Topper2016-05-311-0/+68
| | | | | | | | intrinsics. This will allow us to remove the x86 instrinics from the backend. llvm-svn: 271246
* [X86] Simplify alignr builtin support by recognizing that NumLaneElts is ↵Craig Topper2016-05-291-9/+7
| | | | | | always 16. NFC llvm-svn: 271176
* [CodeGen] Use the ArrayRef form CreateShuffleVector instead of building ↵Craig Topper2016-05-291-48/+39
| | | | | | ConstantVectors or ConstantDataVectors and calling the other form. llvm-svn: 271165
OpenPOWER on IntegriCloud