summaryrefslogtreecommitdiffstats
path: root/clang/lib/CodeGen/CGBuiltin.cpp
Commit message (Collapse)AuthorAgeFilesLines
* [X86] Implement __builtin_cpu_isCraig Topper2017-08-101-0/+117
| | | | | | | | This patch adds support for __builtin_cpu_is. I've tried to match the strings supported to the latest version of gcc. Differential Revision: https://reviews.llvm.org/D35449 llvm-svn: 310657
* [X86] Support 'avx5124vnniw' and 'avx5124fmaps' for __builtin_cpu_supports.Craig Topper2017-08-081-2/+4
| | | | | | They still need to be implemented in the intrinsics, the command line, and the backend. But this change isn't dependent on any of that and resolves a TODO. llvm-svn: 310386
* [OpenCL] Add missing subgroup builtinsJoey Gouly2017-08-011-0/+19
| | | | | | | This adds get_kernel_max_sub_group_size_for_ndrange and get_kernel_sub_group_count_for_ndrange. llvm-svn: 309678
* Fix incorrect assertion condition.Victor Leschuk2017-07-291-2/+2
| | | | llvm-svn: 309484
* [ubsan] Diagnose invalid uses of builtins (clang)Vedant Kumar2017-07-291-2/+22
| | | | | | | | | | | | | | | On some targets, passing zero to the clz() or ctz() builtins has undefined behavior. I ran into this issue while debugging UB in __hash_table from libcxx: the bug I was seeing manifested itself differently under -O0 vs -Os, due to a UB call to clz() (see: libcxx/r304617). This patch introduces a check which can detect UB calls to builtins. llvm.org/PR26979 Differential Revision: https://reviews.llvm.org/D34590 llvm-svn: 309459
* [AArch64] Add support for __builtin_ms_va_list on aarch64Martin Storsjo2017-07-171-25/+27
| | | | | | | | | | | Move builtins from the x86 specific scope into the global scope. Their use is still limited to x86_64 and aarch64 though. This allows wine on aarch64 to properly handle variadic functions. Differential Revision: https://reviews.llvm.org/D34475 llvm-svn: 308218
* [SystemZ] Add support for IBM z14 processor (1/3)Ulrich Weigand2017-07-171-3/+99
| | | | | | | | | | | This patch series adds support for the IBM z14 processor. This part includes: - Basic support for the new processor and its features. - Support for low-level builtins mapped to new LLVM intrinsics. Support for the -fzvector extension to vector float and the new high-level vector intrinsics is provided by separate patches. llvm-svn: 308197
* Enhance synchscope representation (clang)Konstantin Zhuravlyov2017-07-111-14/+13
| | | | | | | | Relevant changes required for r307722. Differential Revision: https://reviews.llvm.org/D33109 llvm-svn: 307723
* [X86] Move AVX512VPOPCNTDQ in __builtin_cpu_support's enum to match trunk gcc.Craig Topper2017-07-081-0/+2
| | | | | | | | There are two other features before it that we don't currently support in the the frontend or backend so I left placeholders to keep the encoding correct. I think the compiler-rt implementation of this feature is even further out of date. llvm-svn: 307456
* This reverts r305820 (ARMv.2-A FP16 vector intrinsics) because it showsSjoerd Meijer2017-07-061-177/+6
| | | | | | | | problems in testing, see comments in D34161 for some more details. A fix is in progres in D35011, but a revert seems better now as the fix will probably take some more time to land. llvm-svn: 307277
* [WebAssembly] Add throw/rethrow builtins for exception handlingHeejin Ahn2017-06-301-0/+10
| | | | | | | | | | | | | | | | | Summary: Add new builtins for throw/rethrow instructions. This follows exception handling handling proposal in https://github.com/WebAssembly/exception-handling/blob/master/proposals/Exceptions.md Reviewers: sunfish, dschuff Reviewed By: dschuff Subscribers: jfb, dschuff, sbc100, jgravelle-google Differential Revision: https://reviews.llvm.org/D34783 llvm-svn: 306775
* [AArch64] ADD ARMv.2-A FP16 vector intrinsicsAbderrazek Zaafrani2017-06-201-6/+177
| | | | | | Differential Revision: https://reviews.llvm.org/D34161 llvm-svn: 305820
* Expand vector oparation to as IR constants, PR28129.Dinar Temirbulatov2017-06-161-0/+21
| | | | llvm-svn: 305551
* Added LLVM_FALLTHROUGH to address warning: this statement may fall through. NFC.Galina Kistanova2017-06-031-0/+3
| | | | llvm-svn: 304649
* Revert "[AArch64] Add ARMv8.2-A FP16 vefctor intrinsics"Vedant Kumar2017-06-021-177/+6
| | | | | | | | | | | | This reverts commit r304493. It breaks all the Darwin bots: http://green.lab.llvm.org/green/job/clang-stage1-cmake-RA-incremental_check/37168 Failure: Failing Tests (2): Clang :: CodeGen/aarch64-v8.2a-neon-intrinsics.c Clang :: CodeGen/arm_neon_intrinsics.c llvm-svn: 304509
* [AArch64] Add ARMv8.2-A FP16 vefctor intrinsicsAbderrazek Zaafrani2017-06-011-6/+177
| | | | llvm-svn: 304493
* [X86] Adding avx512_vpopcntdq feature set and its intrinsicsOren Ben Simhon2017-05-251-31/+39
| | | | | | | | | | AVX512_VPOPCNTDQ is a new feature set that was published by Intel. The patch represents the Clang side of the addition of six intrinsics for two new machine instructions (vpopcntd and vpopcntq). It also includes the addition of the new feature set. Differential Revision: https://reviews.llvm.org/D33170 llvm-svn: 303857
* [PowerPC] Implement vec_xxsldwi builtin.Tony Jiang2017-05-241-0/+41
| | | | | | | | | | The vec_xxsldwi builtin is missing from altivec.h. This has been requested by developers working on libvpx for VP9 support for Google. The patch fixes PR: https://bugs.llvm.org/show_bug.cgi?id=32653 Differential Revision: https://reviews.llvm.org/D33236 llvm-svn: 303766
* [PowerPC] Implement vec_xxpermdi builtin.Tony Jiang2017-05-241-0/+33
| | | | | | | | | | The vec_xxpermdi builtin is missing from altivec.h. This has been requested by developers working on libvpx for VP9 support for Google. The patch fixes PR: https://bugs.llvm.org/show_bug.cgi?id=32653 Differential Revision: https://reviews.llvm.org/D33053 llvm-svn: 303760
* [CodeGen] Propagate LValueBaseInfo instead of AlignmentSourceKrzysztof Parzyszek2017-05-181-2/+1
| | | | | | | | | | | | | The functions creating LValues propagated information about alignment source. Extend the propagated data to also include information about possible unrestricted aliasing. A new class LValueBaseInfo will contain both AlignmentSource and MayAlias info. This patch should not introduce any functional changes. Differential Revision: https://reviews.llvm.org/D33284 llvm-svn: 303358
* Suppress all uses of LLVM_END_WITH_NULL. NFC.Serge Guelton2017-05-091-4/+4
| | | | | | | | | | Use variadic templates instead of relying on <cstdarg> + sentinel. This enforces better type checking and makes code more readable. Differential revision: https://reviews.llvm.org/D32550 llvm-svn: 302572
* [XRay] Add __xray_customeevent(...) as a clang-supported builtinDean Michael Berris2017-05-091-0/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: We define the `__xray_customeevent` builtin that gets translated to IR calls to the correct intrinsic. The default implementation of this is a no-op function. The codegen side of this follows the following logic: - When `-fxray-instrument` is not provided in the driver, we elide all calls to `__xray_customevent`. - When `-fxray-instrument` is enabled and a function is marked as "never instrumented", we elide all calls to `__xray_customevent` in that function; if either marked as "always instrumented" or subject to threshold-based instrumentation, we emit a call to the `llvm.xray.customevent` intrinsic from LLVM for each `__xray_customevent` occurrence in the function. This change depends on D27503 (to land in LLVM first). Reviewers: echristo, rsmith Subscribers: mehdi_amini, pelikan, lrl, cfe-commits Differential Revision: https://reviews.llvm.org/D30018 llvm-svn: 302492
* ANSIfy more. Still no behavior change.Nico Weber2017-05-051-1/+1
| | | | llvm-svn: 302259
* ANSIfy. No behavior change.Nico Weber2017-05-051-1/+1
| | | | llvm-svn: 302258
* Implement _interlockedbittestandset as a builtinHans Wennborg2017-04-071-3/+21
| | | | | | | | | It's used by MS headers in VS 2017 without including intrin.h, so we can't implement it in the header anymore. Differential Revision: https://reviews.llvm.org/D31736 llvm-svn: 299782
* [X86][Clang] Converting __mm{|256|512}_movm_epi{8|16|32|64} LLVMIR call into ↵Michael Zuckerman2017-04-041-0/+22
| | | | | | | | | | | | generic intrinsics. This patch is a part two of two reviews, one for the clang and the other for LLVM. In this patch, I covered the clang side, by introducing the intrinsic to the front end. This is done by creating a generic replacement. Differential Revision: https://reviews.llvm.org/D31394a llvm-svn: 299431
* [X86] Implement __readgsqword (and the rest) as builtins (PR32373)Hans Wennborg2017-03-221-10/+24
| | | | | | | | | | | | | | It seems MS headers have started using __readgsqword, and since it's used in a header that doesn't include intrin.h, we can't implement it as an inline function anymore. That was already the case for __readfsdword, which Saleem added support for in r220859. This patch reuses that codegen to implement all of __read[fg]s{byte,word,dword,qword}. Differential Revision: https://reviews.llvm.org/D31248 llvm-svn: 298538
* Let llvm.objectsize be conservative with null pointersGeorge Burgess IV2017-03-211-3/+6
| | | | | | | D28494 adds another parameter to @llvm.objectsize. Clang needs to be sure to pass that third arg whenever applicable. llvm-svn: 298431
* Update Clang for LLVM rename AttributeSet -> AttributeListReid Kleckner2017-03-211-14/+14
| | | | llvm-svn: 298394
* [x86] these aren't the undefs you're looking for (PR32176)Sanjay Patel2017-03-121-1/+6
| | | | | | | | | | | | | x86 has undef SSE/AVX intrinsics that should represent a bogus register operand. This is not the same as LLVM's undef value which can take on multiple bit patterns. There are better solutions / follow-ups to this discussed here: https://bugs.llvm.org/show_bug.cgi?id=32176 ...but this should prevent miscompiles with a one-line code change. Differential Revision: https://reviews.llvm.org/D30834 llvm-svn: 297588
* [AMDGPU] Add builtin functions readlane ds_permute mov_dppYaxun Liu2017-03-101-0/+8
| | | | | | Differential Revision: https://reviews.llvm.org/D30551 llvm-svn: 297436
* [MS] Add support for __ud2 and __int2c MSVC intrinsicsReid Kleckner2017-03-061-0/+15
| | | | | | This was requested in PR31958 and elsewhere. llvm-svn: 297057
* [CodeGen] Don't reemit expressions for pass_object_size params.George Burgess IV2017-02-231-6/+13
| | | | | | | | | | | | | | This fixes an assertion failure in cases where we had expression statements that declared variables nested inside of pass_object_size args. Since we were emitting the same ExprStmt twice (once for the arg, once for the @llvm.objectsize call), we were getting issues with redefining locals. This also means that we can be more lax about when we emit @llvm.objectsize for pass_object_size args: since we're reusing the arg's value itself, we don't have to care so much about side-effects. llvm-svn: 295935
* AMDGPU: Add fmed3 half builtinMatt Arsenault2017-02-221-0/+1
| | | | llvm-svn: 295874
* Call the correct @llvm.objectsize.George Burgess IV2017-02-221-6/+7
| | | | | | | | | | | | | | | | | | The following code would crash clang: void foo(unsigned *const __attribute__((pass_object_size(0)))); void bar(unsigned *i) { foo(i); } This is because we were always selecting the version of `@llvm.objectsize` that takes an i8* in CodeGen. Passing an i32* as an i8* makes LLVM very unhappy. (Yes, I'm surprised that this remained uncaught for so long, too. :) ) As an added bonus, we'll now also use the appropriate address space when emitting @llvm.objectsize calls. llvm-svn: 295805
* [OpenCL] Correct ndrange_t implementationAnastasia Stulova2017-02-161-4/+13
| | | | | | | | | | | | | | | Removed ndrange_t as Clang builtin type and added as a struct type in the OpenCL header. Use type name to do the Sema checking in enqueue_kernel and modify IR generation accordingly. Review: D28058 Patch by Dmitry Borisenkov! llvm-svn: 295311
* [MS] Implement the __fastfail intrinsic as a builtinReid Kleckner2017-02-091-1/+38
| | | | | | | | | | __fastfail terminates the process immediately with a special system call. It does not run any process shutdown code or exception recovery logic. Fixes PR31854 llvm-svn: 294606
* AMDGPU: Add builtin for fmed3 intrinsicMatt Arsenault2017-01-311-1/+2
| | | | llvm-svn: 293600
* [OpenMP][NVPTX][CUDA] Adding support for printf for an NVPTX OpenMP device.Arpith Chacko Jacob2017-01-291-2/+2
| | | | | | | | | | | | | | | Support for CUDA printf is exploited to support printf for an NVPTX OpenMP device. To reflect the support of both programming models, the file CGCUDABuiltin.cpp has been renamed to CGGPUBuiltin.cpp, and the call EmitCUDADevicePrintfCallExpr has been renamed to EmitGPUDevicePrintfCallExpr. Reviewers: jlebar Differential Revision: https://reviews.llvm.org/D17890 llvm-svn: 293444
* [OpenCL] Add missing address spaces in IR generation of blocksAnastasia Stulova2017-01-271-20/+26
| | | | | | | | | | | | | | | | | | | | | | | | Modify ObjC blocks impl wrt address spaces as follows: - keep default private address space for blocks generated as local variables (with captures); - add global address space for global block literals (no captures); - make the block invoke function and enqueue_kernel prototype with the generic AS block pointer parameter to accommodate both private and global AS cases from above; - add block handling into default AS because it's implemented as a special pointer type (BlockPointer) in the frontend and therefore it is used as a pointer everywhere. This is also needed to accommodate both private and global AS blocks for the two cases above. - removes ObjC RT specific symbols (NSConcreteStackBlock and NSConcreteGlobalBlock) in the OpenCL mode. Review: https://reviews.llvm.org/D28814 llvm-svn: 293286
* P0426: Make the library implementation of constexpr char_traits a little easierRichard Smith2017-01-201-0/+4
| | | | | | | | | by providing a memchr builtin that returns char* instead of void*. Also add a __has_feature flag to indicate the presence of constexpr forms of the relevant <string> functions. llvm-svn: 292555
* [ARM] Use generic bitreverse intrinsic, rather than ARM specific rbit.Chad Rosier2017-01-101-3/+3
| | | | | | The backend already supports lowering this intrinsic to a rbit instruction. llvm-svn: 291582
* [AArch64] Use generic bitreverse intrinsic, rather than AArch64 specific.Chad Rosier2017-01-101-2/+2
| | | | | | Differential Revision: https://reviews.llvm.org/D28400 llvm-svn: 291574
* Add vec_insert4b and vec_extract4b functions to altivec.hSean Fertile2017-01-051-0/+84
| | | | | | | | | Add builtins for the functions and custom codegen mapping the builtins to their corresponding intrinsics and handling the endian related swapping. https://reviews.llvm.org/D26546 llvm-svn: 291179
* CodeGen: force builtins to be localSaleem Abdulrasool2016-12-151-3/+3
| | | | | | | | Unfortunately _setjmp3 can be both import or local. The ASAN tests try to emulate the flags which makes this harder to detect. Rely on the linker creating or using thunks here instead. Should repair the ASAN windows bots. llvm-svn: 289783
* Update for clang after llvm::StringLiteral.Zachary Turner2016-12-131-1/+1
| | | | llvm-svn: 289553
* [clang] Version support for UBSan handlersFilipe Cabecinhas2016-12-121-2/+2
| | | | | | | | | | | | | | | | | | | | | | This adds a way for us to version any UBSan handler by itself. The patch overrides D21289 for a better implementation (we're able to rev up a single handler). After this, then we can land a slight modification of D19667+D19668. We probably don't want to keep all the versions in compiler-rt (maybe we want to deprecate on one release and remove the old handler on the next one?), but with this patch we will loudly fail to compile when mixing incompatible handler calls, instead of silently compiling and then providing bad error messages. Reviewers: kcc, samsonov, rsmith, vsk Subscribers: cfe-commits Differential Revision: https://reviews.llvm.org/D21695 llvm-svn: 289444
* [CodeGen][ARM] Make sure the value and type used to create a bitcastAkira Hatanaka2016-12-011-10/+20
| | | | | | | | | | | have the same size. This fixes an asset that is triggered when an address of a boolean variable is passed to __builtin_arm_ldrex or __builtin_arm_strex. rdar://problem/29269006 llvm-svn: 288404
* IRGen: Remove all uses of CreateDefaultAlignedLoad.Peter Collingbourne2016-11-281-9/+22
| | | | | | Differential Revision: https://reviews.llvm.org/D27157 llvm-svn: 288083
* [AMDGPU] Change frexp.exp builtin to return i16 for f16 inputKonstantin Zhuravlyov2016-11-181-3/+12
| | | | | | Differential Revision: https://reviews.llvm.org/D26863 llvm-svn: 287390
OpenPOWER on IntegriCloud