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* AArch64: share slgihtly more NEON implementation with ARM.Tim Northover2014-02-111-14/+10
| | | | | | | | The s64/u64 vcvt conversion operations are actually pretty much identical to the s32/u32 ones in implementation, and can be shared with just one extra variable. llvm-svn: 201145
* ARM: move vshll NEON implementation to common codeTim Northover2014-02-101-13/+10
| | | | | | | Now that both ARM backends use the same implementation for vshll operations, the code can be shared. This is also a necessary LLVM/Clang interface update. llvm-svn: 201094
* ARM: implement vshrn NEON intrinsic in terms of shr/truncTim Northover2014-02-101-13/+10
| | | | | | | Now the backend supports the natural LLVM IR, we can shamelessly steal the AArch64 front-end code to implement the vshrn intrinsic on 32-bit ARM. llvm-svn: 201086
* ARM & AArch64: combine implementation of vcaXYZ intrinsicsTim Northover2014-02-041-80/+24
| | | | | | | | Now that the back-end intrinsics are more regular, there's no need for the special handling these got in the front-end, so they can be moved to EmitCommonNeonBuiltinExpr. llvm-svn: 200769
* ARM: implement support for crypto intrinsics in arm_neon.hTim Northover2014-02-031-33/+50
| | | | llvm-svn: 200708
* AArch64: use new non-polymorphic crypto intrinsicsTim Northover2014-02-031-14/+14
| | | | | | | The LLVM backend now has invariant types on the various crypto-intrinsics, because in all cases there's only really one interpretation. llvm-svn: 200707
* ARM & AArch64: unify the rest of the completely shared NEON implementationsTim Northover2014-01-311-22/+16
| | | | | | | | This should be the last routine patch: AArch64 does still delegate to EmitARMBuiltinExpr, but the remaining instances have complications of one sort or another so some more cunning thought will be needed. llvm-svn: 200528
* ARM & AArch64: another block of miscellaneous NEON sharing.Tim Northover2014-01-311-119/+83
| | | | llvm-svn: 200527
* ARM & AArch64: move shared vld/vst intrinsics to common implementation.Tim Northover2014-01-311-175/+145
| | | | llvm-svn: 200526
* ARM & AArch64: more instructions into common blockTim Northover2014-01-311-73/+52
| | | | llvm-svn: 200525
* ARM & AArch64: merge another NEON block completely.Tim Northover2014-01-311-236/+154
| | | | llvm-svn: 200524
* ARM & AArch64: extend shared NEON implementation to first block.Tim Northover2014-01-301-86/+72
| | | | | | | This extends the refactoring to the whole of the first block of trivial correspondences (as a fairly arbitrary boundary). llvm-svn: 200472
* ARM & AArch64: fully share NEON implementation of permutation intrinsicsTim Northover2014-01-301-71/+80
| | | | | | | As a starting point, this moves the CodeGen for NEON permutation instructions (vtrn, vzip, vuzp) into a new shared function. llvm-svn: 200471
* ARM & AArch64: share the BI__builtin_neon enum defs.Tim Northover2014-01-301-1102/+1102
| | | | llvm-svn: 200470
* [AArch64 NEON] Fix a bug about vcles_f32 and vcled_f64.Kevin Qin2014-01-231-0/+1
| | | | | | | As vcles_f32() and vcled_f64 are implemented by FCMGE, operands should make a swap. llvm-svn: 199866
* [AArch64]The compare to zero intrinsics should be implemented by 'icmp/fcmp' ↵Hao Liu2013-12-231-1/+1
| | | | | | and 'sext' not 'zext'. Modify the implementation by replacing zext with sext. llvm-svn: 197898
* [AArch64] Refactor NEON floating-point Max/Min/Maxnm/Minnm across vector AArch64Chad Rosier2013-12-111-4/+4
| | | | | | intrinsics to use f32 types, rather than their vector equivalents. llvm-svn: 197091
* [AArch64] Add NEON scalar floating-point compare LLVM AArch64 intrinsics thatChad Rosier2013-12-111-31/+31
| | | | | | use f32/f64 types, rather than their vector equivalents. llvm-svn: 197071
* [AArch64] Refactor the NEON scalar floating-point reciprocal step andChad Rosier2013-12-111-5/+5
| | | | | | | floating-point reciprocal square root step LLVM AArch64 intrinsics to use f32/f64 types, rather than their vector equivalents. llvm-svn: 197070
* [AArch64] Refactor the NEON scalar floating-point reciprocal estimate, floating-Chad Rosier2013-12-111-5/+5
| | | | | | | | point reciprocal exponent, and floating-point reciprocal square root estimate LLVM AArch64 intrinsics to use f32/f64 types, rather than their vector equivalents. llvm-svn: 197069
* [AArch64] Refactor the NEON floating-point absolute difference LLVM AArch64Chad Rosier2013-12-101-1/+1
| | | | | | intrinsic to use f32/f64 types, rather than their vector equivalents. llvm-svn: 196969
* [AArch64] Refactor the NEON signed/unsigned floating-point convert to ↵Chad Rosier2013-12-101-11/+15
| | | | | | | | fixed-point LLVM AArch64 intrinsics to use f32/f64, rather than their vector equivalents. llvm-svn: 196968
* [AArch64] Overload NEON signed/unsigned floating-point convert to fixed-pointChad Rosier2013-12-101-16/+8
| | | | | | and fixed-point convert to floating-point LLVM AArch64 intrinsics. llvm-svn: 196967
* [AArch64] Overload NEON signed/unsigned integer convert to floating-pointChad Rosier2013-12-101-8/+4
| | | | | | LLVM AArch64 intrinsics. llvm-svn: 196966
* [AArch64] Refactor the redundant code in the EmitAArch64ScalarBuiltinExpr()Chad Rosier2013-12-101-206/+189
| | | | | | function. No functional change intended. llvm-svn: 196936
* [AArch64] Refactor the Neon vector/scalar floating-point convert intrinsics soChad Rosier2013-12-101-12/+11
| | | | | | that they use float/double rather than the vector equivalents when appropriate. llvm-svn: 196931
* [AArch64] Refactor the Neon vector/scalar floating-point convert implementation.Chad Rosier2013-12-101-24/+24
| | | | | | Specifically, reuse the ARM intrinsics when possible. llvm-svn: 196927
* [AArch64 NEON] Support poly128_t and implement relevant intrinsic.Kevin Qin2013-12-101-0/+30
| | | | llvm-svn: 196888
* [AArch64] Refactor the NEON scalar reduce pairwise intrinsics so that they useChad Rosier2013-12-091-6/+17
| | | | | | float/double rather than the vector equivalents when appropriate. llvm-svn: 196836
* [AArch64] Refactor the NEON scalar reduce pairwise front-end codegen to removeChad Rosier2013-12-091-11/+11
| | | | | | unnecessary patterns in tablegen. llvm-svn: 196835
* [AArch64] Remove q and non-q intrinsic definitions from the NEON scalar reduceChad Rosier2013-12-091-20/+10
| | | | | | pairwise implementation, using an overloaded definition instead. llvm-svn: 196834
* [AArch64]Add missing pair intrinsics such as:Hao Liu2013-12-091-0/+8
| | | | | | | int32_t vminv_s32(int32x2_t a) which should be compiled into SMINP Vd.2S,Vn.2S,Vm.2S llvm-svn: 196750
* [AArch64 NEON] Add ACLE intrinsic vceqz_f64.Kevin Qin2013-12-041-5/+13
| | | | llvm-svn: 196361
* [AArch64 NEON] Add missing compare intrinsics.Kevin Qin2013-12-041-3/+31
| | | | llvm-svn: 196359
* [AArch64]Add missing floating point convert, round and misc intrinsics.Hao Liu2013-12-031-7/+22
| | | | | | E.g. int64x1_t vcvt_s64_f64(float64x1_t a) -> FCVTZS Dd, Dn llvm-svn: 196211
* revert r196152. Hao Liu2013-12-031-13/+0
| | | | | | | | | | | | | | This is a duplicate implementation. E.g. this patch defines: float64_t vabd_f64(float64_t a, float64_t b) But there is already a similar intrinsic "vabdd_f64" with the same types. Also, this intrinsic will be conflicted to the vector type intrinsic as following(Which is implemented by me and will be committed to trunk): float64x1_t vabd_f64(float64x1_t a, float64x1_t b). Two functions shouldn't have a same name in arm_neon.h. According to ARM ACLE document, such vabd_f64 with float64_t is not existing. So I revert this commit. llvm-svn: 196205
* AArch64: Add missing scalar pair intrinsics.Hao Liu2013-12-031-0/+14
| | | | | | E.g. "float32_t vaddv_f32(float32x2_t a)" to be matched into "faddp s0, v1.2s". llvm-svn: 196199
* [AArch64] Add missing NEON scalar floating-point to integer convert ACLEs.Chad Rosier2013-12-021-0/+13
| | | | llvm-svn: 196152
* Fix the problem that the range check for scalar narrow shift is too wide.Hao Liu2013-11-291-1/+0
| | | | | | E.g. the immediate value of vshrns_n_s16 is [1,16], which should be [1,8]. llvm-svn: 195942
* [AArch64] Add support for NEON scalar floating-point absolute difference.Chad Rosier2013-11-271-0/+5
| | | | llvm-svn: 195804
* [AArch64] Add support for NEON scalar floating-point to integer convertChad Rosier2013-11-261-0/+57
| | | | | | instructions. llvm-svn: 195789
* Implemented Neon scalar vdup_lane intrinsics.Ana Pazos2013-11-211-0/+25
| | | | | | Fixed scalar dup alias and added test case. llvm-svn: 195329
* Implemented Neon scalar by element intrinsics.Ana Pazos2013-11-211-6/+45
| | | | | | | Intrinsics implemented: vqdmull_lane, vqdmulh_lane, vqrdmulh_lane, vqdmlal_lane, vqdmlsl_lane scalar Neon intrinsics. llvm-svn: 195326
* Implement AArch64 neon instructions class SIMD lsone and SIMD lone-post.Hao Liu2013-11-191-0/+127
| | | | llvm-svn: 195079
* Implement the newly added AArch64 ACLE functions for ld1/st1 with 2/3/4 vectors.Hao Liu2013-11-181-0/+86
| | | | | | The functions are like: vst1_s8_x2 ... llvm-svn: 194991
* Remove unused but set variable.Benjamin Kramer2013-11-161-4/+0
| | | | llvm-svn: 194920
* Implemented aarch64 Neon scalar vmulx_lane intrinsicsAna Pazos2013-11-151-7/+80
| | | | | | | | | | | | | | Implemented aarch64 Neon scalar vfma_lane intrinsics Implemented aarch64 Neon scalar vfms_lane intrinsics Implemented legacy vmul_n_f64, vmul_lane_f64, vmul_laneq_f64 intrinsics (v1f64 parameter type) using Neon scalar instructions. Implemented legacy vfma_lane_f64, vfms_lane_f64, vfma_laneq_f64, vfms_laneq_f64 intrinsics (v1f64 parameter type) using Neon scalar instructions. llvm-svn: 194889
* [AArch64] Add support for legacy AArch32 NEON scalar shift right by immediateChad Rosier2013-11-141-0/+11
| | | | | | and accumulate instructions. llvm-svn: 194732
* [AArch64 neon] support poly64 and relevant intrinsic functions.Kevin Qin2013-11-141-0/+1
| | | | llvm-svn: 194660
* Implement aarch64 neon instruction class misc.Kevin Qin2013-11-141-0/+278
| | | | llvm-svn: 194657
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