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* [TargetInfo] Sort target features before passing them to the backendEli Friedman2018-04-251-0/+3
| | | | | | | | | | | | | | | Passing the features in random order will lead to unpredictable results when some of the features are related (like the architecture-version features on ARM). It might be possible to fix this particular case in the ARM target code, to avoid adding overlapping target features. But we should probably be sorting in any case: the behavior shouldn't depend on StringMap's hashing algorithm. Differential Revision: https://reviews.llvm.org/D46030 llvm-svn: 330861
* [CUDA] Enable CUDA compilation with CUDA-9.2Artem Belevich2018-04-241-0/+2
| | | | | | Differential Revision: https://reviews.llvm.org/D45827 llvm-svn: 330753
* [Solaris] __float128 is supported on Solaris/x86Rainer Orth2018-04-231-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When rebasing https://reviews.llvm.org/D40898 with GCC 5.4 on Solaris 11.4, I ran into a few instances of In file included from /vol/llvm/src/compiler-rt/local/test/asan/TestCases/Posix/asan-symbolize-sanity-test.cc:19: In file included from /usr/gcc/5/lib/gcc/x86_64-pc-solaris2.11/5.4.0/../../../../include/c++/5.4.0/string:40: In file included from /usr/gcc/5/lib/gcc/x86_64-pc-solaris2.11/5.4.0/../../../../include/c++/5.4.0/bits/char_traits.h:39: In file included from /usr/gcc/5/lib/gcc/x86_64-pc-solaris2.11/5.4.0/../../../../include/c++/5.4.0/bits/stl_algobase.h:64: In file included from /usr/gcc/5/lib/gcc/x86_64-pc-solaris2.11/5.4.0/../../../../include/c++/5.4.0/bits/stl_pair.h:59: In file included from /usr/gcc/5/lib/gcc/x86_64-pc-solaris2.11/5.4.0/../../../../include/c++/5.4.0/bits/move.h:57: /usr/gcc/5/lib/gcc/x86_64-pc-solaris2.11/5.4.0/../../../../include/c++/5.4.0/type_traits:311:39: error: __float128 is not supported on this target struct __is_floating_point_helper<__float128> ^ during make check-all. The line above is inside #if !defined(__STRICT_ANSI__) && defined(_GLIBCXX_USE_FLOAT128) template<> struct __is_floating_point_helper<__float128> : public true_type { }; #endif While the libstdc++ header indicates support for __float128, clang does not, but should. The following patch implements this and fixed those errors. Differential Revision: https://reviews.llvm.org/D41240 llvm-svn: 330572
* [X86] WaitPKG intrinsicsGabor Buella2018-04-202-0/+8
| | | | | | | | | | Reviewers: craig.topper, zvi Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45254 llvm-svn: 330463
* Record whether a module came from a private module mapJordan Rose2018-04-201-1/+4
| | | | | | | | | | | Right now we only use this information in one place, immediately after we calculate it, but it's still nice information to have. The Swift project is going to use this to tidy up its "API notes" feature (see past discussion on cfe-dev that never quite converged). Reviewed by Bruno Cardoso Lopes. llvm-svn: 330452
* [AAch64] Add the __ARM_FEATURE_DOTPROD macro definitionJunmo Park2018-04-172-0/+7
| | | | | | | | | This matches what GCC does. https://github.com/gcc-mirror/gcc/blob/master/gcc/config/aarch64/aarch64-c.c Differential Revision: https://reviews.llvm.org/D45544 llvm-svn: 330229
* [XRay] Add clang builtin for xray typed events.Keith Wyss2018-04-171-0/+1
| | | | | | | | | | | | | | | | | | | Summary: A clang builtin for xray typed events. Differs from __xray_customevent(...) by the presence of a type tag that is vended by compiler-rt in typical usage. This allows xray handlers to expand logged events with their type description and plugins to process traced events based on type. This change depends on D45633 for the intrinsic definition. Reviewers: dberris, pelikan, rnk, eizan Subscribers: cfe-commits, llvm-commits Differential Revision: https://reviews.llvm.org/D45716 llvm-svn: 330220
* [ARM] Compute a target feature which corresponds to the ARM version.Eli Friedman2018-04-161-0/+11
| | | | | | | | | | | | | | | | Currently, the interaction between the triple, the CPU, and the supported features is a mess: the driver edits the triple to indicate the supported architecture version, and the LLVM backend uses this to figure out what instructions are legal. This makes it difficult to understand what's happening, and makes it impossible to LTO together two modules with different computed architectures. Instead of relying on triple rewriting to get the correct target features, we should add the right target features explicitly. Differential Revision: https://reviews.llvm.org/D45240 llvm-svn: 330169
* Limit types of builtins that can be redeclared.Erich Keane2018-04-161-0/+7
| | | | | | | | | | | | | | | | | | As reported here: https://bugs.llvm.org/show_bug.cgi?id=37033 Any usage of a builtin function that uses a va_list by reference will cause an assertion when redeclaring it. After discussion in the review, it was concluded that the correct way of accomplishing this fix is to make attempts to redeclare certain builtins an error. Unfortunately, doing this limitation for all builtins is likely a breaking change, so this commit simply limits it to types with custom type checking and those that take a reference. Two tests needed to be updated to make this work. Differential Revision: https://reviews.llvm.org/D45383 llvm-svn: 330160
* Defer adding keywords to the identifier table until after the language ↵Aaron Ballman2018-04-161-6/+9
| | | | | | | | | | options have been loaded from the AST file. This fixes issues with "class" being reported as an identifier in "enum class" because the construct is not present when using default language options. Patch by Johann Klähn. llvm-svn: 330159
* [X86] Introduce archs: goldmont-plus & tremontGabor Buella2018-04-161-0/+14
| | | | | | | | | | | | Reviewers: craig.topper Reviewed By: craig.topper Subscribers: cfe-commits Differential Revision: https://reviews.llvm.org/D45613 llvm-svn: 330110
* [X86] Introduce cldemote intrinsicGabor Buella2018-04-132-0/+7
| | | | | | | | | | Reviewers: craig.topper, zvi Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45257 llvm-svn: 329993
* [XRay][clang] Add flag to choose instrumentation bundlesDean Michael Berris2018-04-132-0/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This change addresses http://llvm.org/PR36926 by allowing users to pick which instrumentation bundles to use, when instrumenting with XRay. In particular, the flag `-fxray-instrumentation-bundle=` has four valid values: - `all`: the default, emits all instrumentation kinds - `none`: equivalent to -fnoxray-instrument - `function`: emits the entry/exit instrumentation - `custom`: emits the custom event instrumentation These can be combined either as comma-separated values, or as repeated flag values. Reviewers: echristo, kpw, eizan, pelikan Reviewed By: pelikan Subscribers: mgorny, cfe-commits Differential Revision: https://reviews.llvm.org/D44970 llvm-svn: 329985
* [x86] wbnoinvd intrinsicGabor Buella2018-04-112-0/+9
| | | | | | | | | | | | | | The WBNOINVD instruction writes back all modified cache lines in the processor’s internal cache to main memory but does not invalidate (flush) the internal caches. Reviewers: craig.topper, zvi, ashlykov Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D43817 llvm-svn: 329848
* [NVPTX] Removed 'satom' feature which is no longer used.Artem Belevich2018-04-112-2/+0
| | | | | | Differential Revision: https://reviews.llvm.org/D45061 llvm-svn: 329830
* [NVPTX, CUDA] Improved feature constraints on NVPTX target builtins.Artem Belevich2018-04-112-0/+19
| | | | | | | | | | When NVPTX TARGET_BUILTIN specifies sm_XX or ptxYY as required feature, consider those features available if we're compiling for GPU >= sm_XX or have enabled PTX version >= ptxYY. Differential Revision: https://reviews.llvm.org/D45061 llvm-svn: 329829
* bpf: accept all asm register namesYonghong Song2018-04-111-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Sometimes when people compile bpf programs with "clang ... -target bpf ...", the kernel header files may contain host arch inline assembly codes as in the patch https://patchwork.kernel.org/patch/10119683/ by Arnaldo Carvaldo de Melo. The current workaround in the above patch is to guard the inline assembly with "#ifndef __BPF__" marco. So when __BPF__ is defined, these macros will have no use. Such a method is not extensible. As a matter of fact, most of these inline assembly codes will be thrown away at the end of clang compilation. So for bpf target, this patch accepts all asm register names in clang AST stage. The name will be checked again during llc code generation if the inline assembly code is indeed for bpf programs. With this patch, the above "#ifndef __BPF__" is not needed any more in https://patchwork.kernel.org/patch/10119683/. Signed-off-by: Yonghong Song <yhs@fb.com> llvm-svn: 329823
* [X86] Split up -march=icelake to -client & -serverGabor Buella2018-04-101-2/+4
| | | | | | | | | | Reviewers: craig.topper, zvi, echristo Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45056 llvm-svn: 329741
* Attempt to fix Windows build after r329698.Nico Weber2018-04-101-1/+1
| | | | llvm-svn: 329702
* [X86] Disable SGX for Skylake ServerGabor Buella2018-04-101-1/+2
| | | | | | | | | | Reviewers: craig.topper, zvi, echristo Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45058 llvm-svn: 329701
* Use llvm::sys::fs::real_path() in clang.Nico Weber2018-04-101-16/+2
| | | | | | | No expected behavior change. https://reviews.llvm.org/D45165 llvm-svn: 329698
* [CUDA] Revert defining __CUDA_ARCH__ for amdgcn targetsYaxun Liu2018-04-095-69/+55
| | | | | | | | | | amdgcn targets only support HIP, which does not define __CUDA_ARCH__. this is a partial unroll of r329232 / D45277. Differential Revision: https://reviews.llvm.org/D45387 llvm-svn: 329584
* [XRay][llvm+clang] Consolidate attribute list filesDean Michael Berris2018-04-091-7/+17
| | | | | | | | | | | | | | | | | | | | | | | | Summary: This change consolidates the always/never lists that may be provided to clang to externally control which functions should be XRay instrumented by imbuing attributes. The files follow the same format as defined in https://clang.llvm.org/docs/SanitizerSpecialCaseList.html for the sanitizer blacklist. We also deprecate the existing `-fxray-instrument-always=` and `-fxray-instrument-never=` flags, in favour of `-fxray-attr-list=`. This fixes http://llvm.org/PR34721. Reviewers: echristo, vlad.tsyrklevich, eugenis Reviewed By: vlad.tsyrklevich Subscribers: llvm-commits, cfe-commits Differential Revision: https://reviews.llvm.org/D45357 llvm-svn: 329543
* [HIP] define __CUDA_ARCH_=1 for amdgcn targetsYaxun Liu2018-04-061-1/+1
| | | | | | Differential Revision: https://reviews.llvm.org/D45277 llvm-svn: 329420
* Fix typos in clangAlexander Kornienko2018-04-064-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Found via codespell -q 3 -I ../clang-whitelist.txt Where whitelist consists of: archtype cas classs checkk compres definit frome iff inteval ith lod methode nd optin ot pres statics te thru Patch by luzpaz! (This is a subset of D44188 that applies cleanly with a few files that have dubious fixes reverted.) Differential revision: https://reviews.llvm.org/D44188 llvm-svn: 329399
* [PATCH] [RISCV] Extend getTargetDefines for RISCVTargetInfoShiva Chen2018-04-052-1/+64
| | | | | | | | | | | | | | Summary: This patch extend getTargetDefines and implement handleTargetFeatures and hasFeature. and define corresponding marco for those features. Reviewers: asb, apazos, eli.friedman Differential Revision: https://reviews.llvm.org/D44727 Patch by Kito Cheng. llvm-svn: 329278
* [CUDA] Add amdgpu sub archsYaxun Liu2018-04-046-42/+152
| | | | | | | | | Patch by Greg Rodgers. Revised and lit tests added by Yaxun Liu. Differential Revision: https://reviews.llvm.org/D45277 llvm-svn: 329232
* Fixes errors with FS iterators caused by https://reviews.llvm.org/D44960Max Moroz2018-04-041-6/+8
| | | | | | | | | | | | | | | | | | | | Summary: In https://reviews.llvm.org/D44960, file status check is executed every time a real file system directory iterator is constructed or incremented, and emits an error code. This change list fixes the errors in VirtualFileSystem caused by https://reviews.llvm.org/D44960. Patch by Yuke Liao (@liaoyuke). Reviewers: vsk, pcc, zturner, liaoyuke Reviewed By: vsk Subscribers: mgrang, cfe-commits Differential Revision: https://reviews.llvm.org/D45178 llvm-svn: 329223
* [Hexagon] Remove -mhvx-double and the corresponding subtarget featureKrzysztof Parzyszek2018-04-031-1/+0
| | | | | | | Specifying the HVX vector length should be done via the -mhvx-length option. llvm-svn: 329077
* CodeGenCXX: support PreserveMostCC in MS ABISaleem Abdulrasool2018-04-021-0/+1
| | | | | | | | Microsoft has reserved 'U' for the PreserveMostCC which is used in the swift runtime. Add support for this. This allows the swift runtime to be built for Windows again. llvm-svn: 329025
* [AArch64]: Add support for parsing rN registers.Manoj Gupta2018-03-291-1/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Allow rN registers to be simply parsed as correspoing xN registers. The "register ... asm("rN")" is an command to the compiler's register allocator, not an operand to any individual assembly instruction. GCC documents this syntax as "...the name of the register that should be used." This is needed to support the changes in Linux kernel (see https://lkml.org/lkml/2018/3/1/268 ) Note: This will add support only for the limited use case of register ... asm("rN"). Any other uses that make rN leak into assembly are not supported. Reviewers: kristof.beyls, rengolin, peter.smith, t.p.northover Reviewed By: peter.smith Subscribers: javed.absar, eraman, cfe-commits, srhines Differential Revision: https://reviews.llvm.org/D44815 llvm-svn: 328829
* [Basic] Fix some Clang-tidy modernize and Include What You Use warnings; ↵Eugene Zelenko2018-03-284-103/+193
| | | | | | other minor fixes (NFC). llvm-svn: 328735
* [ObjC++] Make parameter passing and function return compatible with ObjCAkira Hatanaka2018-03-282-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ObjC and ObjC++ pass non-trivial structs in a way that is incompatible with each other. For example: typedef struct { id f0; __weak id f1; } S; // this code is compiled in c++. extern "C" { void foo(S s); } void caller() { // the caller passes the parameter indirectly and destructs it. foo(S()); } // this function is compiled in c. // 'a' is passed directly and is destructed in the callee. void foo(S a) { } This patch fixes the incompatibility by passing and returning structs with __strong or weak fields using the C ABI in C++ mode. __strong and __weak fields in a struct do not cause the struct to be destructed in the caller and __strong fields do not cause the struct to be passed indirectly. Also, this patch fixes the microsoft ABI bug mentioned here: https://reviews.llvm.org/D41039?id=128767#inline-364710 rdar://problem/38887866 Differential Revision: https://reviews.llvm.org/D44908 llvm-svn: 328731
* AMDGPU: Update datalayout for stack alignmentMatt Arsenault2018-03-271-2/+2
| | | | llvm-svn: 328657
* [clang] Change std::sort to llvm::sort in response to r327219Mandeep Singh Grang2018-03-271-2/+2
| | | | | | | | | | | r327219 added wrappers to std::sort which randomly shuffle the container before sorting. This will help in uncovering non-determinism caused due to undefined sorting order of objects having the same key. To make use of that infrastructure we need to invoke llvm::sort instead of std::sort. llvm-svn: 328636
* [AMDGPU] Fix codegen for inline assemblyYaxun Liu2018-03-231-0/+13
| | | | | | | | Need to override convertConstraint to recognise amdgpu specific register names. Differential Revision: https://reviews.llvm.org/D44533 llvm-svn: 328359
* Basic: support PreserveMost and PreserveAll on Windows ARMSaleem Abdulrasool2018-03-201-0/+2
| | | | | | | Do not ignore these calling conventions on Windows ARM. They are used by the swift runtime for certain calls. llvm-svn: 328007
* [ARM] Pass half or i16 types for NEON intrinsicsSjoerd Meijer2018-03-194-5/+6
| | | | | | | | | | | | | | | For generating NEON intrinsics, this determines the NEON data type, and whether it should be a half type or an i16 type. I.e., we always pass a half type for AArch64, this hasn't changed, but now also for ARM but only when FullFP16 is enabled, and i16 otherwise. This is intended to be non-functional change, but together with the backend work in D44538 which adds support for f16 vectors, this enables adding the AArch32 FP16 (vector) intrinsics. Differential Revision: https://reviews.llvm.org/D44561 llvm-svn: 327836
* [ARM] ACLE FP16 feature test macrosSjoerd Meijer2018-03-132-0/+13
| | | | | | | | | This is a partial recommit of r327189 that was reverted due to test issues. I.e., this recommits minimal functional change, the FP16 feature test macros, and adds tests that were missing in the original commit. llvm-svn: 327455
* This reverts "r327189 - [ARM] Add ARMv8.2-A FP16 vector intrinsic"Sjoerd Meijer2018-03-132-10/+0
| | | | | | | This is causing problems in testing, and PR36683 was raised. Reverting it until we have sorted out how to pass f16 vectors. llvm-svn: 327437
* [ARM] Add ARMv8.2-A FP16 vector intrinsicAbderrazek Zaafrani2018-03-092-0/+10
| | | | | | | | Add the fp16 neon vector intrinsic for ARM as described in the ARM ACLE document. Reviews in https://reviews.llvm.org/D43650 llvm-svn: 327189
* Correct the alignment for the PS4 targetMatthew Voss2018-03-071-0/+1
| | | | | | https://reviews.llvm.org/D44218 llvm-svn: 326942
* [AMDGPU] Clean up old address space mapping and fix constant address space valueYaxun Liu2018-03-052-93/+47
| | | | | | Differential Revision: https://reviews.llvm.org/D43911 llvm-svn: 326725
* [WebAssembly] Add exception handling optionHeejin Ahn2018-03-022-1/+11
| | | | | | | | | | | | Summary: Add exception handling option to clang. Reviewers: dschuff Subscribers: jfb, sbc100, jgravelle-google, sunfish, cfe-commits Differential Revision: https://reviews.llvm.org/D43681 llvm-svn: 326517
* AMDGPU: Define FP_FAST_FMA{F} macros for amdgcnKonstantin Zhuravlyov2018-02-272-148/+194
| | | | | | | | | | - Expand GK_*s (i.e. GFX6 -> GFX600, GFX601, etc.) - This allows us to choose features correctly in some cases (for example, fast fmaf is available on gfx600, but not gfx601) - Move HasFMAF, HasFP64, HasLDEXPF to GPUInfo tables - Add HasFastFMA, HasFastFMAF to GPUInfo tables - Add missing tests llvm-svn: 326254
* Fix for LLVM r326109David Zarzycki2018-02-261-2/+4
| | | | llvm-svn: 326110
* [RISCV] Enable __int128_t and __uint128_t through clang flagMandeep Singh Grang2018-02-251-1/+3
| | | | | | | | | | | | | | | | Summary: If the flag -fforce-enable-int128 is passed, it will enable support for __int128_t and __uint128_t types. This flag can then be used to build compiler-rt for RISCV32. Reviewers: asb, kito-cheng, apazos, efriedma Reviewed By: asb, efriedma Subscribers: shiva0217, efriedma, jfb, dschuff, sdardis, sbc100, jgravelle-google, aheejin, rbar, johnrusso, simoncook, jordy.potman.lists, sabuasal, niosHD, cfe-commits Differential Revision: https://reviews.llvm.org/D43105 llvm-svn: 326045
* bpf: Hook target feature "alu32" with LLVMYonghong Song2018-02-231-1/+8
| | | | | | | | | | | | | | LLVM has supported a new target feature "alu32" which could be enabled or disabled by "-mattr=[+|-]alu32" when using llc. This patch link Clang with it, so it could be also done by passing related options to Clang, for example: -Xclang -target-feature -Xclang +alu32 Signed-off-by: Jiong Wang <jiong.wang@netronome.com> Reviewed-by: Yonghong Song <yhs@fb.com> llvm-svn: 325996
* [X86] Disable CLWB in Cannon LakeCraig Topper2018-02-211-1/+2
| | | | | | | | | | | Cannon Lake does not support CLWB, therefore it does not include all features listed under SKX. Patch by Gabor Buella Differential Revision: https://reviews.llvm.org/D43459 llvm-svn: 325655
* [mips] Spectre variant two mitigation for MIPSR2Simon Dardis2018-02-211-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch provides mitigation for CVE-2017-5715, Spectre variant two, which affects the P5600 and P6600. It provides the option -mindirect-jump=hazard, which instructs the LLVM backend to replace indirect branches with their hazard barrier variants. This option is accepted when targeting MIPS revision two or later. The migitation strategy suggested by MIPS for these processors is to use two hazard barrier instructions. 'jalr.hb' and 'jr.hb' are hazard barrier variants of the 'jalr' and 'jr' instructions respectively. These instructions impede the execution of instruction stream until architecturally defined hazards (changes to the instruction stream, privileged registers which may affect execution) are cleared. These instructions in MIPS' designs are not speculated past. These instructions are used with the option -mindirect-jump=hazard when branching indirectly and for indirect function calls. These instructions are defined by the MIPS32R2 ISA, so this mitigation method is not compatible with processors which implement an earlier revision of the MIPS ISA. Implementation note: I've opted to provide this as an -mindirect-jump={hazard,...} style option in case alternative mitigation methods are required for other implementations of the MIPS ISA in future, e.g. retpoline style solutions. Reviewers: atanasyan Differential Revision: https://reviews.llvm.org/D43487 llvm-svn: 325651
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