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llvm-svn: 219880
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Soon we'll need to have access to blacklist before the CodeGen
phase (see http://reviews.llvm.org/D5687), so parse and construct
the blacklist earlier.
llvm-svn: 219857
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This change moves SanitizerBlacklist.h from lib/CodeGen
to public Clang headers in include/clang/Basic. SanitizerBlacklist
is currently only used in CodeGen to decide which functions/modules
should be instrumented, but this will soon change as ASan will
optionally modify class layouts during AST construction
(http://reviews.llvm.org/D5687). We need blacklist machinery
to be available at this point.
llvm-svn: 219840
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PPC64/NetBSD.
llvm-svn: 219839
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Use switch for FreeBSD check to allow easier extension.
llvm-svn: 219838
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Thumb1 has legitimate reasons for preferring 32-bit alignment of types
i1/i8/i16, since the 16-bit encoding of "add rD, sp, #imm" requires #imm to be
a multiple of 4. However, this is a trade-off betweem code size and RAM usage;
the DataLayout string is not the best place to represent it even if desired.
So this patch removes the extra Thumb requirements, hopefully making ARM and
Thumb completely compatible in this respect.
llvm-svn: 219735
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Before, ARM and Thumb mode code had different preferred alignments, which could
lead to some rather unexpected results. There's justification for reducing it
from the default 64-bits (wasted space), but I don't think there is for going
below 32-bits.
There's no actual ABI change here, just to reassure people.
llvm-svn: 219720
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Patch by Matthew Wahab.
llvm-svn: 219607
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Per Hal Finkel's review, improving typability of some variable names.
llvm-svn: 219515
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The current VSX feature for PowerPC specifies availability of the VSX
instructions added with the 2.06 architecture version. With 2.07, the
architecture adds new instructions to both the Category:Vector and
Category:VSX instruction sets. Additionally, unaligned vector storage
operations have improved performance.
This patch adds a feature to provide access to the new instructions
and performance capabilities of Power8. For compatibility with GCC,
the feature is controlled via a new -mpower8-vector switch, and the
feature causes the __POWER8_VECTOR__ builtin define to be generated by
the preprocessor.
There is a companion patch for llvm being committed at the same time.
llvm-svn: 219502
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Includes parsing and semantic analysis for 'omp teams' directive support from OpenMP 4.0. Adds additional analysis to 'omp target' directive with 'omp teams' directive.
llvm-svn: 219385
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semantic analysis for 'omp teams' directive support from OpenMP 4.0. Adds additional analysis to 'omp target' directive with 'omp teams' directive."
This reverts commit r219197 because it broke ARM self-hosting buildbots with
segmentation fault errors in many tests.
llvm-svn: 219289
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Includes parsing and semantic analysis for 'omp teams' directive support from OpenMP 4.0. Adds additional analysis to 'omp target' directive with 'omp teams' directive.
llvm-svn: 219197
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in availability attribute by preserving this info.
in VersionTuple and using it in pretty printing of attributes
and yet using '.' as separator when diagnosing unavailable
message calls. rdar://18490958
llvm-svn: 219124
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These were uncoveredby my yet undelivered patch.
llvm-svn: 218774
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The Cortex-M7 has 3 options for its FPU: none, FPv5-SP-D16 and
FPv5-DP-D16. FPv5 has the same instructions as FP-ARMv8, so it can be
modeled using the same target feature, and all double-precision
operations are already disabled by the fp-only-sp target features.
llvm-svn: 218748
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llvm-svn: 218666
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llvm-svn: 218299
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llvm-svn: 218121
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Added -madx option
llvm-svn: 218116
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llvm-svn: 218110
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128-bit unless the target CPU supports AVX.
rdar://problem/11846140
llvm-svn: 218082
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The 'x' constraint is for "any SSE register", and GCC seems to include the
256-bit ymm registers in that concept.
llvm-svn: 218073
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llvm-svn: 218064
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llvm-svn: 218029
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The ARM ACLE describes the values as hex constants rather than numeric
constants; follow suit. Address post-commit review comments from Jon Roelofs.
llvm-svn: 218009
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S, D, A, y, x, f, t, and u.
This is a follow-up patch for r167717.
rdar://problem/11846140
rdar://problem/17476970
llvm-svn: 217994
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Extend ARM ACLE support (Section 6.5.1) for AArch32. Define __ARM_FP if
hardware floating point support is available as per the value defined by the
ACLE.
llvm-svn: 217957
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Tweak handleTargetFeature for the ARM(32) target to use range based for loops.
NFC.
llvm-svn: 217956
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Fix whitespace. NFC.
llvm-svn: 217955
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Patch by Assad Hashmi!
llvm-svn: 217760
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approach for calling conventions.
llvm-svn: 217696
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Summary:
le64 is a generic little-endian 64-bit processor, mimicking le32.
Also see the associated LLVM change.
Test Plan: make check-all
Reviewers: dschuff
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D5318
llvm-svn: 217694
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off by default, issue a warning if %s directive is used in
certain CF/NS formatting APIs, to assist user in deprecating
use of such %s in these APIs. rdar://18182443
llvm-svn: 217467
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Because we may change the name of a FileEntry inside getFile, the name
returned by FileEntry::getName() could be destroyed. This was causing a
use-after-free when searching the HeaderFileInfo on-disk hashtable for a
module or pch.
llvm-svn: 217385
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const from some other StringRefs since its implicitly const already.
llvm-svn: 216825
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llvm-svn: 216715
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llvm-svn: 216585
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llvm-svn: 216576
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llvm-svn: 216476
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to +initilize as this results in an extra call
to this method. rdar://16628028
llvm-svn: 216271
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'blah', previous versions of the compiler did not override when parameters only differed by const/volatile qualifiers."
This warning is basically useless because the "previous versions" being referred to is MSVC 2005 and earlier, and we obviously do not care about them. However, this warning isn't particularly chatty (I don't recall ever seeing it previously), and it has the opportunity to point out cases where the cv-qualifiers differ unintentionally (like this case), so I am leaving it enabled for now.
llvm-svn: 216267
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variable that has regiser constraint "r" is not 64-bit.
General register operands are output using 64-bit "x" register names, regardless
of the size of the variable, unless the asm operand is prefixed with the "%w"
modifier. This surprises and confuses many users who aren't familiar with
aarch64 inline assembly rules.
With this commit, a note and fixit hint are printed which tell the users that
they need modifier "%w" in order to output a "w" register instead of an "x"
register.
<rdar://problem/12764785>
llvm-svn: 216260
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functionality change.
llvm-svn: 216222
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This fixes a crash in the OCL_ImgProc/Canny OpenCV test.
NOTE: This is a candidate for the 3.5 branch.
llvm-svn: 216181
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llvm-svn: 216180
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llvm-svn: 215926
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llvm-svn: 215925
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llvm-svn: 215856
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llvm-svn: 215853
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