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* Revert "[Modules] Allow modules specified by -fmodule-map-file to shadow ↵Bruno Cardoso Lopes2018-01-041-6/+1
| | | | | | | | | | | implicitly found ones" This reverts r321781 until I fix the leaks pointed out by bots: http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-fast/builds/12146 http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-bootstrap/builds/3741 llvm-svn: 321786
* [Modules] Allow modules specified by -fmodule-map-file to shadow implicitly ↵Bruno Cardoso Lopes2018-01-041-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | found ones When modules come from module map files explicitly specified by -fmodule-map-file= arguments, allow those to override/shadow modules with the same name that are found implicitly by header search. If such a module is looked up by name (e.g. @import), we will always find the one from -fmodule-map-file. If we try to use a shadowed module by including one of its headers report an error. This enables developers to force use of a specific copy of their module to be used if there are multiple copies that would otherwise be visible, for example if they develop modules that are installed in the default search paths. Patch originally by Ben Langmuir, http://lists.llvm.org/pipermail/cfe-commits/Week-of-Mon-20151116/143425.html Based on cfe-dev discussion: http://lists.llvm.org/pipermail/cfe-dev/2015-November/046164.html Differential Revision: https://reviews.llvm.org/D31269 rdar://problem/23612102 llvm-svn: 321781
* [OpenMP] Initial implementation of code generation for pragma 'target teams ↵Carlo Bertolli2018-01-031-1/+5
| | | | | | | | | | distribute parallel for' on host https://reviews.llvm.org/D41709 This patch includes code generation and testing for offloading when target device is host. llvm-svn: 321759
* Revert r321504 "[X86] Don't accidentally enable PKU on cannon lake and ↵Craig Topper2017-12-291-5/+2
| | | | | | | | | | | | | | icelake or CLWB on cannonlake." I based that commit on what was in Intel's public documentation here https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf Which specifically said CLWB wasn't until Icelake. But I've since cross checked with SDE and it thinks these features exist on CNL and ICL. So now I don't know what to believe. I've added test coverage of the current behavior as part of the revert so at least now have proof of what we're doing. llvm-svn: 321547
* Avoid int to string conversion in Twine or raw_ostream contexts.Benjamin Kramer2017-12-282-5/+5
| | | | | | Some output changes from uppercase hex to lowercase hex, no other functionality change intended. llvm-svn: 321526
* [X86] Don't accidentally enable PKU on cannon lake and icelake or CLWB on ↵Craig Topper2017-12-271-2/+4
| | | | | | | | cannonlake. We have cannonlake and icelake inheriting from skylake server in a switch using fallthroughs. But they aren't perfect supersets of skylake server. llvm-svn: 321504
* [X86] Enable avx512vpopcntdq and clwb for icelake.Craig Topper2017-12-271-1/+2
| | | | | | Per table 1-1 of the October 2017 edition of Intel® Architecture Instruction Set Extensions and Future Features Programming Reference llvm-svn: 321502
* [x86][icelake][vbmi2]Coby Tayree2017-12-272-7/+17
| | | | | | | | | | | | | | | added vbmi2 feature recognition added intrinsics support for vbmi2 instructions _mm[128,256,512]_mask[z]_compress_epi[16,32] _mm[128,256,512]_mask_compressstoreu_epi[16,32] _mm[128,256,512]_mask[z]_expand_epi[16,32] _mm[128,256,512]_mask[z]_expandloadu_epi[16,32] _mm[128,256,512]_mask[z]_sh[l,r]di_epi[16,32,64] _mm[128,256,512]_mask_sh[l,r]dv_epi[16,32,64] matching a similar work on the backend (D40206) Differential Revision: https://reviews.llvm.org/D41557 llvm-svn: 321487
* [x86][icelake][vnni]Coby Tayree2017-12-272-2/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | added vnni feature recognition added intrinsics support for VNNI instructions _mm256_mask_dpbusd_epi32 _mm256_maskz_dpbusd_epi32 _mm256_dpbusd_epi32 _mm256_mask_dpbusds_epi32 _mm256_maskz_dpbusds_epi32 _mm256_dpbusds_epi32 _mm256_mask_dpwssd_epi32 _mm256_maskz_dpwssd_epi32 _mm256_dpwssd_epi32 _mm256_mask_dpwssds_epi32 _mm256_maskz_dpwssds_epi32 _mm256_dpwssds_epi32 _mm128_mask_dpbusd_epi32 _mm128_maskz_dpbusd_epi32 _mm128_dpbusd_epi32 _mm128_mask_dpbusds_epi32 _mm128_maskz_dpbusds_epi32 _mm128_dpbusds_epi32 _mm128_mask_dpwssd_epi32 _mm128_maskz_dpwssd_epi32 _mm128_dpwssd_epi32 _mm128_mask_dpwssds_epi32 _mm128_maskz_dpwssds_epi32 _mm128_dpwssds_epi32 _mm512_mask_dpbusd_epi32 _mm512_maskz_dpbusd_epi32 _mm512_dpbusd_epi32 _mm512_mask_dpbusds_epi32 _mm512_maskz_dpbusds_epi32 _mm512_dpbusds_epi32 _mm512_mask_dpwssd_epi32 _mm512_maskz_dpwssd_epi32 _mm512_dpwssd_epi32 _mm512_mask_dpwssds_epi32 _mm512_maskz_dpwssds_epi32 _mm512_dpwssds_epi32 matching a similar work on the backend (D40208) Differential Revision: https://reviews.llvm.org/D41558 llvm-svn: 321484
* [x86][icelake][bitalg]Coby Tayree2017-12-272-6/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | added bitalg feature recognition added intrinsics support for bitalg instructions _mm512_popcnt_epi16 _mm512_mask_popcnt_epi16 _mm512_maskz_popcnt_epi16 _mm512_popcnt_epi8 _mm512_mask_popcnt_epi8 _mm512_maskz_popcnt_epi8 _mm512_mask_bitshuffle_epi64_mask _mm512_bitshuffle_epi64_mask _mm256_popcnt_epi16 _mm256_mask_popcnt_epi16 _mm256_maskz_popcnt_epi16 _mm128_popcnt_epi16 _mm128_mask_popcnt_epi16 _mm128_maskz_popcnt_epi16 _mm256_popcnt_epi8 _mm256_mask_popcnt_epi8 _mm256_maskz_popcnt_epi8 _mm128_popcnt_epi8 _mm128_mask_popcnt_epi8 _mm128_maskz_popcnt_epi8 _mm256_mask_bitshuffle_epi32_mask _mm256_bitshuffle_epi32_mask _mm128_mask_bitshuffle_epi16_mask _mm128_bitshuffle_epi16_mask matching a similar work on the backend (D40222) Differential Revision: https://reviews.llvm.org/D41564 llvm-svn: 321483
* [x86][icelake][vpclmulqdq]Coby Tayree2017-12-272-1/+17
| | | | | | | | | | | added vpclmulqdq feature recognition added intrinsics support for vpclmulqdq instructions _mm256_clmulepi64_epi128 _mm512_clmulepi64_epi128 matching a similar work on the backend (D40101) Differential Revision: https://reviews.llvm.org/D41573 llvm-svn: 321480
* [x86][icelake][gfni]Coby Tayree2017-12-272-1/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | added gfni feature recognition added intrinsics support for gfni instructions _mm_gf2p8affineinv_epi64_epi8 _mm_mask_gf2p8affineinv_epi64_epi8 _mm_maskz_gf2p8affineinv_epi64_epi8 _mm256_gf2p8affineinv_epi64_epi8 _mm256_mask_gf2p8affineinv_epi64_epi8 _mm256_maskz_gf2p8affineinv_epi64_epi8 _mm512_gf2p8affineinv_epi64_epi8 _mm512_mask_gf2p8affineinv_epi64_epi8 _mm512_maskz_gf2p8affineinv_epi64_epi8 _mm_gf2p8affine_epi64_epi8 _mm_mask_gf2p8affine_epi64_epi8 _mm_maskz_gf2p8affine_epi64_epi8 _mm256_gf2p8affine_epi64_epi8 _mm256_mask_gf2p8affine_epi64_epi8 _mm256_maskz_gf2p8affine_epi64_epi8 _mm512_gf2p8affine_epi64_epi8 _mm512_mask_gf2p8affine_epi64_epi8 _mm512_maskz_gf2p8affine_epi64_epi8 _mm_gf2p8mul_epi8 _mm_mask_gf2p8mul_epi8 _mm_maskz_gf2p8mul_epi8 _mm256_gf2p8mul_epi8 _mm256_mask_gf2p8mul_epi8 _mm256_maskz_gf2p8mul_epi8 _mm512_gf2p8mul_epi8 _mm512_mask_gf2p8mul_epi8 _mm512_maskz_gf2p8mul_epi8 matching a similar work on the backend (D40373) Differential Revision: https://reviews.llvm.org/D41582 llvm-svn: 321477
* [x86][icelake][vaes]Coby Tayree2017-12-272-1/+17
| | | | | | | | | | | | | | | added vaes feature recognition added intrinsics support for vaes instructions, matching a similar work on the backend (D40078) _mm256_aesenc_epi128 _mm512_aesenc_epi128 _mm256_aesenclast_epi128 _mm512_aesenclast_epi128 _mm256_aesdec_epi128 _mm512_aesdec_epi128 _mm256_aesdeclast_epi128 _mm512_aesdeclast_epi128 llvm-svn: 321474
* [X86] Add 'prfchw' to the correct CPUs to match the backend.Craig Topper2017-12-221-0/+3
| | | | llvm-svn: 321341
* Correct hasFeature/isValidFeatureName's handling of shstk/adx/mwaitxErich Keane2017-12-211-2/+7
| | | | | | | | | | | | https://bugs.llvm.org/show_bug.cgi?id=35721 reports that x86intrin.h is issuing a few warnings. This is because attribute target is using isValidFeatureName for its source. It was also discovered that two of these were missing from hasFeature. Additionally, shstk is and ibu are reordered alphabetically, as came up during code review. llvm-svn: 321324
* [AARch64] Add ARMv8.2-A FP16 vector intrinsicsAbderrazek Zaafrani2017-12-211-0/+3
| | | | | | | | Putting back the code that was reverted few weeks ago. Differential Revision: https://reviews.llvm.org/D34161 llvm-svn: 321294
* Make DiagnosticIDs::getAllDiagnostics use std::vector. NFC.Gabor Horvath2017-12-202-2/+2
| | | | | | | | | | | | The size of the result vector is currently around 4600 with Flavor::WarningOrError, which makes std::vector a better candidate than llvm::SmallVector. Patch by: Andras Leitereg! Differential Revision: https://reviews.llvm.org/D39372 llvm-svn: 321190
* Remove llvm::MemoryBuffer const_castsPavel Labath2017-12-201-3/+4
| | | | | | | | | | | | | | | Summary: llvm has grown a WritableMemoryBuffer class, which is convertible (inherits from) a MemoryBuffer. We can use it to avoid conts_casting the buffer contents when we want to write to it. Reviewers: dblaikie, rsmith Subscribers: cfe-commits Differential Revision: https://reviews.llvm.org/D41387 llvm-svn: 321167
* [c++20] P0515R3: Parsing support and basic AST construction for operator <=>.Richard Smith2017-12-141-0/+1
| | | | | | | | | | | | | | | Adding the new enumerator forced a bunch more changes into this patch than I would have liked. The -Wtautological-compare warning was extended to properly check the new comparison operator, clang-format needed updating because it uses precedence levels as weights for determining where to break lines (and several operators increased their precedence levels with this change), thread-safety analysis needed changes to build its own IL properly for the new operator. All "real" semantic checking for this operator has been deferred to a future patch. For now, we use the relational comparison rules and arbitrarily give the builtin form of the operator a return type of 'void'. llvm-svn: 320707
* [OPENMP] Initial codegen for `target teams distribute simd` directive.Alexey Bataev2017-12-131-1/+1
| | | | | | | Host + generic device codegen for `target teams distribute simd` directive. llvm-svn: 320608
* [Hexagon] Add front-end support for Hexagon V65Krzysztof Parzyszek2017-12-131-0/+4
| | | | llvm-svn: 320579
* [mips] Minor update to the comment (NFC)Aleksandar Beserminji2017-12-111-1/+1
| | | | llvm-svn: 320354
* [mips] Removal of microMIPS64R6Aleksandar Beserminji2017-12-111-0/+7
| | | | | | | | | | | microMIPS64R6 is removed from backend, and therefore frontend will show an error when target is microMIPS64R6. This is Clang part of patch. Differential Revision: https://reviews.llvm.org/D35624 llvm-svn: 320351
* [CodeGen][X86] Fix handling of __fp16 vectors.Akira Hatanaka2017-12-093-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit fixes a bug in IRGen where it generates completely broken code for __fp16 vectors on X86. For example when the following code is compiled: half4 hv0, hv1, hv2; // these are vectors of __fp16. void foo221() { hv0 = hv1 + hv2; } clang generates the following IR, in which two i16 vectors are added: @hv1 = common global <4 x i16> zeroinitializer, align 8 @hv2 = common global <4 x i16> zeroinitializer, align 8 @hv0 = common global <4 x i16> zeroinitializer, align 8 define void @foo221() { %0 = load <4 x i16>, <4 x i16>* @hv1, align 8 %1 = load <4 x i16>, <4 x i16>* @hv2, align 8 %add = add <4 x i16> %0, %1 store <4 x i16> %add, <4 x i16>* @hv0, align 8 ret void } To fix the bug, this commit uses the code committed in r314056, which modified clang to promote and truncate __fp16 vectors to and from float vectors in the AST. It also fixes another IRGen bug where a short value is assigned to an __fp16 variable without any integer-to-floating-point conversion, as shown in the following example: __fp16 a; short b; void foo1() { a = b; } @b = common global i16 0, align 2 @a = common global i16 0, align 2 define void @foo1() #0 { %0 = load i16, i16* @b, align 2 store i16 %0, i16* @a, align 2 ret void } rdar://problem/20625184 Differential Revision: https://reviews.llvm.org/D40112 llvm-svn: 320215
* [OPENMP] Initial codegen for `target teams distribute` directive.Alexey Bataev2017-12-081-1/+1
| | | | | | Host + default devices codegen for `target teams distribute` directive. llvm-svn: 320149
* [OpenCL] Fix layering violation by getOpenCLTypeAddrSpaceSven van Haastregt2017-12-062-31/+13
| | | | | | | | | | | | Commit 7ac28eb0a5 / r310911 ("[OpenCL] Allow targets to select address space per type", 2017-08-15) made Basic depend on AST, introducing a circular dependency. Break this dependency by adding the OpenCLTypeKind enum in Basic and map from AST types to this enum in ASTContext. Differential Revision: https://reviews.llvm.org/D40838 llvm-svn: 319883
* [WebAssembly] Don't use Wasm function sections for more than one functionDan Gohman2017-12-051-5/+0
| | | | | | | | | | Patch by Nicholas Wilson! Fixes PR35467. Differential Revision: https://reviews.llvm.org/D40738 llvm-svn: 319801
* AMDGPU: Don't add fp64 feature to r600 subtargetsMatt Arsenault2017-12-051-1/+1
| | | | | | Should fix test after r319709 llvm-svn: 319735
* [OpenMP] Initial implementation of code generation for pragma 'teams ↵Carlo Bertolli2017-12-041-1/+1
| | | | | | | | | | distribute parallel for simd' on host https://reviews.llvm.org/D40795 This includes regression tests for all associated clauses. llvm-svn: 319696
* Now that C++17 is official (https://www.iso.org/standard/68564.html), start ↵Aaron Ballman2017-12-041-1/+1
| | | | | | changing the C++1z terminology over to C++17. NFC intended, these are all mechanical changes. llvm-svn: 319688
* Toolchain: Normalize dwarf, sjlj and seh ehMartell Malone2017-11-294-29/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a re-apply of r319294. adds -fseh-exceptions and -fdwarf-exceptions flags clang will check if the user has specified an exception model flag, in the absense of specifying the exception model clang will then check the driver default and append the model flag for that target to cc1 -fno-exceptions has a higher priority then specifying the model move __SEH__ macro definitions out of Targets into InitPreprocessor behind the -fseh-exceptions flag move __ARM_DWARF_EH__ macrodefinitions out of verious targets and into InitPreprocessor behind the -fdwarf-exceptions flag and arm|thumb check remove unused USESEHExceptions from the MinGW Driver fold USESjLjExceptions into a new GetExceptionModel function that gives the toolchain classes more flexibility with eh models Reviewers: rnk, mstorsjo Differential Revision: https://reviews.llvm.org/D39673 llvm-svn: 319297
* Revert "Toolchain: Normalize dwarf, sjlj and seh eh"Martell Malone2017-11-294-0/+29
| | | | | | | | This reverts rL319294. The windows sanitizer does not like seh on x86. Will re apply with None type for x86 llvm-svn: 319295
* Toolchain: Normalize dwarf, sjlj and seh ehMartell Malone2017-11-294-29/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | adds -fseh-exceptions and -fdwarf-exceptions flags clang will check if the user has specified an exception model flag, in the absense of specifying the exception model clang will then check the driver default and append the model flag for that target to cc1 clang cc1 assumes dwarf is the default if none is passed and -fno-exceptions has a higher priority then specifying the model move __SEH__ macro definitions out of Targets into InitPreprocessor behind the -fseh-exceptions flag move __ARM_DWARF_EH__ macrodefinitions out of verious targets and into InitPreprocessor behind the -fdwarf-exceptions flag and arm|thumb check remove unused USESEHExceptions from the MinGW Driver fold USESjLjExceptions into a new GetExceptionModel function that gives the toolchain classes more flexibility with eh models Reviewers: rnk, mstorsjo Differential Revision: https://reviews.llvm.org/D39673 llvm-svn: 319294
* [OPENMP] Generalize capturing of clauses expressions.Alexey Bataev2017-11-281-7/+9
| | | | | | | The handling and capturing of the non-constant expressions of some of the capturable clauses in combined directives is generalized. llvm-svn: 319227
* [WebAssembly] Add options for using the nontrapping-fptoint feature.Dan Gohman2017-11-282-2/+15
| | | | | | | This adds ways to control use of WebAssembly's new nontrapping-fptoint feature. llvm-svn: 319129
* [OPENMP] Codegen for `distribute parallel for simd` directive.Alexey Bataev2017-11-271-1/+1
| | | | | | Added proper codegen for `distribute parallel for simd` directive. llvm-svn: 319078
* Control-Flow Enforcement Technology - Shadow Stack and Indirect Branch ↵Oren Ben Simhon2017-11-262-0/+10
| | | | | | | | | | | | | | | | | | Tracking support (Clang side) Shadow stack solution introduces a new stack for return addresses only. The stack has a Shadow Stack Pointer (SSP) that points to the last address to which we expect to return. If we return to a different address an exception is triggered. This patch includes shadow stack intrinsics as well as the corresponding CET header. It includes CET clang flags for shadow stack and Indirect Branch Tracking. For more information, please see the following: https://software.intel.com/sites/default/files/managed/4d/2a/control-flow-enforcement-technology-preview.pdf Differential Revision: https://reviews.llvm.org/D40224 Change-Id: I79ad0925a028bbc94c8ecad75f6daa2f214171f1 llvm-svn: 318995
* [OPENMP] General improvement of code, NFC.Alexey Bataev2017-11-221-11/+11
| | | | llvm-svn: 318849
* [X86] Update CPUSupports code to reuse LLVM .def file [NFC]Erich Keane2017-11-221-31/+2
| | | | llvm-svn: 318815
* [OPENMP] Initial support for asynchronous data update, NFC.Alexey Bataev2017-11-211-3/+5
| | | | | | | | | OpenMP 5.0 introduces asynchronous data update/dependecies clauses on target data directives. Patch adds initial support for outer task regions to use task-based codegen for future async target data directives. llvm-svn: 318781
* [MINGW] normalize WIN32 macrosMartell Malone2017-11-217-38/+14
| | | | | | | | | | | | | | move _WIN64 and _WIN32 defines to lib/Basic/Targets/OSTargets.h move WIN32, WIN64 and __MINGW64__ to addMinGWDefines fixes __MINGW64__ not being defined for aarch64 adds WIN32 definition for x64 Reviewers: mstorsjo Differential Revision: https://reviews.llvm.org/D40285 llvm-svn: 318755
* [x86][inline-asm] allow recognition of MPX regs inside ms inline-asm blobCoby Tayree2017-11-211-0/+1
| | | | | | Differential Revision: https://reviews.llvm.org/D38445 llvm-svn: 318739
* [MS] Increase default new alignment for win64 and test itReid Kleckner2017-11-211-1/+1
| | | | | | | | | | | | | | | | | | Summary: This raises __STDCPP_DEFAULT_NEW_ALIGNMENT__ from 8 to 16 on Win64. This matches platforms that follow the usual `2 * sizeof(void*)` alignment requirement for malloc. We might want to consider making that the default rather than relying on long double alignment. Fixes PR35356 Reviewers: STL_MSFT, rsmith Subscribers: cfe-commits Differential Revision: https://reviews.llvm.org/D40277 llvm-svn: 318723
* [X86] Remove 'mm3now' from isValidFeatureName.Craig Topper2017-11-211-2/+0
| | | | | | The correct spelling is '3dnow' which is already in the list. llvm-svn: 318716
* [OpenMP] Initial implementation of code generation for pragma 'teams ↵Carlo Bertolli2017-11-201-1/+4
| | | | | | | | | | distribute parallel for' on host https://reviews.llvm.org/D40187 This patch implements code gen for 'teams distribute parallel for' on the host, including all its clauses and related regression tests. llvm-svn: 318692
* [X86] Add icelake CPU support for -march.Craig Topper2017-11-191-0/+4
| | | | llvm-svn: 318617
* [X86] Set __corei7__ preprocessor defines for skylake server and cannonlake.Craig Topper2017-11-191-5/+2
| | | | | | This is the resolution we came to in D38824. llvm-svn: 318616
* [OpenMP] Show error if VLAs are not supportedJonas Hahnfeld2017-11-183-0/+3
| | | | | | | | | | | | | | Some target devices (e.g. Nvidia GPUs) don't support dynamic stack allocation and hence no VLAs. Print errors with description instead of failing in the backend or generating code that doesn't work. This patch handles explicit uses of VLAs (local variable in target or declare target region) or implicitly generated (private) VLAs for reductions on VLAs or on array sections with non-constant size. Differential Revision: https://reviews.llvm.org/D39505 llvm-svn: 318601
* [OPENMP] Codegen for `target simd` construct.Alexey Bataev2017-11-171-1/+3
| | | | | | Added codegen support for `target simd` directive. llvm-svn: 318536
* [MinGW] Define __ARM_DWARF_EH__ for MinGW/ARMMartin Storsjo2017-11-171-0/+1
| | | | | | | | | Since SVN r318510, the MinGW/ARM configuration defaults to dwarf exception handling. Differential Revision: https://reviews.llvm.org/D39533 llvm-svn: 318511
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