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* [X86] Disable SGX for Skylake ServerGabor Buella2018-04-101-1/+2
| | | | | | | | | | Reviewers: craig.topper, zvi, echristo Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45058 llvm-svn: 329701
* Use llvm::sys::fs::real_path() in clang.Nico Weber2018-04-101-16/+2
| | | | | | | No expected behavior change. https://reviews.llvm.org/D45165 llvm-svn: 329698
* [CUDA] Revert defining __CUDA_ARCH__ for amdgcn targetsYaxun Liu2018-04-095-69/+55
| | | | | | | | | | amdgcn targets only support HIP, which does not define __CUDA_ARCH__. this is a partial unroll of r329232 / D45277. Differential Revision: https://reviews.llvm.org/D45387 llvm-svn: 329584
* [XRay][llvm+clang] Consolidate attribute list filesDean Michael Berris2018-04-091-7/+17
| | | | | | | | | | | | | | | | | | | | | | | | Summary: This change consolidates the always/never lists that may be provided to clang to externally control which functions should be XRay instrumented by imbuing attributes. The files follow the same format as defined in https://clang.llvm.org/docs/SanitizerSpecialCaseList.html for the sanitizer blacklist. We also deprecate the existing `-fxray-instrument-always=` and `-fxray-instrument-never=` flags, in favour of `-fxray-attr-list=`. This fixes http://llvm.org/PR34721. Reviewers: echristo, vlad.tsyrklevich, eugenis Reviewed By: vlad.tsyrklevich Subscribers: llvm-commits, cfe-commits Differential Revision: https://reviews.llvm.org/D45357 llvm-svn: 329543
* [HIP] define __CUDA_ARCH_=1 for amdgcn targetsYaxun Liu2018-04-061-1/+1
| | | | | | Differential Revision: https://reviews.llvm.org/D45277 llvm-svn: 329420
* Fix typos in clangAlexander Kornienko2018-04-064-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Found via codespell -q 3 -I ../clang-whitelist.txt Where whitelist consists of: archtype cas classs checkk compres definit frome iff inteval ith lod methode nd optin ot pres statics te thru Patch by luzpaz! (This is a subset of D44188 that applies cleanly with a few files that have dubious fixes reverted.) Differential revision: https://reviews.llvm.org/D44188 llvm-svn: 329399
* [PATCH] [RISCV] Extend getTargetDefines for RISCVTargetInfoShiva Chen2018-04-052-1/+64
| | | | | | | | | | | | | | Summary: This patch extend getTargetDefines and implement handleTargetFeatures and hasFeature. and define corresponding marco for those features. Reviewers: asb, apazos, eli.friedman Differential Revision: https://reviews.llvm.org/D44727 Patch by Kito Cheng. llvm-svn: 329278
* [CUDA] Add amdgpu sub archsYaxun Liu2018-04-046-42/+152
| | | | | | | | | Patch by Greg Rodgers. Revised and lit tests added by Yaxun Liu. Differential Revision: https://reviews.llvm.org/D45277 llvm-svn: 329232
* Fixes errors with FS iterators caused by https://reviews.llvm.org/D44960Max Moroz2018-04-041-6/+8
| | | | | | | | | | | | | | | | | | | | Summary: In https://reviews.llvm.org/D44960, file status check is executed every time a real file system directory iterator is constructed or incremented, and emits an error code. This change list fixes the errors in VirtualFileSystem caused by https://reviews.llvm.org/D44960. Patch by Yuke Liao (@liaoyuke). Reviewers: vsk, pcc, zturner, liaoyuke Reviewed By: vsk Subscribers: mgrang, cfe-commits Differential Revision: https://reviews.llvm.org/D45178 llvm-svn: 329223
* [Hexagon] Remove -mhvx-double and the corresponding subtarget featureKrzysztof Parzyszek2018-04-031-1/+0
| | | | | | | Specifying the HVX vector length should be done via the -mhvx-length option. llvm-svn: 329077
* CodeGenCXX: support PreserveMostCC in MS ABISaleem Abdulrasool2018-04-021-0/+1
| | | | | | | | Microsoft has reserved 'U' for the PreserveMostCC which is used in the swift runtime. Add support for this. This allows the swift runtime to be built for Windows again. llvm-svn: 329025
* [AArch64]: Add support for parsing rN registers.Manoj Gupta2018-03-291-1/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Allow rN registers to be simply parsed as correspoing xN registers. The "register ... asm("rN")" is an command to the compiler's register allocator, not an operand to any individual assembly instruction. GCC documents this syntax as "...the name of the register that should be used." This is needed to support the changes in Linux kernel (see https://lkml.org/lkml/2018/3/1/268 ) Note: This will add support only for the limited use case of register ... asm("rN"). Any other uses that make rN leak into assembly are not supported. Reviewers: kristof.beyls, rengolin, peter.smith, t.p.northover Reviewed By: peter.smith Subscribers: javed.absar, eraman, cfe-commits, srhines Differential Revision: https://reviews.llvm.org/D44815 llvm-svn: 328829
* [Basic] Fix some Clang-tidy modernize and Include What You Use warnings; ↵Eugene Zelenko2018-03-284-103/+193
| | | | | | other minor fixes (NFC). llvm-svn: 328735
* [ObjC++] Make parameter passing and function return compatible with ObjCAkira Hatanaka2018-03-282-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ObjC and ObjC++ pass non-trivial structs in a way that is incompatible with each other. For example: typedef struct { id f0; __weak id f1; } S; // this code is compiled in c++. extern "C" { void foo(S s); } void caller() { // the caller passes the parameter indirectly and destructs it. foo(S()); } // this function is compiled in c. // 'a' is passed directly and is destructed in the callee. void foo(S a) { } This patch fixes the incompatibility by passing and returning structs with __strong or weak fields using the C ABI in C++ mode. __strong and __weak fields in a struct do not cause the struct to be destructed in the caller and __strong fields do not cause the struct to be passed indirectly. Also, this patch fixes the microsoft ABI bug mentioned here: https://reviews.llvm.org/D41039?id=128767#inline-364710 rdar://problem/38887866 Differential Revision: https://reviews.llvm.org/D44908 llvm-svn: 328731
* AMDGPU: Update datalayout for stack alignmentMatt Arsenault2018-03-271-2/+2
| | | | llvm-svn: 328657
* [clang] Change std::sort to llvm::sort in response to r327219Mandeep Singh Grang2018-03-271-2/+2
| | | | | | | | | | | r327219 added wrappers to std::sort which randomly shuffle the container before sorting. This will help in uncovering non-determinism caused due to undefined sorting order of objects having the same key. To make use of that infrastructure we need to invoke llvm::sort instead of std::sort. llvm-svn: 328636
* [AMDGPU] Fix codegen for inline assemblyYaxun Liu2018-03-231-0/+13
| | | | | | | | Need to override convertConstraint to recognise amdgpu specific register names. Differential Revision: https://reviews.llvm.org/D44533 llvm-svn: 328359
* Basic: support PreserveMost and PreserveAll on Windows ARMSaleem Abdulrasool2018-03-201-0/+2
| | | | | | | Do not ignore these calling conventions on Windows ARM. They are used by the swift runtime for certain calls. llvm-svn: 328007
* [ARM] Pass half or i16 types for NEON intrinsicsSjoerd Meijer2018-03-194-5/+6
| | | | | | | | | | | | | | | For generating NEON intrinsics, this determines the NEON data type, and whether it should be a half type or an i16 type. I.e., we always pass a half type for AArch64, this hasn't changed, but now also for ARM but only when FullFP16 is enabled, and i16 otherwise. This is intended to be non-functional change, but together with the backend work in D44538 which adds support for f16 vectors, this enables adding the AArch32 FP16 (vector) intrinsics. Differential Revision: https://reviews.llvm.org/D44561 llvm-svn: 327836
* [ARM] ACLE FP16 feature test macrosSjoerd Meijer2018-03-132-0/+13
| | | | | | | | | This is a partial recommit of r327189 that was reverted due to test issues. I.e., this recommits minimal functional change, the FP16 feature test macros, and adds tests that were missing in the original commit. llvm-svn: 327455
* This reverts "r327189 - [ARM] Add ARMv8.2-A FP16 vector intrinsic"Sjoerd Meijer2018-03-132-10/+0
| | | | | | | This is causing problems in testing, and PR36683 was raised. Reverting it until we have sorted out how to pass f16 vectors. llvm-svn: 327437
* [ARM] Add ARMv8.2-A FP16 vector intrinsicAbderrazek Zaafrani2018-03-092-0/+10
| | | | | | | | Add the fp16 neon vector intrinsic for ARM as described in the ARM ACLE document. Reviews in https://reviews.llvm.org/D43650 llvm-svn: 327189
* Correct the alignment for the PS4 targetMatthew Voss2018-03-071-0/+1
| | | | | | https://reviews.llvm.org/D44218 llvm-svn: 326942
* [AMDGPU] Clean up old address space mapping and fix constant address space valueYaxun Liu2018-03-052-93/+47
| | | | | | Differential Revision: https://reviews.llvm.org/D43911 llvm-svn: 326725
* [WebAssembly] Add exception handling optionHeejin Ahn2018-03-022-1/+11
| | | | | | | | | | | | Summary: Add exception handling option to clang. Reviewers: dschuff Subscribers: jfb, sbc100, jgravelle-google, sunfish, cfe-commits Differential Revision: https://reviews.llvm.org/D43681 llvm-svn: 326517
* AMDGPU: Define FP_FAST_FMA{F} macros for amdgcnKonstantin Zhuravlyov2018-02-272-148/+194
| | | | | | | | | | - Expand GK_*s (i.e. GFX6 -> GFX600, GFX601, etc.) - This allows us to choose features correctly in some cases (for example, fast fmaf is available on gfx600, but not gfx601) - Move HasFMAF, HasFP64, HasLDEXPF to GPUInfo tables - Add HasFastFMA, HasFastFMAF to GPUInfo tables - Add missing tests llvm-svn: 326254
* Fix for LLVM r326109David Zarzycki2018-02-261-2/+4
| | | | llvm-svn: 326110
* [RISCV] Enable __int128_t and __uint128_t through clang flagMandeep Singh Grang2018-02-251-1/+3
| | | | | | | | | | | | | | | | Summary: If the flag -fforce-enable-int128 is passed, it will enable support for __int128_t and __uint128_t types. This flag can then be used to build compiler-rt for RISCV32. Reviewers: asb, kito-cheng, apazos, efriedma Reviewed By: asb, efriedma Subscribers: shiva0217, efriedma, jfb, dschuff, sdardis, sbc100, jgravelle-google, aheejin, rbar, johnrusso, simoncook, jordy.potman.lists, sabuasal, niosHD, cfe-commits Differential Revision: https://reviews.llvm.org/D43105 llvm-svn: 326045
* bpf: Hook target feature "alu32" with LLVMYonghong Song2018-02-231-1/+8
| | | | | | | | | | | | | | LLVM has supported a new target feature "alu32" which could be enabled or disabled by "-mattr=[+|-]alu32" when using llc. This patch link Clang with it, so it could be also done by passing related options to Clang, for example: -Xclang -target-feature -Xclang +alu32 Signed-off-by: Jiong Wang <jiong.wang@netronome.com> Reviewed-by: Yonghong Song <yhs@fb.com> llvm-svn: 325996
* [X86] Disable CLWB in Cannon LakeCraig Topper2018-02-211-1/+2
| | | | | | | | | | | Cannon Lake does not support CLWB, therefore it does not include all features listed under SKX. Patch by Gabor Buella Differential Revision: https://reviews.llvm.org/D43459 llvm-svn: 325655
* [mips] Spectre variant two mitigation for MIPSR2Simon Dardis2018-02-211-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch provides mitigation for CVE-2017-5715, Spectre variant two, which affects the P5600 and P6600. It provides the option -mindirect-jump=hazard, which instructs the LLVM backend to replace indirect branches with their hazard barrier variants. This option is accepted when targeting MIPS revision two or later. The migitation strategy suggested by MIPS for these processors is to use two hazard barrier instructions. 'jalr.hb' and 'jr.hb' are hazard barrier variants of the 'jalr' and 'jr' instructions respectively. These instructions impede the execution of instruction stream until architecturally defined hazards (changes to the instruction stream, privileged registers which may affect execution) are cleared. These instructions in MIPS' designs are not speculated past. These instructions are used with the option -mindirect-jump=hazard when branching indirectly and for indirect function calls. These instructions are defined by the MIPS32R2 ISA, so this mitigation method is not compatible with processors which implement an earlier revision of the MIPS ISA. Implementation note: I've opted to provide this as an -mindirect-jump={hazard,...} style option in case alternative mitigation methods are required for other implementations of the MIPS ISA in future, e.g. retpoline style solutions. Reviewers: atanasyan Differential Revision: https://reviews.llvm.org/D43487 llvm-svn: 325651
* [AVR] Set the program address space in the data layoutDylan McKay2018-02-191-1/+1
| | | | | | This is accompanied by r325481 in LLVM. llvm-svn: 325483
* [X86] Add 'sahf' CPU feature to frontendDimitry Andric2018-02-172-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Make clang accept `-msahf` (and `-mno-sahf`) flags to activate the `+sahf` feature for the backend, for bug 36028 (Incorrect use of pushf/popf enables/disables interrupts on amd64 kernels). This was originally submitted in bug 36037 by Jonathan Looney <jonlooney@gmail.com>. As described there, GCC also uses `-msahf` for this feature, and the backend already recognizes the `+sahf` feature. All that is needed is to teach clang to pass this on to the backend. The mapping of feature support onto CPUs may not be complete; rather, it was chosen to match LLVM's idea of which CPUs support this feature (see lib/Target/X86/X86.td). I also updated the affected test case (CodeGen/attr-target-x86.c) to match the emitted output. Reviewers: craig.topper, coby, efriedma, rsmith Reviewed By: craig.topper Subscribers: emaste, cfe-commits Differential Revision: https://reviews.llvm.org/D43394 llvm-svn: 325446
* [Basic] Fix some Clang-tidy modernize and Include What You Use warnings; ↵Eugene Zelenko2018-02-164-46/+49
| | | | | | other minor fixes (NFC). llvm-svn: 325412
* Reapply r325193Konstantin Zhuravlyov2018-02-152-91/+101
| | | | llvm-svn: 325203
* Revert r325193 as it breaks buildbotsKonstantin Zhuravlyov2018-02-152-101/+91
| | | | llvm-svn: 325200
* Add missing definition for class static after r325193.Richard Smith2018-02-151-1/+1
| | | | llvm-svn: 325195
* AMDGPU: Cleanup most of the macrosKonstantin Zhuravlyov2018-02-152-91/+101
| | | | | | | | | | | - Insert __AMD__ macro - Insert __AMDGPU__ macro - Insert __devicename__ macro - Add missing tests for arch macros Differential Revision: https://reviews.llvm.org/D36802 llvm-svn: 325193
* [Modules] Add more language features to be used with requires-declarationBruno Cardoso Lopes2018-02-141-0/+5
| | | | | | | | | Features added: c99, c11, c17, cplusplus14 and cplusplus17. rdar://problem/36328787 rdar://problem/36668431 llvm-svn: 325154
* [AMDGPU] Change constant addr space to 4Yaxun Liu2018-02-131-9/+9
| | | | | | Differential Revision: https://reviews.llvm.org/D43171 llvm-svn: 325031
* [NFC] Extract method to SourceManager for traversing the macro "stack"George Karpenkov2018-02-091-0/+6
| | | | | | | | | | | | The code for going up the macro arg expansion is duplicated in many places (and we need it for the analyzer as well, so I did not want to duplicate it two more times). This patch is an NFC, so the semantics should remain the same. Differential Revision: https://reviews.llvm.org/D42458 llvm-svn: 324780
* AMDGPU: Update for datalayout changeMatt Arsenault2018-02-091-3/+3
| | | | llvm-svn: 324748
* AMDGPU/GCN: Bring processors in sync with AMDGPUUsageKonstantin Zhuravlyov2018-02-091-28/+42
| | | | | | | | | | | - Remove gfx800 - Remove gfx804 - Remove gfx901 - Remove gfx903 Differential Revision: https://reviews.llvm.org/D40045 llvm-svn: 324714
* [modules] Fix incorrect diagnostic mapping computation when a module changesRichard Smith2018-02-091-0/+90
| | | | | | | | | | | | | | | diagnostic settings using _Pragma within a macro. The AST writer had previously been assuming that all diagnostic state transitions would occur within a FileID corresponding to a file. When a diagnostic state change occured within a macro, it was unable to form a location for that state change and would instead corrupt the diagnostic state of the "root" node (and thus that of the main compilation). Also introduce a "#pragma clang __debug diag_mapping" debugging utility that I added to track this issue down. llvm-svn: 324695
* Fix UBSan issue with PPC::isValidCPUNameErich Keane2018-02-091-2/+1
| | | | | | | | Apparently storing the pointer to a StringLiteral as a StringRef caused this section of code to issue a ubsan warning. This will hopefully fix that. llvm-svn: 324687
* Add size to constexpr ArraysErich Keane2018-02-081-2/+2
| | | | | | | | What seems to be a bug in older versions of MSVC, constexpr member arrays with a redefinition (to force emission) require their initial definition to have the size between the brackets. llvm-svn: 324682
* Add Rest of Targets Support to ValidCPUList (enabling march notes)Erich Keane2018-02-0821-269/+307
| | | | | | | | | | | A followup to: https://reviews.llvm.org/D42978 Most of the rest of the Targets were pretty rote, so this patch knocks them all out at once. Differential Revision: https://reviews.llvm.org/D43057 llvm-svn: 324676
* Add NVPTX Support to ValidCPUList (enabling march notes)Erich Keane2018-02-083-0/+14
| | | | | | | | | | A followup to: https://reviews.llvm.org/D42978 This patch adds NVPTX support for enabling the march notes. Differential Revision: https://reviews.llvm.org/D43045 llvm-svn: 324675
* Add X86 Support to ValidCPUList (enabling march notes)Erich Keane2018-02-082-2/+15
| | | | | | | | | | A followup to: https://reviews.llvm.org/D42978 This patch adds X86 and X86_64 support for enabling the march notes. Differential Revision: https://reviews.llvm.org/D43041 llvm-svn: 324674
* Make march/target-cpu print a note with the list of valid values for ARMErich Keane2018-02-085-0/+17
| | | | | | | | | | | | When rejecting a march= or target-cpu command line parameter, the message is quite lacking. This patch adds a note that prints all possible values for the current target, if the target supports it. This adds support for the ARM/AArch64 targets (more to come!). Differential Revision: https://reviews.llvm.org/D42978 llvm-svn: 324673
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