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path: root/clang/lib/Basic/Targets.cpp
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* Replace llvm::utostr calls in Twine context with Twines. NFC.Benjamin Kramer2015-12-241-1/+1
| | | | llvm-svn: 256377
* [mips] Add _GCC_HAVE_SYNC_COMPARE_AND_SWAP macros.Daniel Sanders2015-12-221-0/+8
| | | | | | | This fixes the 'pure virtual function called' failure with ThreadPool in a clang-built clang. This fixes the llvm-mips-linux builder. llvm-svn: 256240
* [Cygwin] Enable TLS as emutls.NAKAMURA Takumi2015-12-211-1/+0
| | | | | | | | It resolves clang selfhosting with std::once() for Cygwin. FIXME: It may be EmulatedTLS-generic also for X86-Android. FIXME: Pass EmulatedTLS to LLVM CodeGen from Clang with -femulated-tls. llvm-svn: 256134
* [Hexagon] Update default paths and argumentsKrzysztof Parzyszek2015-12-141-41/+72
| | | | | | | | | - Removed support for hexagonv3 and earlier. - Added handling of hexagonv55 and hexagonv60. - Added handling of target features (hvx, hvx-double). - Updated paths to reflect current directory layout. llvm-svn: 255502
* [WebAssembly] Remove an obsolete TODO comment.Dan Gohman2015-12-051-1/+0
| | | | llvm-svn: 254817
* Teaches clang about Cortex-A35.Christof Douma2015-12-021-1/+1
| | | | | | | | Adds support for the new Cortex-A35 ARMv8-A core. Differential Revision: http://reviews.llvm.org/D15142 llvm-svn: 254505
* ARM v8.1a adds Advanced SIMD instructions for Rounding Double MultiplyAlexandros Lamprineas2015-11-291-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | Add/Subtract. The following instructions are added to AArch32 instruction set: - VQRDMLAH: Vector Saturating Rounding Doubling Multiply Accumulate Returning High Half - VQRDMLSH: Vector Saturating Rounding Doubling Multiply Subtract Returning High Half The following instructions are added to AArch64 instruction set: - SQRDMLAH: Signed Saturating Rounding Doubling Multiply Accumulate Returning High Half - SQRDMLSH: Signed Saturating Rounding Doubling Multiply Subtract Returning High Half This patch adds intrinsic and ACLE macro support for these instructions, as well as corresponding tests. Differential Revision: http://reviews.llvm.org/D14982 llvm-svn: 254250
* [X86] Support for C calling convention only for MCU target.Alexey Bataev2015-11-251-10/+23
| | | | | | | For MCU only C calling convention is allowed, all other calling conventions are not supported. Differential Revision: http://reviews.llvm.org/D14864 llvm-svn: 254063
* AMDGPU: Add support for 's' and 'v' asm constraintsTom Stellard2015-11-191-2/+9
| | | | | | | | | | | | Summary: 's' is used to specify sgprs and 'v' is used to specify vgprs. Reviewers: arsenm, echristo Subscribers: cfe-commits Differential Revision: http://reviews.llvm.org/D14307 llvm-svn: 253610
* Produce a better diagnostic for global register variables.Akira Hatanaka2015-11-181-0/+30
| | | | | | | | | | | | | | | | | | Currently, when there is a global register variable in a program that is bound to an invalid register, clang/llvm prints an error message that is not very user-friendly. This commit improves the diagnostic and moves the check that used to be in the backend to Sema. In addition, it makes changes to error out if the size of the register doesn't match the declared variable size. e.g., volatile register int B asm ("rbp"); rdar://problem/23084219 Differential Revision: http://reviews.llvm.org/D13834 llvm-svn: 253405
* [ARM] Pass in the architecture to TargetParser to cope with API changeBradley Smith2015-11-161-2/+3
| | | | | | | | The TargetParser API to get the default FPU and default extensions has changed so that it can fall back to the architecture in case of a generic CPU. llvm-svn: 253199
* Cull non-standard variants of ARM architectures (NFC)Artyom Skrobov2015-11-121-5/+0
| | | | | | | | | | | | Summary: Clang-side update, corresponding to D14577 Reviewers: rengolin Subscribers: aemerson, cfe-commits, rengolin Differential Revision: http://reviews.llvm.org/D14578 llvm-svn: 252904
* Silencing a -Wreturn-type warning for control reaching the end of a non-void ↵Aaron Ballman2015-11-111-0/+1
| | | | | | function. llvm-svn: 252727
* [WebAssembly] Change long double to be quadruple-precision floating point.Dan Gohman2015-11-101-0/+2
| | | | llvm-svn: 252646
* Add the variant of __sparc_v9__ with five underscores, not just four.Joerg Sonnenberger2015-11-101-1/+3
| | | | llvm-svn: 252640
* Reorganise CPU handling for Sparc. When using -mcpu=v9 and co, __sparcv8Joerg Sonnenberger2015-11-091-14/+88
| | | | | | | | | is not defined for 32bit mode, but __sparcv9 is. Pass down the correct -target-cpu flags to the backend, so that instruction restrictions are applied correctly. Pass down the correct -A flag when not using IAS. The latter is limited to NetBSD targets in this commit. llvm-svn: 252545
* [x86] Additional small fix for MCU psABI supportAndrey Bokhanko2015-11-051-2/+6
| | | | | | | | This patch fixes one more thing in MCU psABI support: LongDoubleWidth should be set to 64. Differential Revision: http://reviews.llvm.org/D14285 llvm-svn: 252156
* [x86] Front-end part of MCU psABI supportAndrey Bokhanko2015-11-021-1/+7
| | | | | | | | | | | This patch implements two things in front-end for MCU psABI support: 1) "long double type is the same as double." 2) "New predefined C/C++ pre-processor symbols: iamcu and iamcu__. Differential Revision: http://reviews.llvm.org/D14205 llvm-svn: 251786
* ARMv7k: implement ABI changes for watchOS from standard iOS.Tim Northover2015-10-301-10/+40
| | | | llvm-svn: 251710
* Watch and TV OS: wire up basic ABI choicesTim Northover2015-10-301-1/+4
| | | | | | | This sets the mostly expected Darwin default ABI options for these two platforms. Active changes from these defaults for watchOS are in a later patch. llvm-svn: 251708
* Preprocessor: define correct tvOS and watchOS version macrosTim Northover2015-10-301-1/+16
| | | | llvm-svn: 251707
* Fix the calling convention of Mingw64 long double valuesReid Kleckner2015-10-281-1/+7
| | | | | | | | | | GCC uses the x87DoubleExtended model for long doubles, and passes them indirectly by address through function calls. Also replace the existing mingw-long-double assembly emitting test with an IR-level test. llvm-svn: 251567
* Simplify boolean conditional return statements in lib/Basic.Rafael Espindola2015-10-241-3/+3
| | | | | | Patch by Richard. llvm-svn: 251214
* [ARM] Renaming +t2dsp feature into +dsp, as discussed on llvm-devArtyom Skrobov2015-10-231-1/+1
| | | | llvm-svn: 251124
* Define weak and __weak to mean ARC-style weak references, even in MRC.John McCall2015-10-221-11/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously, __weak was silently accepted and ignored in MRC mode. That makes this a potentially source-breaking change that we have to roll out cautiously. Accordingly, for the time being, actual support for __weak references in MRC is experimental, and the compiler will reject attempts to actually form such references. The intent is to eventually enable the feature by default in all non-GC modes. (It is, of course, incompatible with ObjC GC's interpretation of __weak.) If you like, you can enable this feature with -Xclang -fobjc-weak but like any -Xclang option, this option may be removed at any point, e.g. if/when it is eventually enabled by default. This patch also enables the use of the ARC __unsafe_unretained qualifier in MRC. Unlike __weak, this is being enabled immediately. Since variables are essentially __unsafe_unretained by default in MRC, the only practical uses are (1) communication and (2) changing the default behavior of by-value block capture. As an implementation matter, this means that the ObjC ownership qualifiers may appear in any ObjC language mode, and so this patch removes a number of checks for getLangOpts().ObjCAutoRefCount that were guarding the processing of these qualifiers. I don't expect this to be a significant drain on performance; it may even be faster to just check for these qualifiers directly on a type (since it's probably in a register anyway) than to do N dependent loads to grab the LangOptions. rdar://9674298 llvm-svn: 251041
* Fix __ARM_FP value for sp-only FPUs with Half-precisionRichard Barton2015-10-211-1/+1
| | | | | | | | | The logic for parsing FP capabilities to set __ARM_FP was mistakenly removing the Half-Precision capability when handling fp-only-sp resulting in a value of 0x4. Section 6.5.1 of ACLE states that for such FP architectures the value should be 0x6 llvm-svn: 250888
* [X86] Remove a few 'else' after 'return'Craig Topper2015-10-201-7/+6
| | | | llvm-svn: 250764
* Make getTargetBuiltins return an ArrayRef instead of having two out ↵Craig Topper2015-10-191-63/+44
| | | | | | parameters of a pointer and length. NFC llvm-svn: 250681
* Recommit "Return an ArrayRef instead of having two out parameters of a ↵Craig Topper2015-10-191-178/+93
| | | | | | pointer and length. NFC". Hopefully this time the bots will be happy. llvm-svn: 250678
* Revert r250676 "Return an ArrayRef instead of having two out parameters of a ↵Craig Topper2015-10-191-93/+178
| | | | | | pointer and length. NFC" llvm-svn: 250677
* Return an ArrayRef instead of having two out parameters of a pointer and ↵Craig Topper2015-10-191-178/+93
| | | | | | length. NFC llvm-svn: 250676
* Make a bunch of static arrays const.Craig Topper2015-10-181-3/+3
| | | | llvm-svn: 250647
* [X86] Add fxsr feature name for fxsave/fxrestore builtins.Craig Topper2015-10-161-0/+18
| | | | llvm-svn: 250498
* Add support for CloudABI/aarch64.Ed Schouten2015-10-151-0/+2
| | | | | | | The core C library has already been ported over to aarch64 successfully, meaning there is no reason to hold this change back. llvm-svn: 250416
* [X86] Add command line switches for xsave/xsaveopt/xsavec/xsaves. Macro ↵Craig Topper2015-10-151-1/+48
| | | | | | defines for the same. And add the flags to correct CPU names. llvm-svn: 250368
* [X86] Use C+11 non-static data member initialization to initialize all the ↵Craig Topper2015-10-141-34/+30
| | | | | | | | X86 feature controls. NFC This simplifies the constructor initialization list and makes it less likely a feature flag will be forgotten there. llvm-svn: 250348
* Fix whitespace, 80-column violations, embedded tabs for theEric Christopher2015-10-091-15/+18
| | | | | | TargetInfo class. llvm-svn: 249872
* constify the feature vector going into initFeatureMap as it shouldn'tEric Christopher2015-10-091-24/+30
| | | | | | change the set of features. llvm-svn: 249871
* Use Triple.isAndroid() where possible.Evgeniy Stepanov2015-10-081-1/+1
| | | | llvm-svn: 249751
* Handle sse turning on mmx, but no -mmx not turning off SSE.Eric Christopher2015-10-081-11/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rationale : // sse3 __m128d test_mm_addsub_pd(__m128d A, __m128d B) { return _mm_addsub_pd(A, B); } // mmx void shift(__m64 a, __m64 b, int c) { _mm_slli_pi16(a, c); _mm_slli_pi32(a, c); _mm_slli_si64(a, c); _mm_srli_pi16(a, c); _mm_srli_pi32(a, c); _mm_srli_si64(a, c); _mm_srai_pi16(a, c); _mm_srai_pi32(a, c); } clang -msse3 -mno-mmx file.c -c For this code we should be able to explicitly turn off MMX without affecting the compilation of the SSE3 function and then diagnose and error on compiling the MMX function. This is a preparatory patch to the actual diagnosis code which is coming in a future patch. This sets us up to have the correct information where we need it and verifies that it's being emitted for the backend to handle. llvm-svn: 249733
* Migrate most feature map inclusion to initFeatureMap for the x86 target soEric Christopher2015-10-081-17/+21
| | | | | | | | that we can build up an accurate set of features rather than relying on TargetInfo initialization via handleTargetFeatures to munge the list of features. llvm-svn: 249732
* Simplify DefaultCPU in ARMTargetInfoRenato Golin2015-10-081-19/+11
| | | | | | | | | | | | | | | | | | Simplifying the convoluted CPU handling in ARMTargetInfo. The default base CPU on ARM is ARM7TDMI, arch ARMv4T, and ARMTargetInfo had a different one. This wasn't visible from Clang because the driver selects the defaults and sets the Arch/CPU features directly, but the constructor depended on the CPU, which was never used. This patch corrects the mistake and greatly simplifies how CPU is dealt with (essentially by removing the duplicated DefaultCPU field). Tests updated. llvm-svn: 249699
* The Driver does not set the +strict-align flag when targetingAlexandros Lamprineas2015-10-051-4/+0
| | | | | | | | [ARM] armv6m + netbsd. Tests are misssing for armv6m + darwin as well. Differential Revision: http://reviews.llvm.org/D13217 llvm-svn: 249308
* [mips][p5600] Add -mcpu=p5600 option.Daniel Sanders2015-10-051-0/+1
| | | | | | | | | | | | Summary: Reviewers: vkalintiris, atanasyan Subscribers: cfe-commits Differential Revision: http://reviews.llvm.org/D12234 llvm-svn: 249306
* Implement ACLE 2.0 macros of chapters 6.6 and 6.7 for [ARM] and [Aarch64] ↵Alexandros Lamprineas2015-10-021-6/+6
| | | | | | | | targets. Differential Revision: http://reviews.llvm.org/D12633 llvm-svn: 249140
* [PowerPC] Define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_* macros on all PPC coresHal Finkel2015-10-011-8/+6
| | | | | | | | | | | | We support all __sync_val_compare_and_swap_* builtins (only 64-bit on 64-bit targets) on all cores, and should define the corresponding __GCC_HAVE_SYNC_COMPARE_AND_SWAP_* macros, just as GCC does. As it turns out, this is really important because they're needed to prevent a bad ODR violation with libstdc++'s std::shared_ptr (this is well explained in PR12730). We were doing this only for P8, but this is necessary on all PPC systems. llvm-svn: 249009
* [CUDA] 32-bit NVPTX should have 32-bit long type.Artem Belevich2015-09-281-0/+1
| | | | | | | | | Currently it's 64-bit which will lead to mismatch between host and device code if we compile for i386. Differential Revision: http://reviews.llvm.org/D13181 llvm-svn: 248753
* Move the darwin define static function to be close to the OS define.Eric Christopher2015-09-241-24/+23
| | | | llvm-svn: 248539
* Use just one larger anonymous namespace instead of a lot of smaller ones.Eric Christopher2015-09-241-15/+0
| | | | llvm-svn: 248538
* Recommit r248154: [ARM] Handle DSP feature as an ArchExtKindArtyom Skrobov2015-09-241-10/+8
| | | | | | | | | | | | | | | | Currently, the availability of DSP instructions (ACLE 6.4.7) is handled in a hand-rolled tricky condition block in lib/Basic/Targets.cpp, with a FIXME: attached. http://reviews.llvm.org/D12937 moved the handling of the DSP feature over to ARMTargetParser.def in LLVM, to be in line with other architecture extensions. This is the corresponding patch to clang, to clear the FIXME: and update the tests. Differential Revision: http://reviews.llvm.org/D12938 llvm-svn: 248521
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